cocotb 1.8.1__cp39-cp39-win_amd64.whl → 1.9.0rc1__cp39-cp39-win_amd64.whl

cocotb/scheduler.py

@@ -33,6 +33,7 @@ FIXME: We have a problem here.  If a coroutine schedules a read-only but we
 also have pending writes we have to schedule the ReadWrite callback before
 the ReadOnly (and this is invalid, at least in Modelsim).
 """
+
 import inspect
 import logging
 import os
@@ -584,11 +585,6 @@ class Scheduler:
             except BaseException as e:
                 coro.log.error("Exception raised by this forked coroutine")
                 e = remove_traceback_frames(e, ["_unschedule", "get"])
-                warnings.warn(
-                    '"Unwatched" tasks that throw exceptions will not cause the test to fail. '
-                    "See issue #2664 for more details.",
-                    FutureWarning,
-                )
                 self._abort_test(e)
 
     def _schedule_write(self, handle, write_func, *args):
@@ -639,7 +635,7 @@ class Scheduler:
                 self._resume_coro_upon(
                     coro,
                     NullTrigger(
-                        name="Trigger.prime() Error", outcome=outcomes.Error(e)
+                        name="Trigger.prime() Error", _outcome=outcomes.Error(e)
                     ),
                 )
 
@@ -841,7 +837,7 @@ class Scheduler:
         self._test = test_coro
         self._resume_coro_upon(
             test_coro,
-            NullTrigger(name=f"Start {test_coro!s}", outcome=outcomes.Value(None)),
+            NullTrigger(name=f"Start {test_coro!s}", _outcome=outcomes.Value(None)),
         )
 
     # This collection of functions parses a trigger out of the object
@@ -971,7 +967,7 @@ class Scheduler:
                 except TypeError as exc:
                     # restart this coroutine with an exception object telling it that
                     # it wasn't allowed to yield that
-                    result = NullTrigger(outcome=outcomes.Error(exc))
+                    result = NullTrigger(_outcome=outcomes.Error(exc))
 
                 self._resume_coro_upon(coroutine, result)
 

cocotb/share/lib/verilator/verilator.cpp

@@ -2,7 +2,11 @@
 // Licensed under the Revised BSD License, see LICENSE for details.
 // SPDX-License-Identifier: BSD-3-Clause
 
-#include <memory>
+#include <libgen.h>  // basename
+#include <stdio.h>   // stderr, fprintf
+
+#include <memory>  // std::unique_ptr
+#include <string>  // std::string
 
 #include "Vtop.h"
 #include "verilated.h"
@@ -47,6 +51,39 @@ static inline bool settle_value_callbacks() {
 }
 
 int main(int argc, char** argv) {
+    bool traceOn = false;
+#if VM_TRACE_FST
+    const char* traceFile = "dump.fst";
+#else
+    const char* traceFile = "dump.vcd";
+#endif
+
+    for (int i = 1; i < argc; i++) {
+        std::string arg = std::string(argv[i]);
+        if (arg == "--trace") {
+            traceOn = true;
+        } else if (arg == "--trace-file") {
+            if (++i < argc) {
+                traceFile = argv[i];
+            } else {
+                fprintf(stderr, "Error: --trace-file requires a parameter\n");
+                return -1;
+            }
+        } else if (arg == "--help") {
+            fprintf(stderr,
+                    "usage: %s [--trace] [--trace-file TRACEFILE]\n"
+                    "\n"
+                    "Cocotb + Verilator sim\n"
+                    "\n"
+                    "options:\n"
+                    "  --trace      Enables tracing (VCD or FST)\n"
+                    "  --trace-file Specifies the trace file name (%s by "
+                    "default)\n",
+                    basename(argv[0]), traceFile);
+            return 0;
+        }
+    }
+
     Verilated::commandArgs(argc, argv);
 #ifdef VERILATOR_SIM_DEBUG
     Verilated::debug(99);
@@ -62,16 +99,17 @@ int main(int argc, char** argv) {
     VerilatedVpi::callCbs(cbStartOfSimulation);
 
 #if VM_TRACE
-    Verilated::traceEverOn(true);
 #if VM_TRACE_FST
     std::unique_ptr<VerilatedFstC> tfp(new VerilatedFstC);
-    top->trace(tfp.get(), 99);
-    tfp->open("dump.fst");
 #else
     std::unique_ptr<VerilatedVcdC> tfp(new VerilatedVcdC);
-    top->trace(tfp.get(), 99);
-    tfp->open("dump.vcd");
 #endif
+
+    if (traceOn) {
+        Verilated::traceEverOn(true);
+        top->trace(tfp.get(), 99);
+        tfp->open(traceFile);
+    }
 #endif
 
     while (!Verilated::gotFinish()) {
@@ -107,7 +145,9 @@ int main(int argc, char** argv) {
         VerilatedVpi::callCbs(cbReadOnlySynch);
 
 #if VM_TRACE
-        tfp->dump(main_time);
+        if (traceOn) {
+            tfp->dump(main_time);
+        }
 #endif
         // cocotb controls the clock inputs using cbAfterDelay so
         // skip ahead to the next registered callback
@@ -140,7 +180,9 @@ int main(int argc, char** argv) {
     top->final();
 
 #if VM_TRACE
-    tfp->close();
+    if (traceOn) {
+        tfp->close();
+    }
 #endif
 
 // VM_COVERAGE is a define which is set if Verilator is

cocotb/share/makefiles/Makefile.inc

@@ -37,13 +37,13 @@ COCOTB_MAKEFILE_INC_INCLUDED = 1
 .PHONY: sim
 sim:
 	$(RM) $(COCOTB_RESULTS_FILE)
-	$(MAKE) -f $(firstword $(MAKEFILE_LIST)) $(COCOTB_RESULTS_FILE)
+	"$(MAKE)" -f $(firstword $(MAKEFILE_LIST)) $(COCOTB_RESULTS_FILE)
 
 # Make sure to use bash for the pipefail option used in many simulator Makefiles
 SHELL := bash
 
-# Directory containing the cocotb Python module (realpath for Windows compatibility)
-COCOTB_PY_DIR := $(realpath $(shell cocotb-config --prefix))
+# Directory containing the cocotb Python module
+COCOTB_PY_DIR := $(shell cocotb-config --prefix)
 
 # Directory containing all support files required to build cocotb-based
 # simulations: Makefile fragments, and the simulator libraries.
@@ -62,13 +62,7 @@ export OS
 IS_VENV=$(shell $(shell cocotb-config --python-bin) -c 'import sys; print(sys.prefix != sys.base_prefix)')
 
 # this ensures we use the same python as the one cocotb was installed into
-ifeq ($(IS_VENV),True)
-    # In a virtual environment, the Python binary may be a symlink, so it should not use realpath
-    PYTHON_BIN ?= $(shell cocotb-config --python-bin)
-else
-    # realpath to convert windows paths to unix paths, like cygpath -u
-    PYTHON_BIN ?= $(realpath $(shell cocotb-config --python-bin))
-endif
+PYTHON_BIN ?= $(shell cocotb-config --python-bin)
 
 include $(COCOTB_SHARE_DIR)/makefiles/Makefile.deprecations
 

cocotb/share/makefiles/Makefile.sim

@@ -57,10 +57,10 @@ SIM                       Selects which simulator Makefile to use
 WAVES                     Enable wave traces dump for Riviera-PRO and Questa
 VERILOG_SOURCES           A list of the Verilog source files to include
 VHDL_SOURCES              A list of the VHDL source files to include
-VHDL_SOURCES_<lib>        VHDL source files to include in *lib* (GHDL/ModelSim/Questa/Xcelium/Incisive only)
-VHDL_LIB_ORDER            Compilation order of VHDL libraries (needed for ModelSim/Questa/Xcelium/Incisive)
+VHDL_SOURCES_<lib>        VHDL source files to include in *lib* (GHDL/NVC/ModelSim/Questa/Xcelium/Incisive/Riviera-PRO only)
+VHDL_LIB_ORDER            Compilation order of VHDL libraries (needed for NVC/ModelSim/Questa/Xcelium/Incisive/Riviera-PRO)
 SIM_CMD_PREFIX            Prefix for simulation command invocations
-COMPILE_ARGS              Arguments to pass to compile stage of simulation
+COMPILE_ARGS              Arguments to pass to compile (analysis) stage of simulation
 SIM_ARGS                  Arguments to pass to execution of compiled simulation
 EXTRA_ARGS                Arguments for compile and execute phases
 PLUSARGS                  Plusargs to pass to the simulator
@@ -98,8 +98,8 @@ SIM ?= icarus
 # Maintain backwards compatibility by supporting upper and lower case SIM variable
 SIM_LOWERCASE := $(shell echo $(SIM) | tr A-Z a-z)
 
-# Directory containing the cocotb Makfiles (realpath for Windows compatibility)
-COCOTB_MAKEFILES_DIR := $(realpath $(shell cocotb-config --makefiles))
+# Directory containing the cocotb Makfiles
+COCOTB_MAKEFILES_DIR := $(shell cocotb-config --makefiles)
 
 include $(COCOTB_MAKEFILES_DIR)/Makefile.deprecations
 

cocotb/share/makefiles/simulators/Makefile.activehdl

@@ -9,7 +9,7 @@ include $(shell cocotb-config --makefiles)/Makefile.inc
 CMD_BIN := vsimsa
 
 ifdef ACTIVEHDL_BIN_DIR
-    CMD := $(shell :; command -v $(realpath $(ACTIVEHDL_BIN_DIR))/$(CMD_BIN) 2>/dev/null)
+    CMD := $(shell :; command -v $(ACTIVEHDL_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
 else
     # auto-detect bin dir from system path
     CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
@@ -54,7 +54,7 @@ endif
 ifneq ($(VERILOG_SOURCES),)
 	@echo "alog $(ALOG_ARGS) $(call to_tcl_path,$(VERILOG_SOURCES))" >> $@
 endif
-	@echo "asim $(ASIM_ARGS) $(PLUSARGS) +access +w -interceptcoutput -O2 -dbg $(GPI_ARGS) $(TOPLEVEL) $(EXTRA_TOPS)" >> $@
+	@echo "asim $(ASIM_ARGS) $(PLUSARGS) +access +w_nets -interceptcoutput $(GPI_ARGS) $(TOPLEVEL) $(EXTRA_TOPS)" >> $@
 	@echo "run -all" >> $@
 	@echo "endsim" >> $@
 
@@ -62,7 +62,7 @@ $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/runsim.do $(CUSTOM_COMPILE_DEPS) $(CUSTOM_S
 	$(RM) $(COCOTB_RESULTS_FILE)
 
 	set -o pipefail; GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) $(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.do | tee $(SIM_BUILD)/sim.log
+	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) $(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.do $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.cvc

@@ -72,7 +72,7 @@ else
     $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
 	MODULE=$(MODULE) \
         TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(SIM_CMD_PREFIX) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS)
+        $(SIM_CMD_PREFIX) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
 endif
 
 # Execution phase

cocotb/share/makefiles/simulators/Makefile.ghdl

@@ -63,6 +63,34 @@ ifeq ($(OS),Msys)
     export PATH := $(GHDL_BIN_DIR)/../lib:$(PATH)
 endif
 
+GHDL_RUN_ARGS ?=
+
+ifeq ($(shell $(CMD) --version | grep -q mcode; echo $$?),0)
+    ifneq ($(COCOTB_HDL_TIMEPRECISION),)
+        # Convert the time precision to a format string supported by GHDL, if
+        # possible.
+        # GHDL only supports setting the time precision if the mcode backend is
+        # used, using the --time-resolution argument causes GHDL to error out
+        # otherwise.
+        # https://ghdl.github.io/ghdl/using/InvokingGHDL.html#cmdoption-ghdl-time-resolution
+        ifeq ($(COCOTB_HDL_TIMEPRECISION),1fs)
+            GHDL_TIME_RESOLUTION=fs
+        else ifeq ($(COCOTB_HDL_TIMEPRECISION),1ps)
+            GHDL_TIME_RESOLUTION=ps
+        else ifeq ($(COCOTB_HDL_TIMEPRECISION),1us)
+            GHDL_TIME_RESOLUTION=us
+        else ifeq ($(COCOTB_HDL_TIMEPRECISION),1ms)
+            GHDL_TIME_RESOLUTION=ms
+        else ifeq ($(COCOTB_HDL_TIMEPRECISION),1s)
+            GHDL_TIME_RESOLUTION=sec
+        else
+            $(error GHDL only supports the following values for COCOTB_HDL_TIMEPRECISION: 1fs, 1ps, 1us, 1ms, 1s)
+        endif
+
+        GHDL_RUN_ARGS += --time-resolution=$(GHDL_TIME_RESOLUTION)
+    endif
+endif
+
 .PHONY: analyse
 
 # Compilation phase
@@ -76,7 +104,7 @@ $(COCOTB_RESULTS_FILE): analyse $(CUSTOM_SIM_DEPS)
 	$(RM) $(COCOTB_RESULTS_FILE)
 
 	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-	$(SIM_CMD_PREFIX) $(CMD) -r $(GHDL_ARGS) --workdir=$(SIM_BUILD) -P$(SIM_BUILD) --work=$(RTL_LIBRARY) $(TOPLEVEL) --vpi=$(shell cocotb-config --lib-name-path vpi ghdl) $(SIM_ARGS) $(PLUSARGS)
+	$(SIM_CMD_PREFIX) $(CMD) -r $(GHDL_ARGS) $(GHDL_RUN_ARGS) --workdir=$(SIM_BUILD) -P$(SIM_BUILD) --work=$(RTL_LIBRARY) $(TOPLEVEL) $(ARCH) --vpi=$(shell cocotb-config --lib-name-path vpi ghdl) $(SIM_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.icarus

@@ -62,7 +62,7 @@ else
   TOPMODULE_ARG :=
 endif
 
-COMPILE_ARGS += -f $(SIM_BUILD)/cmds.f -g2012 # Default to latest SystemVerilog standard
+COMPILE_ARGS += -f $(SIM_BUILD)/cmds.f
 
 ifdef VERILOG_INCLUDE_DIRS
     COMPILE_ARGS += $(addprefix -I, $(VERILOG_INCLUDE_DIRS))
@@ -78,7 +78,7 @@ endif
 
 $(SIM_BUILD)/sim.vvp: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
 	@echo "+timescale+$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)" > $(SIM_BUILD)/cmds.f
-	$(CMD) -o $(SIM_BUILD)/sim.vvp -D COCOTB_SIM=1 $(TOPMODULE_ARG) $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+	$(CMD) -o $(SIM_BUILD)/sim.vvp -D COCOTB_SIM=1 $(TOPMODULE_ARG) -g2012 $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
 
 $(SIM_BUILD)/cocotb_iverilog_dump.v: | $(SIM_BUILD)
 	@echo 'module cocotb_iverilog_dump();' > $@
@@ -94,7 +94,7 @@ $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
 	$(RM) $(COCOTB_RESULTS_FILE)
 
 	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(SIM_CMD_PREFIX) $(ICARUS_BIN_DIR)/vvp -M $(shell cocotb-config --lib-dir) -m $(shell cocotb-config --lib-name vpi icarus) $(SIM_ARGS) $(EXTRA_ARGS) $(SIM_BUILD)/sim.vvp $(PLUSARGS)
+        $(SIM_CMD_PREFIX) $(ICARUS_BIN_DIR)/vvp -M $(shell cocotb-config --lib-dir) -m $(shell cocotb-config --lib-name vpi icarus) $(SIM_ARGS) $(EXTRA_ARGS) $(SIM_BUILD)/sim.vvp $(PLUSARGS) $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 
@@ -102,7 +102,7 @@ debug: $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
 	$(RM) -r $(COCOTB_RESULTS_FILE)
 
 	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(SIM_CMD_PREFIX) gdb --args $(ICARUS_BIN_DIR)/vvp $(shell cocotb-config --lib-dir) -m $(shell cocotb-config --lib-name vpi icarus) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS)
+        $(SIM_CMD_PREFIX) gdb --args $(ICARUS_BIN_DIR)/vvp $(shell cocotb-config --lib-dir) -m $(shell cocotb-config --lib-name vpi icarus) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.ius

@@ -114,7 +114,7 @@ $(COCOTB_RESULTS_FILE): $(HDL_SOURCES) $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS)
 	set -o pipefail; \
 	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
 	$(SIM_CMD_PREFIX) $(CMD) -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
-	$(EXTRA_ARGS) $(GPI_ARGS) +access+rwc $(LIBS) $(MAKE_LIB) $(HDL_SOURCES) $(PLUSARGS) 2>&1 | tee $(SIM_BUILD)/sim.log
+	$(EXTRA_ARGS) $(GPI_ARGS) +access+rwc $(LIBS) $(MAKE_LIB) $(HDL_SOURCES) $(PLUSARGS) $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.nvc

@@ -0,0 +1,64 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+include $(shell cocotb-config --makefiles)/Makefile.inc
+
+ifneq ($(VERILOG_SOURCES),)
+
+$(COCOTB_RESULTS_FILE):
+	@echo "Skipping simulation as Verilog is not supported on simulator=$(SIM)"
+clean::
+
+else
+
+CMD_BIN := nvc
+
+ifdef NVC_BIN_DIR
+    CMD := $(shell :; command -v $(NVC_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+endif
+
+ifeq (, $(CMD))
+    $(error "Unable to locate command >$(CMD_BIN)<")
+else
+    NVC_BIN_DIR := $(shell dirname $(CMD))
+    export NVC_BIN_DIR
+endif
+
+RTL_LIBRARY ?= work
+
+.PHONY: analyse
+
+# Split SIM_ARGS into those options that need to be passed to -e and
+# those that need to be passed to -r
+NVC_E_FILTER := -g% --cover --cover=%
+
+NVC_E_ARGS := $(filter $(NVC_E_FILTER),$(SIM_ARGS))
+NVC_R_ARGS := $(filter-out $(NVC_E_FILTER),$(SIM_ARGS))
+
+# Compilation phase
+analyse: $(VHDL_SOURCES) $(SIM_BUILD) $(CUSTOM_COMPILE_DEPS)
+	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
+	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
+
+	$(foreach LIB_VAR,$(VHDL_LIB_ORDER), \
+		$(CMD) $(EXTRA_ARGS) --work=$(LIB_VAR):$(SIM_BUILD)/$(LIB_VAR) -L $(SIM_BUILD) -a $(VHDL_SOURCES_$(LIB_VAR)) $(COMPILE_ARGS) && ) \
+	$(CMD) $(EXTRA_ARGS) --work=$(RTL_LIBRARY):$(SIM_BUILD)/$(RTL_LIBRARY) -L $(SIM_BUILD) -a $(VHDL_SOURCES) $(COMPILE_ARGS)
+
+$(COCOTB_RESULTS_FILE): analyse $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	TESTCASE=$(TESTCASE) MODULE=$(MODULE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	  $(SIM_CMD_PREFIX) $(CMD) $(EXTRA_ARGS) --work=$(RTL_LIBRARY):$(SIM_BUILD)/$(RTL_LIBRARY) -L $(SIM_BUILD) \
+	  -e $(TOPLEVEL) --no-save $(NVC_E_ARGS) \
+	  -r --load $(shell cocotb-config --lib-name-path vhpi nvc) $(TRACE) $(NVC_R_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
+
+	$(call check_for_results_file)
+
+clean::
+	$(RM) -r $(SIM_BUILD)
+endif

cocotb/share/makefiles/simulators/Makefile.questa

@@ -160,7 +160,7 @@ $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/runsim.do
 
 	set -o pipefail; MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) \
 	GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-	$(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.do $(PLUSARGS) 2>&1 | tee $(SIM_BUILD)/sim.log
+	$(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.do $(PLUSARGS) $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.riviera

@@ -69,9 +69,11 @@ ASIM_ARGS += $(SIM_ARGS)
 # Plusargs need to be passed to ASIM command not vsimsa
 ASIM_ARGS += $(PLUSARGS)
 
-RTL_LIBRARY ?= $(SIM_BUILD)/work
-ALOG_ARGS += +define+COCOTB_SIM -dbg -pli libgpi
-ACOM_ARGS += -dbg
+RTL_LIBRARY ?= work
+ALOG_ARGS += +define+COCOTB_SIM
+
+# Pass the VPI library to the Verilog compilation to get extended checking.
+ALOG_ARGS += -pli $(shell cocotb-config --lib-name-path vpi riviera)
 
 # Aldec-specific coverage types:
 # - (s)tatement
@@ -84,8 +86,10 @@ ACOM_ARGS += -dbg
 # Documentation: Riviera Pro 2017.02 Documentation - Page 359
 COVERAGE_TYPES ?= sb
 ifeq ($(COVERAGE),1)
-    ASIM_ARGS += -acdb -acdb_cov $(COVERAGE_TYPES)
-    ALOG_ARGS += -coverage $(COVERAGE_TYPES)
+    ALOG_ARGS += -dbg -coverage $(COVERAGE_TYPES)
+    ACOM_ARGS += -dbg -coverage $(COVERAGE_TYPES)
+
+    ASIM_ARGS += -dbg -acdb -acdb_cov $(COVERAGE_TYPES)
 endif
 
 GPI_EXTRA:=
@@ -105,30 +109,41 @@ else
    $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
 endif
 
+define make_lib
+  echo "if [file exists $(SIM_BUILD)/$(LIB)] {adel -lib $(SIM_BUILD)/$(LIB) -all}" >> $@;
+  echo "alib $(SIM_BUILD)/$(LIB)" >> $@;
+  echo "amap $(LIB) $(SIM_BUILD)/$(LIB)" >> $@;
+  echo "acom -work $(LIB) $(VCOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES_$(LIB)))" >> $@;
+endef
+
 # Create a TCL script based on the list of $(VERILOG_SOURCES)
 $(SIM_BUILD)/runsim.tcl : $(VERILOG_SOURCES) $(VHDL_SOURCES) | $(SIM_BUILD)
 	@echo "onerror {" > $@
 	@echo "	puts [read [open sim.log r]]" >> $@
 	@echo "	quit -code 1" >> $@
 	@echo "}" >> $@
+	@echo "amap -c" >> $@
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(make_lib))
 	@echo "@if [string length [array get env LICENSE_QUEUE]] {" >> $@
 	@echo " set LICENSE_QUEUE $$::env(LICENSE_QUEUE)" >> $@
 	@echo "}" >> $@
-	@echo "alib $(RTL_LIBRARY)" >> $@
-	@echo "set worklib $(RTL_LIBRARY)" >> $@
+	@echo "if [file exists $(SIM_BUILD)/$(RTL_LIBRARY)] {adel -lib $(SIM_BUILD)/$(RTL_LIBRARY) -all}" >> $@;
+	@echo "alib $(SIM_BUILD)/$(RTL_LIBRARY)" >> $@
+	@echo "amap $(RTL_LIBRARY) $(SIM_BUILD)/$(RTL_LIBRARY)" >> $@;
+	@echo "set worklib $(RTL_LIBRARY)" >> $@;
 ifneq ($(VHDL_SOURCES),)
-	@echo "acom $(ACOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES))" >> $@
+	@echo "acom -work $(RTL_LIBRARY) $(ACOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES))" >> $@
 endif
 ifneq ($(VERILOG_SOURCES),)
-	@echo "alog $(ALOG_ARGS) $(call to_tcl_path,$(VERILOG_SOURCES))" >> $@
+	@echo "alog -work $(RTL_LIBRARY) $(ALOG_ARGS) $(call to_tcl_path,$(VERILOG_SOURCES))" >> $@
 endif
 ifdef SCRIPT_FILE
 	@echo "do $(SCRIPT_FILE)" >> $@
 endif
 ifneq ($(CFG_TOPLEVEL),)
-	@echo "asim $(ASIM_ARGS) +access +w -interceptcoutput -O2 -dbg $(GPI_ARGS) $(CFG_TOPLEVEL) $(EXTRA_TOPS)" >> $@
+	@echo "asim $(ASIM_ARGS) +access +w_nets -interceptcoutput $(GPI_ARGS) $(CFG_TOPLEVEL) $(EXTRA_TOPS)" >> $@
 else
-	@echo "asim $(ASIM_ARGS) +access +w -interceptcoutput -O2 -dbg $(GPI_ARGS) $(TOPLEVEL) $(EXTRA_TOPS)" >> $@
+	@echo "asim $(ASIM_ARGS) +access +w_nets -interceptcoutput $(GPI_ARGS) $(TOPLEVEL) $(EXTRA_TOPS)" >> $@
 endif
 ifeq ($(WAVES),1)
 	@echo "log -recursive *" >> $@
@@ -142,6 +157,7 @@ ifeq ($(COVERAGE),1)
 	@echo "acdb report -cov $(COVERAGE_TYPES) -db $(RTL_LIBRARY).acdb -html -o coverage/acdb_report.html" >> $@
 	@echo "acdb report -cov $(COVERAGE_TYPES) -db $(RTL_LIBRARY).acdb -txt -o coverage/acdb_report.txt" >> $@
 endif
+	@echo "exit" >> $@
 endif
 
 # Note it's the redirection of the output rather than the 'do' command
@@ -150,7 +166,7 @@ $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/runsim.tcl $(CUSTOM_COMPILE_DEPS) $(CUSTOM_
 	$(RM) $(COCOTB_RESULTS_FILE)
 
 	set -o pipefail; GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) $(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.tcl | tee $(SIM_BUILD)/sim.log
+	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) $(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.tcl $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.vcs

@@ -77,7 +77,7 @@ $(SIM_BUILD)/pli.tab : | $(SIM_BUILD)
 $(SIM_BUILD)/simv: $(VERILOG_SOURCES) $(SIM_BUILD)/pli.tab $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
 	cd $(SIM_BUILD) && \
 	TOPLEVEL=$(TOPLEVEL) \
-	$(CMD) -top $(TOPLEVEL) $(PLUSARGS) +acc+1 +vpi -P pli.tab +define+COCOTB_SIM=1 -sverilog \
+	$(CMD) -top $(TOPLEVEL) $(PLUSARGS) -debug_access+r+w-memcbk -debug_region+cell +vpi -P pli.tab +define+COCOTB_SIM=1 -sverilog \
 	-timescale=$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
 	$(EXTRA_ARGS) -debug -load $(shell cocotb-config --lib-name-path vpi vcs) $(COMPILE_ARGS) $(VERILOG_SOURCES)
 
@@ -86,7 +86,7 @@ $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/simv $(CUSTOM_SIM_DEPS)
 	$(RM) $(COCOTB_RESULTS_FILE)
 
 	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-	$(SIM_CMD_PREFIX) $(SIM_BUILD)/simv +define+COCOTB_SIM=1 $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS)
+	$(SIM_CMD_PREFIX) $(SIM_BUILD)/simv +define+COCOTB_SIM=1 $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.verilator

@@ -15,11 +15,17 @@ clean::
 
 else
 
-CMD := verilator
+CMD_BIN := verilator
 
-ifeq ($(shell which $(CMD) 2>/dev/null),)
-# Verilator is not in PATH, lets start searching for it
-$(error Cannot find verilator.)
+ifdef VERILATOR_BIN_DIR
+  CMD := $(shell :; command -v $(VERILATOR_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+  # auto-detect bin dir from system path
+  CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+endif
+
+ifeq (, $(CMD))
+  $(error Unable to locate command >$(CMD_BIN)<)
 endif
 
 VLT_MIN := 4.106
@@ -64,7 +70,7 @@ $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/Vtop $(CUSTOM_SIM_DEPS)
 	$(RM) $(COCOTB_RESULTS_FILE)
 
 	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(SIM_CMD_PREFIX) $< $(PLUSARGS)
+        $(SIM_CMD_PREFIX) $< $(PLUSARGS) $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.xcelium

@@ -97,8 +97,12 @@ ifeq ($(TOPLEVEL_LANG),verilog)
 else ifeq ($(TOPLEVEL_LANG),vhdl)
     GPI_EXTRA = $(shell cocotb-config --lib-name-path vhpi xcelium):cocotbvhpi_entry_point
     EXTRA_ARGS += -top $(TOPLEVEL)
+    # Xcelium 23.09.004 fixes cocotb issue #1076 as long as the following define
+    # is set.
+    EXTRA_ARGS += -NEW_VHPI_PROPAGATE_DELAY
     RTL_LIBRARY ?= $(TOPLEVEL)
     MAKE_LIB = -makelib $(RTL_LIBRARY)
+    END_LIB = -endlib
     HDL_SOURCES = $(VHDL_SOURCES)
     ifneq ($(VERILOG_SOURCES),)
         HDL_SOURCES += $(VERILOG_SOURCES)
@@ -120,7 +124,8 @@ $(COCOTB_RESULTS_FILE): $(HDL_SOURCES) $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS)
 	set -o pipefail; \
 	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
 	$(SIM_CMD_PREFIX) $(CMD) -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
-	$(EXTRA_ARGS) $(GPI_ARGS) $(INCDIRS) -access +rwc -createdebugdb $(LIBS) $(MAKE_LIB) $(HDL_SOURCES) $(PLUSARGS) 2>&1 | tee $(SIM_BUILD)/sim.log
+	-vhdl_time_precision "$(COCOTB_HDL_TIMEPRECISION)" \
+	$(EXTRA_ARGS) $(GPI_ARGS) $(INCDIRS) -access +rwc -createdebugdb $(LIBS) $(MAKE_LIB) $(HDL_SOURCES) $(END_LIB) $(PLUSARGS) $(SIM_CMD_SUFFIX)
 
 	$(call check_for_results_file)