cocotb 1.7.2__cp310-cp310-win32.whl → 1.8.0rc1__cp310-cp310-win32.whl

cocotb/scheduler.py

@@ -47,9 +47,9 @@ import cocotb
 import cocotb.decorators
 from cocotb import _py_compat, outcomes
 from cocotb._deprecation import deprecated
-from cocotb.decorators import Task
 from cocotb.log import SimLog
 from cocotb.result import TestComplete
+from cocotb.task import Task
 from cocotb.triggers import (
     Event,
     GPITrigger,
@@ -76,7 +76,7 @@ if _profiling:
 _debug = "COCOTB_SCHEDULER_DEBUG" in os.environ
 
 
-class InternalError(RuntimeError):
+class InternalError(BaseException):
     """An error internal to scheduler. If you see this, report a bug!"""
 
     pass
@@ -265,6 +265,7 @@ class Scheduler:
         self._pending_triggers = []
         self._pending_threads = []
         self._pending_events = []  # Events we need to call set on once we've unwound
+        self._scheduling = []
 
         self._terminate = False
         self._test = None
@@ -437,7 +438,7 @@ class Scheduler:
                 # Scheduled coroutines may append to our waiting list so the first
                 # thing to do is pop all entries waiting on this trigger.
                 try:
-                    scheduling = self._trigger2coros.pop(trigger)
+                    self._scheduling = self._trigger2coros.pop(trigger)
                 except KeyError:
                     # GPI triggers should only be ever pending if there is an
                     # associated coroutine waiting on that trigger, otherwise it would
@@ -463,19 +464,19 @@ class Scheduler:
 
                 if _debug:
                     debugstr = "\n\t".join(
-                        [coro._coro.__qualname__ for coro in scheduling]
+                        [coro._coro.__qualname__ for coro in self._scheduling]
                     )
-                    if len(scheduling) > 0:
+                    if len(self._scheduling) > 0:
                         debugstr = "\n\t" + debugstr
                     self.log.debug(
                         "%d pending coroutines for event %s%s"
-                        % (len(scheduling), str(trigger), debugstr)
+                        % (len(self._scheduling), str(trigger), debugstr)
                     )
 
                 # This trigger isn't needed any more
                 trigger.unprime()
 
-                for coro in scheduling:
+                for coro in self._scheduling:
                     if coro._outcome is not None:
                         # coroutine was killed by another coroutine waiting on the same trigger
                         continue
@@ -494,6 +495,8 @@ class Scheduler:
                     # happened in gh-957)
                     del coro
 
+                self._scheduling = []
+
                 # Handle any newly queued coroutines that need to be scheduled
                 while self._pending_coros:
                     task = self._pending_coros.pop(0)
@@ -522,7 +525,6 @@ class Scheduler:
                 # to try and avoid them being destroyed at a weird time (as
                 # happened in gh-957)
                 del trigger
-                del scheduling
 
             # no more pending triggers
             self._check_termination()
@@ -579,7 +581,7 @@ class Scheduler:
                 coro.log.info("Test stopped by this forked coroutine")
                 e = remove_traceback_frames(e, ["_unschedule", "get"])
                 self._abort_test(e)
-            except Exception as e:
+            except BaseException as e:
                 coro.log.error("Exception raised by this forked coroutine")
                 e = remove_traceback_frames(e, ["_unschedule", "get"])
                 warnings.warn(
@@ -621,7 +623,6 @@ class Scheduler:
             trigger_coros.append(coro)
 
         if not trigger.primed:
-
             if trigger_coros != [coro]:
                 # should never happen
                 raise InternalError(
@@ -696,7 +697,7 @@ class Scheduler:
             event.set()
 
         event = threading.Event()
-        self._pending_coros.append(cocotb.decorators.Task(wrapper()))
+        self._pending_coros.append(Task(wrapper()))
         # The scheduler thread blocks in `thread_wait`, and is woken when we
         # call `thread_suspend` - so we need to make sure the coroutine is
         # queued before that.
@@ -849,14 +850,14 @@ class Scheduler:
     # Doing them as separate functions allows us to avoid repeating unnecessary
     # `isinstance` checks.
 
-    def _trigger_from_started_coro(self, result: cocotb.decorators.Task) -> Trigger:
+    def _trigger_from_started_coro(self, result: Task) -> Trigger:
         if _debug:
             self.log.debug(
                 "Joining to already running coroutine: %s" % result._coro.__qualname__
             )
         return result.join()
 
-    def _trigger_from_unstarted_coro(self, result: cocotb.decorators.Task) -> Trigger:
+    def _trigger_from_unstarted_coro(self, result: Task) -> Trigger:
         self._queue(result)
         if _debug:
             self.log.debug(
@@ -865,7 +866,7 @@ class Scheduler:
         return result.join()
 
     def _trigger_from_waitable(self, result: cocotb.triggers.Waitable) -> Trigger:
-        return self._trigger_from_unstarted_coro(cocotb.decorators.Task(result._wait()))
+        return self._trigger_from_unstarted_coro(Task(result._wait()))
 
     def _trigger_from_list(self, result: list) -> Trigger:
         return self._trigger_from_waitable(cocotb.triggers.First(*result))
@@ -877,14 +878,14 @@ class Scheduler:
         if isinstance(result, Trigger):
             return result
 
-        if isinstance(result, cocotb.decorators.Task):
+        if isinstance(result, Task):
             if not result.has_started():
                 return self._trigger_from_unstarted_coro(result)
             else:
                 return self._trigger_from_started_coro(result)
 
         if inspect.iscoroutine(result):
-            return self._trigger_from_unstarted_coro(cocotb.decorators.Task(result))
+            return self._trigger_from_unstarted_coro(Task(result))
 
         if isinstance(result, list):
             return self._trigger_from_list(result)
@@ -979,7 +980,6 @@ class Scheduler:
             # where a sim might change what this thread is.
 
             if self._main_thread is threading.current_thread():
-
                 for ext in self._pending_threads:
                     ext.thread_start()
                     if _debug:
@@ -1062,7 +1062,7 @@ class Scheduler:
         Unprime all pending triggers and kill off any coroutines, stop all externals.
         """
         # copy since we modify this in kill
-        items = list(self._trigger2coros.items())
+        items = list((k, list(v)) for k, v in self._trigger2coros.items())
 
         # reversing seems to fix gh-928, although the order is still somewhat
         # arbitrary.
@@ -1071,10 +1071,27 @@ class Scheduler:
                 if _debug:
                     self.log.debug("Killing %s" % str(coro))
                 coro.kill()
+        assert not self._trigger2coros
+
+        # if there are coroutines being scheduled when the test ends, kill them (gh-1347)
+        for coro in self._scheduling:
+            if _debug:
+                self.log.debug("Killing %s" % str(coro))
+            coro.kill()
+        self._scheduling = []
+
+        # cancel outstanding triggers *before* queued coroutines (gh-3270)
+        while self._pending_triggers:
+            trigger = self._pending_triggers.pop(0)
+            if _debug:
+                self.log.debug("Unpriming %r", trigger)
+            trigger.unprime()
+        assert not self._pending_triggers
 
         # kill any queued coroutines
         for task in self._pending_coros:
             task.kill()
+        assert not self._pending_coros
 
         if self._main_thread is not threading.current_thread():
             raise Exception("Cleanup() called outside of the main thread")

cocotb/share/def/modelsim.def

@@ -93,6 +93,8 @@ mti_Now
 mti_NowUpper
 mti_Quit
 mti_ReleaseSignal
+mti_RemoveLoadDoneCB
+mti_RemoveQuitCB
 mti_ScheduleWakeup
 mti_ScheduleWakeup64
 mti_Sensitize

cocotb/share/include/embed.h

@@ -47,8 +47,7 @@ extern COCOTB_EMBED_EXPORT void embed_init_python(void);
 extern COCOTB_EMBED_EXPORT void embed_sim_cleanup(void);
 extern COCOTB_EMBED_EXPORT int embed_sim_init(int argc,
                                               char const* const* argv);
-extern COCOTB_EMBED_EXPORT void embed_sim_event(gpi_event_t level,
-                                                const char* msg);
+extern COCOTB_EMBED_EXPORT void embed_sim_event(const char* msg);
 
 #ifdef __cplusplus
 }

cocotb/share/include/gpi.h

@@ -101,12 +101,6 @@ typedef struct GpiIterator *gpi_iterator_hdl;
 extern "C" {
 #endif
 
-typedef enum gpi_event_e {
-    SIM_INFO = 0,
-    SIM_TEST_FAIL = 1,
-    SIM_FAIL = 2,
-} gpi_event_t;
-
 // Functions for controlling/querying the simulation state
 
 /**
@@ -242,17 +236,18 @@ typedef enum gpi_edge {
 } gpi_edge_e;
 
 // The callback registering functions
-GPI_EXPORT gpi_cb_hdl gpi_register_timed_callback(
-    int (*gpi_function)(const void *), void *gpi_cb_data, uint64_t time);
+GPI_EXPORT gpi_cb_hdl gpi_register_timed_callback(int (*gpi_function)(void *),
+                                                  void *gpi_cb_data,
+                                                  uint64_t time);
 GPI_EXPORT gpi_cb_hdl gpi_register_value_change_callback(
-    int (*gpi_function)(const void *), void *gpi_cb_data, gpi_sim_hdl gpi_hdl,
+    int (*gpi_function)(void *), void *gpi_cb_data, gpi_sim_hdl gpi_hdl,
     int edge);
-GPI_EXPORT gpi_cb_hdl gpi_register_readonly_callback(
-    int (*gpi_function)(const void *), void *gpi_cb_data);
-GPI_EXPORT gpi_cb_hdl gpi_register_nexttime_callback(
-    int (*gpi_function)(const void *), void *gpi_cb_data);
-GPI_EXPORT gpi_cb_hdl gpi_register_readwrite_callback(
-    int (*gpi_function)(const void *), void *gpi_cb_data);
+GPI_EXPORT gpi_cb_hdl
+gpi_register_readonly_callback(int (*gpi_function)(void *), void *gpi_cb_data);
+GPI_EXPORT gpi_cb_hdl
+gpi_register_nexttime_callback(int (*gpi_function)(void *), void *gpi_cb_data);
+GPI_EXPORT gpi_cb_hdl
+gpi_register_readwrite_callback(int (*gpi_function)(void *), void *gpi_cb_data);
 
 // Calling convention is that 0 = success and negative numbers a failure
 // For implementers of GPI the provided macro GPI_RET(x) is provided

cocotb/share/include/vpi_user_ext.h

@@ -34,6 +34,9 @@
 extern "C" {
 #endif
 
+/* used by Cadence Xcelium for packed unions */
+#define vpiUnionNet          525
+
 /* used by Cadence Xcelium for Verilog-AMS */
 #define vpiRealNet           526
 #define vpiInterconnectNet   533

cocotb/share/lib/verilator/verilator.cpp

@@ -88,7 +88,7 @@ int main(int argc, char** argv) {
         bool again = true;
         while (again) {
             // Evaluate design
-            top->eval();
+            top->eval_step();
 
             // Call Value Change callbacks triggered by eval()
             // These can modify signal values
@@ -101,6 +101,7 @@ int main(int argc, char** argv) {
             // These can modify signal values
             again |= settle_value_callbacks();
         }
+        top->eval_end_step();
 
         // Call ReadOnly callbacks
         VerilatedVpi::callCbs(cbReadOnlySynch);
@@ -110,12 +111,15 @@ int main(int argc, char** argv) {
 #endif
         // cocotb controls the clock inputs using cbAfterDelay so
         // skip ahead to the next registered callback
-        vluint64_t next_time = VerilatedVpi::cbNextDeadline();
+        const vluint64_t NO_TOP_EVENTS_PENDING = static_cast<vluint64_t>(~0ULL);
+        vluint64_t next_time_cocotb = VerilatedVpi::cbNextDeadline();
+        vluint64_t next_time_timing =
+            top->eventsPending() ? top->nextTimeSlot() : NO_TOP_EVENTS_PENDING;
+        vluint64_t next_time = std::min(next_time_cocotb, next_time_timing);
 
         // If there are no more cbAfterDelay callbacks,
         // the next deadline is max value, so end the simulation now
-        if (next_time == static_cast<vluint64_t>(~0ULL)) {
-            vl_finish(__FILE__, __LINE__, "");
+        if (next_time == NO_TOP_EVENTS_PENDING) {
             break;
         } else {
             main_time = next_time;

cocotb/share/makefiles/Makefile.inc

@@ -57,9 +57,18 @@ else ifneq (, $(findstring MSYS, $(OS)))
 endif
 export OS
 
+# Detects if Python is running in a virtual environment
+# https://docs.python.org/3/library/venv.html
+IS_VENV=$(shell $(shell cocotb-config --python-bin) -c 'import sys; print(sys.prefix != sys.base_prefix)')
+
 # this ensures we use the same python as the one cocotb was installed into
-# realpath to convert windows paths to unix paths, like cygpath -u
-PYTHON_BIN ?= $(realpath $(shell cocotb-config --python-bin))
+ifeq ($(IS_VENV),True)
+    # In a virtual environment, the Python binary may be a symlink, so it should not use realpath
+    PYTHON_BIN ?= $(shell cocotb-config --python-bin)
+else
+    # realpath to convert windows paths to unix paths, like cygpath -u
+    PYTHON_BIN ?= $(realpath $(shell cocotb-config --python-bin))
+endif
 
 include $(COCOTB_SHARE_DIR)/makefiles/Makefile.deprecations
 
@@ -70,8 +79,11 @@ ifeq ($(filter $(PYTHON_ARCH),64bit 32bit),)
     $(error Unknown Python architecture: $(PYTHON_ARCH))
 endif
 
-# Set PYTHONHOME to properly populate sys.path in embedded python interpreter
-export PYTHONHOME := $(shell $(PYTHON_BIN) -c 'import sys; print(sys.prefix)')
+# Changing PYTHONHOME confuses virtual environments, so only set it when not using a venv
+ifeq ($(IS_VENV),False)
+    # Set PYTHONHOME to properly populate sys.path in embedded python interpreter
+    export PYTHONHOME := $(shell $(PYTHON_BIN) -c 'import sys; print(sys.prefix)')
+endif
 
 ifeq ($(OS),Msys)
     to_tcl_path = $(shell cygpath -m $(1) )

cocotb/share/makefiles/Makefile.sim

@@ -57,8 +57,8 @@ SIM                       Selects which simulator Makefile to use
 WAVES                     Enable wave traces dump for Riviera-PRO and Questa
 VERILOG_SOURCES           A list of the Verilog source files to include
 VHDL_SOURCES              A list of the VHDL source files to include
-VHDL_SOURCES_<lib>        VHDL source files to include in *lib* (GHDL/ModelSim/Questa/Xcelium only)
-VHDL_LIB_ORDER            Compilation order of VHDL libraries (needed for ModelSim/Questa/Xcelium)
+VHDL_SOURCES_<lib>        VHDL source files to include in *lib* (GHDL/ModelSim/Questa/Xcelium/Incisive only)
+VHDL_LIB_ORDER            Compilation order of VHDL libraries (needed for ModelSim/Questa/Xcelium/Incisive)
 SIM_CMD_PREFIX            Prefix for simulation command invocations
 COMPILE_ARGS              Arguments to pass to compile stage of simulation
 SIM_ARGS                  Arguments to pass to execution of compiled simulation

cocotb/share/makefiles/simulators/Makefile.icarus

@@ -64,11 +64,30 @@ endif
 
 COMPILE_ARGS += -f $(SIM_BUILD)/cmds.f -g2012 # Default to latest SystemVerilog standard
 
+ifdef VERILOG_INCLUDE_DIRS
+    COMPILE_ARGS += $(addprefix -I, $(VERILOG_INCLUDE_DIRS))
+endif
+
 # Compilation phase
+
+ifeq ($(WAVES), 1)
+    VERILOG_SOURCES += $(SIM_BUILD)/cocotb_iverilog_dump.v
+    COMPILE_ARGS += -s cocotb_iverilog_dump
+    PLUSARGS += -fst
+endif
+
 $(SIM_BUILD)/sim.vvp: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
 	@echo "+timescale+$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)" > $(SIM_BUILD)/cmds.f
 	$(CMD) -o $(SIM_BUILD)/sim.vvp -D COCOTB_SIM=1 $(TOPMODULE_ARG) $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
 
+$(SIM_BUILD)/cocotb_iverilog_dump.v: | $(SIM_BUILD)
+	@echo 'module cocotb_iverilog_dump();' > $@
+	@echo 'initial begin' >> $@
+	@echo '    $$dumpfile("$(SIM_BUILD)/$(TOPLEVEL).fst");' >> $@
+	@echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
+	@echo 'end' >> $@
+	@echo 'endmodule' >> $@
+
 # Execution phase
 
 $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)

cocotb/share/makefiles/simulators/Makefile.ius

@@ -47,6 +47,10 @@ else
     export IUS_BIN_DIR
 endif
 
+ifdef VERILOG_INCLUDE_DIRS
+    COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
 EXTRA_ARGS += $(COMPILE_ARGS)
 EXTRA_ARGS += $(SIM_ARGS)
 EXTRA_ARGS += -licqueue
@@ -97,13 +101,20 @@ else
    $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
 endif
 
+# Builds a list of arguments to support VHDL libraries specified in VHDL_SOURCES_*:
+LIBS := $(foreach LIB, $(VHDL_LIB_ORDER),-makelib $(LIB) $(VHDL_SOURCES_$(LIB)) -endlib)
+
 $(COCOTB_RESULTS_FILE): $(HDL_SOURCES) $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS) | $(SIM_BUILD)
 	$(RM) $(COCOTB_RESULTS_FILE)
 
+	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
+	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
+
 	set -o pipefail; \
 	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
 	$(SIM_CMD_PREFIX) $(CMD) -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
-	$(EXTRA_ARGS) $(GPI_ARGS) +access+rwc $(MAKE_LIB) $(HDL_SOURCES) $(PLUSARGS) 2>&1 | tee $(SIM_BUILD)/sim.log
+	$(EXTRA_ARGS) $(GPI_ARGS) +access+rwc $(LIBS) $(MAKE_LIB) $(HDL_SOURCES) $(PLUSARGS) 2>&1 | tee $(SIM_BUILD)/sim.log
 
 	$(call check_for_results_file)
 

cocotb/share/makefiles/simulators/Makefile.questa

@@ -54,7 +54,7 @@ endif
 COMPILE_ARGS += +acc
 
 ifdef VERILOG_INCLUDE_DIRS
-    VLOG_ARGS += +incdir+$(VERILOG_INCLUDE_DIRS)
+    VLOG_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
 endif
 
 # below allows for maintaining legacy syntax as well as enables using cross-simulator vars COMPILE_ARGS/SIM_ARGS
@@ -88,6 +88,7 @@ ifeq ($(filter vhpi fli,$(VHDL_GPI_INTERFACE)),)
 endif
 
 ifeq ($(TOPLEVEL_LANG),vhdl)
+    VSIM_ARGS += -t $(COCOTB_HDL_TIMEPRECISION)
 ifeq ($(VHDL_GPI_INTERFACE),fli)
     CUSTOM_COMPILE_DEPS += $(FLI_LIB)
     VSIM_ARGS += -foreign \"cocotb_init $(FLI_LIB)\"

cocotb/share/makefiles/simulators/Makefile.riviera

@@ -57,6 +57,10 @@ endif
 
 ALOG_ARGS += -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)
 
+ifdef VERILOG_INCLUDE_DIRS
+    ALOG_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
 # below allows for maintaining legacy syntax as well as enables using cross-simulator vars COMPILE_ARGS/SIM_ARGS
 ALOG_ARGS += $(COMPILE_ARGS)
 ACOM_ARGS += $(COMPILE_ARGS)

cocotb/share/makefiles/simulators/Makefile.vcs

@@ -53,6 +53,10 @@ else
      export VCS_BIN_DIR
 endif
 
+ifdef VERILOG_INCLUDE_DIRS
+    COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
 ifeq ($(PYTHON_ARCH),64bit)
     EXTRA_ARGS += -full64
 endif

cocotb/share/makefiles/simulators/Makefile.verilator

@@ -36,7 +36,7 @@ else
 endif
 
 ifeq ($(VERILATOR_SIM_DEBUG), 1)
-  COMPILE_ARGS += --debug -CFLAGS "-DVL_DEBUG -g"
+  COMPILE_ARGS += --debug -CFLAGS "-DVL_DEBUG -DVERILATOR_SIM_DEBUG -g"
   PLUSARGS += +verilator+debug
   BUILD_ARGS += OPT_FAST=-Og OPT_SLOW=-Og OPT_GLOBAL=-Og
 endif
@@ -49,6 +49,10 @@ EXTRA_ARGS += --timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)
 
 COMPILE_ARGS += --vpi --public-flat-rw --prefix Vtop -o Vtop -LDFLAGS "-Wl,-rpath,$(shell cocotb-config --lib-dir) -L$(shell cocotb-config --lib-dir) -lcocotbvpi_verilator"
 
+ifdef VERILOG_INCLUDE_DIRS
+  COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
 $(SIM_BUILD)/Vtop.mk: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) $(COCOTB_SHARE_DIR)/lib/verilator/verilator.cpp | $(SIM_BUILD)
 	$(CMD) -cc --exe -Mdir $(SIM_BUILD) -DCOCOTB_SIM=1 $(TOPMODULE_ARG) $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES) $(COCOTB_SHARE_DIR)/lib/verilator/verilator.cpp
 

cocotb/share/makefiles/simulators/Makefile.xcelium

@@ -47,6 +47,10 @@ else
     export XCELIUM_BIN_DIR
 endif
 
+ifdef VERILOG_INCLUDE_DIRS
+    COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
 EXTRA_ARGS += $(COMPILE_ARGS)
 EXTRA_ARGS += $(SIM_ARGS)
 EXTRA_ARGS += -licqueue
@@ -73,7 +77,7 @@ else
 endif
 
 # Xcelium errors out if multiple timescales are specified on the command line.
-ifneq (,$(findstring timescale,$(EXTRA_ARGS)))
+ifneq (,$(filter -timescale%,$(EXTRA_ARGS)))
     $(error Please use COCOTB_HDL_TIMEUNIT and COCOTB_HDL_TIMEPRECISION to specify timescale.)
 endif