classiq 0.38.0__py3-none-any.whl → 0.65.4__py3-none-any.whl

classiq/interface/generator/functions/core_lib_declarations/quantum_operators.py

@@ -1,95 +0,0 @@
-from typing import Any
-
-from classiq.interface.generator.functions.classical_type import Bool, Integer
-from classiq.interface.generator.functions.port_declaration import (
-    PortDeclarationDirection,
-)
-from classiq.interface.helpers.pydantic_model_helpers import nameables_to_dict
-from classiq.interface.model.port_declaration import PortDeclaration
-from classiq.interface.model.quantum_function_declaration import (
-    QuantumFunctionDeclaration,
-    QuantumOperandDeclaration,
-)
-
-REPEAT_OPERATOR = QuantumFunctionDeclaration(
-    name="repeat",
-    param_decls={"count": Integer()},
-    operand_declarations={
-        "iteration": QuantumOperandDeclaration(
-            name="iteration", param_decls={"index": Integer()}
-        )
-    },
-)
-
-
-def _get_single_empty_operand_operator(
-    operator_name: str, **kwargs: Any
-) -> QuantumFunctionDeclaration:
-    operand_field_name = "operand"
-    return QuantumFunctionDeclaration(
-        name=operator_name,
-        operand_declarations={
-            operand_field_name: QuantumOperandDeclaration(name=operand_field_name)
-        },
-        **kwargs,
-    )
-
-
-INVERT_OPERATOR = _get_single_empty_operand_operator(operator_name="invert")
-
-_CTRL_FIELD_NAME = "ctrl"
-CONTROL_OPERATOR = _get_single_empty_operand_operator(
-    operator_name="control",
-    port_declarations={
-        _CTRL_FIELD_NAME: PortDeclaration(
-            name=_CTRL_FIELD_NAME,
-            direction=PortDeclarationDirection.Inout,
-        )
-    },
-)
-
-IF_OPERATOR = QuantumFunctionDeclaration(
-    name="if",
-    param_decls={"condition": Bool()},
-    operand_declarations={
-        "then": QuantumOperandDeclaration(name="then"),
-        "else": QuantumOperandDeclaration(name="else"),
-    },
-)
-
-
-PERMUTE_OPERATOR = QuantumFunctionDeclaration(
-    name="permute",
-    operand_declarations={
-        "functions": QuantumOperandDeclaration(
-            name="functions",
-            is_list=True,
-        )
-    },
-)
-
-POWER_OPERATOR = _get_single_empty_operand_operator(
-    operator_name="power", param_decls={"power": Integer()}
-)
-
-APPLY_OPERATOR = _get_single_empty_operand_operator(operator_name="apply")
-
-COMPUTE = _get_single_empty_operand_operator(operator_name="compute")
-
-UNCOMPUTE = _get_single_empty_operand_operator(operator_name="uncompute")
-
-BUILTIN_QUANTUM_OPERATOR_LIST = [
-    REPEAT_OPERATOR,
-    INVERT_OPERATOR,
-    CONTROL_OPERATOR,
-    IF_OPERATOR,
-    PERMUTE_OPERATOR,
-    POWER_OPERATOR,
-    APPLY_OPERATOR,
-    COMPUTE,
-    UNCOMPUTE,
-]
-
-QuantumFunctionDeclaration.BUILTIN_FUNCTION_DECLARATIONS.update(
-    nameables_to_dict(BUILTIN_QUANTUM_OPERATOR_LIST)
-)

classiq/interface/generator/functions/foreign_function_definition.py

@@ -1,114 +0,0 @@
-from __future__ import annotations
-
-from typing import Any, Dict, List, NoReturn, Optional, Tuple, Union
-
-import pydantic
-
-from classiq.interface.generator.arith.register_user_input import RegisterUserInput
-from classiq.interface.generator.function_params import ArithmeticIODict, IOName
-from classiq.interface.generator.functions.function_implementation import (
-    FunctionImplementation,
-)
-from classiq.interface.generator.functions.port_declaration import (
-    SynthesisPortDeclaration,
-)
-from classiq.interface.generator.functions.quantum_function_declaration import (
-    SynthesisQuantumFunctionDeclaration,
-)
-from classiq.interface.generator.functions.register import Register
-from classiq.interface.generator.functions.register_mapping_data import (
-    RegisterMappingData,
-)
-
-from classiq.exceptions import ClassiqValueError
-
-ImplementationsType = Tuple[FunctionImplementation, ...]
-
-
-class SynthesisForeignFunctionDefinition(SynthesisQuantumFunctionDeclaration):
-    """
-    Facilitates the creation of a user-defined elementary function
-
-    This class sets extra to forbid so that it can be used in a Union and not "steal"
-    objects from other classes.
-    """
-
-    register_mapping: RegisterMappingData = pydantic.Field(
-        default_factory=RegisterMappingData,
-        description="The PortDirection data that is common to all implementations of the function",
-    )
-    implementations: Optional[ImplementationsType] = pydantic.Field(
-        description="The implementations of the custom function",
-    )
-
-    @pydantic.validator("register_mapping")
-    def _validate_register_mapping(
-        cls, register_mapping: RegisterMappingData
-    ) -> RegisterMappingData:
-        if not register_mapping.output_registers:
-            raise ClassiqValueError(
-                "The outputs of a custom function must be non-empty"
-            )
-        return register_mapping
-
-    @pydantic.validator("implementations", pre=True)
-    def _parse_implementations(
-        cls,
-        implementations: Optional[Union[ImplementationsType, FunctionImplementation]],
-    ) -> Optional[ImplementationsType]:
-        if isinstance(implementations, FunctionImplementation):
-            return (implementations,)
-
-        return implementations
-
-    @pydantic.validator("implementations")
-    def _validate_implementations(
-        cls,
-        implementations: Optional[ImplementationsType],
-        values: Dict[str, Any],
-    ) -> Optional[ImplementationsType]:
-        if not implementations:
-            raise ClassiqValueError(
-                "The implementations of a custom function must be non-empty."
-            )
-
-        register_mapping = values.get("register_mapping")
-        assert isinstance(register_mapping, RegisterMappingData)
-        for impl in implementations:
-            impl.validate_ranges_of_all_registers(register_mapping=register_mapping)
-
-        return implementations
-
-    @property
-    def inputs(self) -> ArithmeticIODict:
-        return _map_reg_user_input(self.register_mapping.input_registers)
-
-    @property
-    def outputs(self) -> ArithmeticIODict:
-        return _map_reg_user_input(self.register_mapping.output_registers)
-
-    def renamed(self, new_name: str) -> SynthesisForeignFunctionDefinition:
-        return SynthesisForeignFunctionDefinition(
-            name=new_name,
-            implementations=self.implementations,
-            register_mapping=self.register_mapping,
-        )
-
-    @property
-    def port_declarations(self) -> Dict[IOName, SynthesisPortDeclaration]:
-        raise ClassiqValueError(
-            "Bad usage of foreign function definition: port_declarations"
-        )
-
-    @port_declarations.setter
-    def port_declarations(self, value: Any) -> NoReturn:
-        raise ClassiqValueError(
-            "Bad usage of foreign function definition: port_declarations"
-        )
-
-
-def _map_reg_user_input(registers: List[Register]) -> ArithmeticIODict:
-    return {
-        reg.name: RegisterUserInput(size=len(reg.qubits), name=reg.name)
-        for reg in registers
-    }

classiq/interface/generator/functions/function_implementation.py

@@ -1,107 +0,0 @@
-from itertools import chain
-from typing import Optional, Tuple, Union
-
-import pydantic
-from pydantic import BaseModel
-
-from classiq.interface.generator.functions.register import Register
-from classiq.interface.generator.functions.register_mapping_data import (
-    RegisterMappingData,
-)
-from classiq.interface.helpers.custom_pydantic_types import PydanticNonEmptyString
-
-from classiq.exceptions import ClassiqValueError
-
-RegistersStrictType = Tuple[Register, ...]
-RegistersType = Union[Register, RegistersStrictType]
-
-
-def to_tuple(reg_type: RegistersType) -> RegistersStrictType:
-    if isinstance(reg_type, Register):
-        return (reg_type,)
-    else:
-        return reg_type
-
-
-class FunctionImplementation(BaseModel):
-    """
-    Facilitates the creation of a user-defined custom function implementation
-    """
-
-    class Config:
-        validate_all = True
-        extra = "forbid"
-
-    name: Optional[PydanticNonEmptyString] = pydantic.Field(
-        default=None,
-        description="The name of the custom implementation",
-    )
-
-    serialized_circuit: PydanticNonEmptyString = pydantic.Field(
-        description="The QASM code of the custom function implementation",
-    )
-
-    auxiliary_registers: RegistersStrictType = pydantic.Field(
-        default_factory=tuple,
-        description="A tuple of auxiliary registers to the custom implementation",
-    )
-
-    def num_qubits_in_all_registers(self, register_mapping: RegisterMappingData) -> int:
-        all_input_registers = (
-            register_mapping.input_registers
-            + register_mapping.zero_input_registers
-            + list(self.auxiliary_registers)
-        )
-        input_qubits = set(
-            chain.from_iterable(register.qubits for register in all_input_registers)
-        )
-        return len(input_qubits)
-
-    @pydantic.validator(
-        "auxiliary_registers",
-        pre=True,
-        always=True,
-    )
-    def validate_all_registers_are_tuples(
-        cls,
-        registers: RegistersType,
-    ) -> RegistersStrictType:
-        if isinstance(registers, Register):
-            return (registers,)
-        return registers
-
-    def validate_ranges_of_all_registers(
-        self, register_mapping: RegisterMappingData
-    ) -> None:
-        input_registers = register_mapping.input_registers
-        output_registers = register_mapping.output_registers
-        zero_input_registers = register_mapping.zero_input_registers
-        auxiliary_registers = list(self.auxiliary_registers)
-
-        all_input_registers = (
-            input_registers + zero_input_registers + auxiliary_registers
-        )
-        input_qubits = set(
-            chain.from_iterable(register.qubits for register in all_input_registers)
-        )
-        num_qubits = len(input_qubits)
-        all_qubits = set(range(num_qubits))
-        if num_qubits != sum(register.width for register in all_input_registers):
-            raise ClassiqValueError("The input registers must not overlap.")
-        if input_qubits != all_qubits:
-            raise ClassiqValueError(
-                "The set of qubits contained in all registers must be consecutive."
-            )
-
-        all_output_registers = output_registers + auxiliary_registers
-        output_qubits = set(
-            chain.from_iterable(register.qubits for register in all_output_registers)
-        )
-        if len(output_qubits) != sum(
-            register.width for register in all_output_registers
-        ):
-            raise ClassiqValueError("The output registers must not overlap.")
-        if not output_qubits == all_qubits:
-            raise ClassiqValueError(
-                "The input and output qubits must be mutually consistent."
-            )

classiq/interface/generator/functions/native_function_definition.py

@@ -1,155 +0,0 @@
-from typing import Any, Dict, List, Optional
-
-import pydantic
-
-from classiq.interface.generator.arith.register_user_input import RegisterUserInput
-from classiq.interface.generator.function_params import IOName, PortDirection
-from classiq.interface.generator.functions.port_declaration import (
-    SynthesisPortDeclaration,
-)
-from classiq.interface.generator.functions.quantum_function_declaration import (
-    SynthesisQuantumFunctionDeclaration,
-)
-from classiq.interface.generator.quantum_function_call import (
-    SynthesisQuantumFunctionCall,
-    WireDict,
-    WireName,
-)
-from classiq.interface.generator.validations import flow_graph
-
-from classiq.exceptions import ClassiqValueError
-
-LOGIC_FLOW_DUPLICATE_NAME_ERROR_MSG = (
-    "Cannot have multiple function calls with the same name"
-)
-
-
-class IOData(pydantic.BaseModel):
-    wire: WireName = pydantic.Field(
-        description="The name of the wire of the PortDirection data."
-    )
-    reg: RegisterUserInput = pydantic.Field(
-        description="The register information about the PortDirection data."
-    )
-
-    class Config:
-        frozen = True
-
-
-class SynthesisNativeFunctionDefinition(SynthesisQuantumFunctionDeclaration):
-    """
-    Facilitates the creation of a user-defined composite function
-
-    This class sets extra to forbid so that it can be used in a Union and not "steal"
-    objects from other classes.
-    """
-
-    input_ports_wiring: Dict[IOName, WireName] = pydantic.Field(
-        description="The mapping between the functions input ports, to inner wires",
-        default_factory=dict,
-    )
-
-    output_ports_wiring: Dict[IOName, WireName] = pydantic.Field(
-        description="The mapping between the functions output ports, to inner wires",
-        default_factory=dict,
-    )
-
-    body: List[SynthesisQuantumFunctionCall] = pydantic.Field(
-        default_factory=list, description="List of function calls to perform."
-    )
-
-    def validate_body(self) -> None:
-        function_call_names = {call.name for call in self.body}
-        if len(function_call_names) != len(self.body):
-            raise ClassiqValueError(LOGIC_FLOW_DUPLICATE_NAME_ERROR_MSG)
-        flow_graph.validate_legal_wiring(
-            self.body,
-            flow_input_names=list(self.input_ports_wiring.values()),
-            flow_output_names=list(self.output_ports_wiring.values()),
-        )
-        flow_graph.validate_acyclic_logic_flow(
-            self.body,
-            flow_input_names=list(self.input_ports_wiring.values()),
-            flow_output_names=list(self.output_ports_wiring.values()),
-        )
-
-    @classmethod
-    def _validate_direction_ports(
-        cls,
-        port_declarations: Dict[IOName, SynthesisPortDeclaration],
-        directions_external_port_wiring: WireDict,
-        direction: PortDirection,
-    ) -> None:
-        for io_name in directions_external_port_wiring:
-            if (
-                io_name not in port_declarations
-                or not port_declarations[io_name].direction == direction
-            ):
-                raise ClassiqValueError(
-                    f"The wired {direction} port {io_name!r} is not declared."
-                )
-
-    @pydantic.root_validator
-    def validate_ports(cls, values: Dict[str, Any]) -> Dict[str, Any]:
-        port_declarations: Optional[Dict[IOName, SynthesisPortDeclaration]] = (
-            values.get("port_declarations")
-        )
-        if port_declarations is None:
-            return values
-        cls._validate_direction_ports(
-            port_declarations,
-            values.get("input_ports_wiring", dict()),
-            PortDirection.Input,
-        )
-        cls._validate_direction_ports(
-            port_declarations,
-            values.get("output_ports_wiring", dict()),
-            PortDirection.Output,
-        )
-        return values
-
-    @pydantic.validator("input_ports_wiring", always=True)
-    def _populate_input_ports_wiring(
-        cls, input_ports_wiring: Dict[IOName, WireName], values: Dict[str, Any]
-    ) -> Dict[IOName, WireName]:
-        return _validate_ports_wiring_for_direction(
-            input_ports_wiring, values, PortDirection.Input
-        )
-
-    @pydantic.validator("output_ports_wiring", always=True)
-    def _populate_output_ports_wiring(
-        cls, output_ports_wiring: Dict[IOName, WireName], values: Dict[str, Any]
-    ) -> Dict[IOName, WireName]:
-        return _validate_ports_wiring_for_direction(
-            output_ports_wiring, values, PortDirection.Output
-        )
-
-
-def _get_single_port_wiring(
-    ports_wiring: Dict[IOName, WireName], name: str, direction: PortDirection
-) -> WireName:
-    direction_id = "out" if direction == PortDirection.Output else "in"
-    return ports_wiring.get(name) or f"{name}_{direction_id}"
-
-
-def _port_declarations_to_wiring(
-    ports_wiring: Dict[IOName, WireName],
-    port_decls: Dict[IOName, SynthesisPortDeclaration],
-    direction: PortDirection,
-) -> Dict[IOName, WireName]:
-    return {
-        name: _get_single_port_wiring(ports_wiring, name, direction)
-        for name, port in port_decls.items()
-        if port.direction.includes_port_direction(direction)
-    }
-
-
-def _validate_ports_wiring_for_direction(
-    ports_wiring: Dict[IOName, WireName],
-    values: Dict[str, Any],
-    direction: PortDirection,
-) -> Dict[IOName, WireName]:
-    port_decls = values.get("port_declarations")
-    if port_decls is None:
-        return ports_wiring
-    return _port_declarations_to_wiring(ports_wiring, port_decls, direction)

classiq/interface/generator/functions/quantum_function_declaration.py

@@ -1,69 +0,0 @@
-from typing import Dict, Set
-
-import pydantic
-from pydantic import BaseModel
-
-from classiq.interface.generator.arith.register_user_input import RegisterUserInput
-from classiq.interface.generator.function_params import (
-    ArithmeticIODict,
-    IOName,
-    PortDirection,
-)
-from classiq.interface.generator.functions.port_declaration import (
-    SynthesisPortDeclaration,
-)
-from classiq.interface.helpers.validation_helpers import validate_nameables_mapping
-
-
-class SynthesisQuantumFunctionDeclaration(BaseModel):
-    """
-    Facilitates the creation of a common quantum function interface object.
-    """
-
-    name: str = pydantic.Field(description="The name of the function")
-
-    port_declarations: Dict[IOName, SynthesisPortDeclaration] = pydantic.Field(
-        description="The input and output ports of the function.",
-        default_factory=dict,
-    )
-
-    @property
-    def input_set(self) -> Set[IOName]:
-        return set(self.inputs.keys())
-
-    @property
-    def output_set(self) -> Set[IOName]:
-        return set(self.outputs.keys())
-
-    @property
-    def inputs(self) -> ArithmeticIODict:
-        return _ports_to_registers(self.port_declarations, PortDirection.Input)
-
-    @property
-    def outputs(self) -> ArithmeticIODict:
-        return _ports_to_registers(self.port_declarations, PortDirection.Output)
-
-    @pydantic.validator("port_declarations")
-    def _validate_port_declarations_names(
-        cls, port_declarations: Dict[IOName, SynthesisPortDeclaration]
-    ) -> Dict[IOName, SynthesisPortDeclaration]:
-        validate_nameables_mapping(port_declarations, "Port")
-        return port_declarations
-
-    class Config:
-        extra = pydantic.Extra.forbid
-
-
-def _ports_to_registers(
-    port_declarations: Dict[IOName, SynthesisPortDeclaration], direction: PortDirection
-) -> ArithmeticIODict:
-    return {
-        name: RegisterUserInput(
-            name=name,
-            size=port_decl.size,
-            is_signed=port_decl.is_signed,
-            fraction_places=port_decl.fraction_places,
-        )
-        for name, port_decl in port_declarations.items()
-        if port_decl.direction.includes_port_direction(direction)
-    }

classiq/interface/generator/functions/register.py

@@ -1,44 +0,0 @@
-from __future__ import annotations
-
-from operator import attrgetter
-from typing import Iterable, Tuple
-
-import pydantic
-from pydantic import BaseModel
-
-from classiq.interface.helpers.custom_pydantic_types import PydanticNonEmptyString
-
-from classiq.exceptions import ClassiqValueError
-
-QubitsType = Tuple[pydantic.NonNegativeInt, ...]
-
-
-class Register(BaseModel):
-    """
-    A user-defined custom register.
-    """
-
-    name: PydanticNonEmptyString = pydantic.Field(
-        description="The name of the custom register",
-    )
-
-    qubits: QubitsType = pydantic.Field(
-        description="A tuple of qubits as integers as indexed within a custom function code",
-    )
-
-    @property
-    def width(self) -> pydantic.PositiveInt:
-        """The number of qubits of the custom register"""
-        return len(self.qubits)
-
-    @pydantic.validator("qubits")
-    def validate_qubits(cls, qubits: QubitsType) -> QubitsType:
-        if len(qubits) == 0:
-            raise ClassiqValueError("qubits field must be non-empty.")
-        if len(set(qubits)) != len(qubits):
-            raise ClassiqValueError("All qubits of a register must be distinct.")
-        return qubits
-
-
-def get_register_names(reg_list: Iterable[Register]) -> Iterable[str]:
-    return map(attrgetter("name"), reg_list)

classiq/interface/generator/functions/register_mapping_data.py

@@ -1,106 +0,0 @@
-from __future__ import annotations
-
-import itertools
-from typing import Any, Dict, Iterable, List, Tuple
-
-import pydantic
-
-from classiq.interface.generator.functions.register import Register, get_register_names
-from classiq.interface.generator.register_role import RegisterRole as Role
-from classiq.interface.helpers.custom_pydantic_types import PydanticNonEmptyString
-
-from classiq.exceptions import ClassiqValueError
-
-REGISTER_NOT_FOUND_ERROR = "Register name not found"
-
-
-class RegisterMappingData(pydantic.BaseModel):
-    input_registers: List[Register] = pydantic.Field(default_factory=list)
-    output_registers: List[Register] = pydantic.Field(default_factory=list)
-    zero_input_registers: List[Register] = pydantic.Field(default_factory=list)
-
-    @pydantic.root_validator()
-    def validate_mapping(cls, values: Dict[str, Any]) -> Dict[str, Any]:
-        input_registers = values.get("input_registers", list())
-        output_registers = values.get("output_registers", list())
-        zero_input_registers = values.get("zero_input_registers", list())
-
-        input_qubits = cls._get_qubit_range(input_registers)
-        output_qubits = cls._get_qubit_range(output_registers)
-        zero_input_qubits = cls._get_qubit_range(zero_input_registers)
-
-        all_input_qubits = sorted(input_qubits + zero_input_qubits)
-        if not cls._validate_no_overlap(all_input_qubits):
-            raise ClassiqValueError("overlapping input qubits are not allowed")
-        if not cls._validate_no_overlap(output_qubits):
-            raise ClassiqValueError("overlapping output qubits are not allowed")
-
-        if not output_qubits == all_input_qubits:
-            raise ClassiqValueError(
-                "output registers should be included within the input / zero input registers"
-            )
-
-        return values
-
-    @pydantic.validator("input_registers", "output_registers")
-    def validate_input_registers_are_distinct(
-        cls, field_value: List[Register]
-    ) -> List[Register]:
-        if len(field_value) != len({io_register.name for io_register in field_value}):
-            raise ClassiqValueError(
-                "The names of PortDirection registers must be distinct."
-            )
-        return field_value
-
-    @staticmethod
-    def _validate_no_overlap(reg_list: List[int]) -> bool:
-        return len(reg_list) == len(set(reg_list))
-
-    @staticmethod
-    def _get_qubit_range(registers: Iterable[Register]) -> List[int]:
-        return sorted(itertools.chain.from_iterable(reg.qubits for reg in registers))
-
-    @property
-    def input_names(self) -> Iterable[str]:
-        return get_register_names(self.input_registers)
-
-    @property
-    def output_names(self) -> Iterable[str]:
-        return get_register_names(self.output_registers)
-
-    def validate_equal_mappings(self, other: RegisterMappingData) -> None:
-        if any(
-            [
-                self.input_registers != other.input_registers,
-                self.output_registers != other.output_registers,
-                self.zero_input_registers != other.zero_input_registers,
-            ]
-        ):
-            raise ClassiqValueError(
-                "Interface should be identical in all implementations"
-            )
-
-    def get_input_register(self, name: PydanticNonEmptyString) -> Register:
-        for reg in self.input_registers:
-            if reg.name == name:
-                return reg
-        raise ClassiqValueError(REGISTER_NOT_FOUND_ERROR)
-
-    def get_output_register(self, name: PydanticNonEmptyString) -> Register:
-        for reg in self.output_registers:
-            if reg.name == name:
-                return reg
-        raise ClassiqValueError(REGISTER_NOT_FOUND_ERROR)
-
-    @staticmethod
-    def from_registers_dict(
-        regs_dict: Dict[Role, Tuple[Register, ...]]
-    ) -> RegisterMappingData:
-        return RegisterMappingData(
-            input_registers=list(regs_dict[Role.INPUT]),
-            output_registers=list(regs_dict[Role.OUTPUT]),
-            zero_input_registers=list(regs_dict[Role.ZERO_INPUT]),
-        )
-
-    class Config:
-        extra = "forbid"