cirq-core 1.5.0.dev20250116193042__py3-none-any.whl → 1.5.0.dev20250117150435__py3-none-any.whl

cirq/_version.py

@@ -28,4 +28,4 @@ if sys.version_info < (3, 10, 0):  # pragma: no cover
         'of cirq (e.g. "python -m pip install cirq==1.1.*")'
     )
 
-__version__ = "1.5.0.dev20250116193042"
+__version__ = "1.5.0.dev20250117150435"

cirq/_version_test.py

@@ -3,4 +3,4 @@ import cirq
 
 
 def test_version():
-    assert cirq.__version__ == "1.5.0.dev20250116193042"
+    assert cirq.__version__ == "1.5.0.dev20250117150435"

cirq/circuits/qasm_output.py

@@ -366,10 +366,10 @@ class QasmOutput:
             if should_annotate:
                 output_line_gap(1)
                 if isinstance(main_op, ops.GateOperation):
-                    x = str(main_op.gate).replace('\n', '\n //')
+                    x = str(main_op.gate).replace('\n', '\n//       ')
                     output(f'// Gate: {x!s}\n')
                 else:
-                    x = str(main_op).replace('\n', '\n //')
+                    x = str(main_op).replace('\n', '\n//            ')
                     output(f'// Operation: {x!s}\n')
 
             for qasm in qasms:

cirq/contrib/qasm_import/_lexer.py

@@ -33,6 +33,7 @@ class QasmLexer:
         'creg': 'CREG',
         'measure': 'MEASURE',
         'reset': 'RESET',
+        'gate': 'GATE',
         'if': 'IF',
         '->': 'ARROW',
         '==': 'EQ',
@@ -120,6 +121,10 @@ class QasmLexer:
         r"""reset"""
         return t
 
+    def t_GATE(self, t):
+        r"""gate"""
+        return t
+
     def t_IF(self, t):
         r"""if"""
         return t

cirq/contrib/qasm_import/_lexer_test.py

@@ -159,6 +159,74 @@ def test_creg():
     assert token.value == ";"
 
 
+def test_custom_gate():
+    lexer = QasmLexer()
+    lexer.input('gate name(param1,param2) q1, q2 {X(q1)}')
+    token = lexer.token()
+    assert token.type == "GATE"
+    assert token.value == "gate"
+
+    token = lexer.token()
+    assert token.type == "ID"
+    assert token.value == "name"
+
+    token = lexer.token()
+    assert token.type == "("
+    assert token.value == "("
+
+    token = lexer.token()
+    assert token.type == "ID"
+    assert token.value == "param1"
+
+    token = lexer.token()
+    assert token.type == ","
+    assert token.value == ","
+
+    token = lexer.token()
+    assert token.type == "ID"
+    assert token.value == "param2"
+
+    token = lexer.token()
+    assert token.type == ")"
+    assert token.value == ")"
+
+    token = lexer.token()
+    assert token.type == "ID"
+    assert token.value == "q1"
+
+    token = lexer.token()
+    assert token.type == ","
+    assert token.value == ","
+
+    token = lexer.token()
+    assert token.type == "ID"
+    assert token.value == "q2"
+
+    token = lexer.token()
+    assert token.type == "{"
+    assert token.value == "{"
+
+    token = lexer.token()
+    assert token.type == "ID"
+    assert token.value == "X"
+
+    token = lexer.token()
+    assert token.type == "("
+    assert token.value == "("
+
+    token = lexer.token()
+    assert token.type == "ID"
+    assert token.value == "q1"
+
+    token = lexer.token()
+    assert token.type == ")"
+    assert token.value == ")"
+
+    token = lexer.token()
+    assert token.type == "}"
+    assert token.value == "}"
+
+
 def test_error():
     lexer = QasmLexer()
     lexer.input('θ')

cirq/contrib/qasm_import/_parser.py

@@ -12,15 +12,28 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+import dataclasses
 import functools
 import operator
-from typing import Any, Callable, cast, Dict, Iterable, List, Optional, Union, TYPE_CHECKING
+from typing import (
+    Any,
+    Callable,
+    cast,
+    Dict,
+    Iterable,
+    List,
+    Optional,
+    Set,
+    Tuple,
+    Union,
+    TYPE_CHECKING,
+)
 
 import numpy as np
 import sympy
 from ply import yacc
 
-from cirq import ops, Circuit, NamedQubit, CX
+from cirq import ops, value, Circuit, CircuitOperation, CX, FrozenCircuit, NamedQubit
 from cirq.circuits.qasm_output import QasmUGate
 from cirq.contrib.qasm_import._lexer import QasmLexer
 from cirq.contrib.qasm_import.exception import QasmException
@@ -47,6 +60,31 @@ class Qasm:
         self.circuit = c
 
 
+def _generate_op_qubits(args: List[List[ops.Qid]], lineno: int) -> List[List[ops.Qid]]:
+    """Generates the Cirq qubits for an operation from the OpenQASM qregs.
+
+    OpenQASM gates can be applied on single qubits and qubit registers.
+    We represent single qubits as registers of size 1.
+    Based on the OpenQASM spec (https://arxiv.org/abs/1707.03429),
+    single qubit arguments can be mixed with qubit registers.
+    Given quantum registers of length reg_size and single qubits are both
+    used as arguments, we generate reg_size GateOperations via iterating
+    through each qubit of the registers 0 to n-1 and use the same one
+    qubit from the "single-qubit registers" for each operation."""
+    reg_sizes = np.unique([len(reg) for reg in args])
+    if len(reg_sizes) > 2 or (len(reg_sizes) > 1 and reg_sizes[0] != 1):
+        raise QasmException(
+            f"Non matching quantum registers of length {reg_sizes} at line {lineno}"
+        )
+    op_qubits_gen = functools.reduce(
+        cast(Callable[[List['cirq.Qid'], List['cirq.Qid']], List['cirq.Qid']], np.broadcast), args
+    )
+    op_qubits = [[q] if isinstance(q, ops.Qid) else q for q in op_qubits_gen]
+    if any(len(set(q)) < len(q) for q in op_qubits):
+        raise QasmException(f"Overlapping qubits in arguments at line {lineno}")
+    return op_qubits
+
+
 class QasmGateStatement:
     """Specifies how to convert a call to an OpenQASM gate
     to a list of `cirq.GateOperation`s.
@@ -87,7 +125,7 @@ class QasmGateStatement:
                 f"got: {len(args)}, at line {lineno}"
             )
 
-    def _validate_params(self, params: List[float], lineno: int):
+    def _validate_params(self, params: List[value.TParamVal], lineno: int):
         if len(params) != self.num_params:
             raise QasmException(
                 f"{self.qasm_gate} takes {self.num_params} parameter(s), "
@@ -95,41 +133,47 @@ class QasmGateStatement:
             )
 
     def on(
-        self, params: List[float], args: List[List[ops.Qid]], lineno: int
+        self, params: List[value.TParamVal], args: List[List[ops.Qid]], lineno: int
     ) -> Iterable[ops.Operation]:
         self._validate_args(args, lineno)
         self._validate_params(params, lineno)
 
-        reg_sizes = np.unique([len(reg) for reg in args])
-        if len(reg_sizes) > 2 or (len(reg_sizes) > 1 and reg_sizes[0] != 1):
-            raise QasmException(
-                f"Non matching quantum registers of length {reg_sizes} at line {lineno}"
-            )
-
         # the actual gate we'll apply the arguments to might be a parameterized
         # or non-parameterized gate
         final_gate: ops.Gate = (
             self.cirq_gate if isinstance(self.cirq_gate, ops.Gate) else self.cirq_gate(params)
         )
-        # OpenQASM gates can be applied on single qubits and qubit registers.
-        # We represent single qubits as registers of size 1.
-        # Based on the OpenQASM spec (https://arxiv.org/abs/1707.03429),
-        # single qubit arguments can be mixed with qubit registers.
-        # Given quantum registers of length reg_size and single qubits are both
-        # used as arguments, we generate reg_size GateOperations via iterating
-        # through each qubit of the registers 0 to n-1 and use the same one
-        # qubit from the "single-qubit registers" for each operation.
-        op_qubits = functools.reduce(
-            cast(Callable[[List['cirq.Qid'], List['cirq.Qid']], List['cirq.Qid']], np.broadcast),
-            args,
-        )
-        for qubits in op_qubits:
-            if isinstance(qubits, ops.Qid):
-                yield final_gate.on(qubits)
-            elif len(np.unique(qubits)) < len(qubits):
-                raise QasmException(f"Overlapping qubits in arguments at line {lineno}")
-            else:
-                yield final_gate.on(*qubits)
+        for qubits in _generate_op_qubits(args, lineno):
+            yield final_gate.on(*qubits)
+
+
+@dataclasses.dataclass
+class CustomGate:
+    """Represents an invocation of a user-defined gate.
+
+    The custom gate definition is encoded here as a `FrozenCircuit`, and the
+    arguments (params and qubits) of the specific invocation of that gate are
+    stored here too. When `on` is called, we create a CircuitOperation, mapping
+    the qubits and params to the values provided."""
+
+    name: str
+    circuit: FrozenCircuit
+    params: Tuple[str, ...]
+    qubits: Tuple[ops.Qid, ...]
+
+    def on(
+        self, params: List[value.TParamVal], args: List[List[ops.Qid]], lineno: int
+    ) -> Iterable[ops.Operation]:
+        if len(params) != len(self.params):
+            raise QasmException(f"Wrong number of params for '{self.name}' at line {lineno}")
+        if len(args) != len(self.qubits):
+            raise QasmException(f"Wrong number of qregs for '{self.name}' at line {lineno}")
+        for qubits in _generate_op_qubits(args, lineno):
+            yield CircuitOperation(
+                self.circuit,
+                param_resolver={k: v for k, v in zip(self.params, params)},
+                qubit_map={k: v for k, v in zip(self.qubits, qubits)},
+            )
 
 
 class QasmParser:
@@ -146,6 +190,18 @@ class QasmParser:
         self.circuit = Circuit()
         self.qregs: Dict[str, int] = {}
         self.cregs: Dict[str, int] = {}
+        self.gate_set: Dict[str, Union[CustomGate, QasmGateStatement]] = {**self.basic_gates}
+        """The gates available to use in the circuit, including those from libraries, and
+         user-defined ones."""
+        self.in_custom_gate_scope = False
+        """This is set to True when the parser is in the middle of parsing a custom gate
+         definition."""
+        self.custom_gate_scoped_params: Set[str] = set()
+        """The params declared within the current custom gate definition. Empty if not in
+         custom gate scope."""
+        self.custom_gate_scoped_qubits: Dict[str, ops.Qid] = {}
+        """The qubits declared within the current custom gate definition. Empty if not in
+         custom gate scope."""
         self.qelibinc = False
         self.lexer = QasmLexer()
         self.supported_format = False
@@ -270,8 +326,6 @@ class QasmParser:
         'tdg': QasmGateStatement(qasm_gate='tdg', num_params=0, num_args=1, cirq_gate=ops.T**-1),
     }
 
-    all_gates = {**basic_gates, **qelib_gates}
-
     tokens = QasmLexer.tokens
     start = 'start'
 
@@ -296,11 +350,13 @@ class QasmParser:
     def p_qasm_include(self, p):
         """qasm : qasm QELIBINC"""
         self.qelibinc = True
+        self.gate_set |= self.qelib_gates
         p[0] = Qasm(self.supported_format, self.qelibinc, self.qregs, self.cregs, self.circuit)
 
     def p_qasm_include_stdgates(self, p):
         """qasm : qasm STDGATESINC"""
         self.qelibinc = True
+        self.gate_set |= self.qelib_gates
         p[0] = Qasm(self.supported_format, self.qelibinc, self.qregs, self.cregs, self.circuit)
 
     def p_qasm_circuit(self, p):
@@ -338,6 +394,10 @@ class QasmParser:
         """circuit : empty"""
         p[0] = self.circuit
 
+    def p_circuit_gate_def(self, p):
+        """circuit : gate_def"""
+        p[0] = self.circuit
+
     # qreg and creg
 
     def p_new_reg(self, p):
@@ -382,14 +442,13 @@ class QasmParser:
         self._resolve_gate_operation(args=p[5], gate=p[1], p=p, params=p[3])
 
     def _resolve_gate_operation(
-        self, args: List[List[ops.Qid]], gate: str, p: Any, params: List[float]
+        self, args: List[List[ops.Qid]], gate: str, p: Any, params: List[value.TParamVal]
     ):
-        gate_set = self.basic_gates if not self.qelibinc else self.all_gates
-        if gate not in gate_set.keys():
+        if gate not in self.gate_set:
             tip = ", did you forget to include qelib1.inc?" if not self.qelibinc else ""
             msg = f'Unknown gate "{gate}" at line {p.lineno(1)}{tip}'
             raise QasmException(msg)
-        p[0] = gate_set[gate].on(args=args, params=params, lineno=p.lineno(1))
+        p[0] = self.gate_set[gate].on(args=args, params=params, lineno=p.lineno(1))
 
     # params : parameter ',' params
     #        | parameter
@@ -404,7 +463,8 @@ class QasmParser:
         p[0] = [p[1]]
 
     # expr : term
-    #            | func '(' expression ')' """
+    #            | ID
+    #            | func '(' expression ')'
     #            | binary_op
     #            | unary_op
 
@@ -412,6 +472,14 @@ class QasmParser:
         """expr : term"""
         p[0] = p[1]
 
+    def p_expr_identifier(self, p):
+        """expr : ID"""
+        if not self.in_custom_gate_scope:
+            raise QasmException(f"Parameter '{p[1]}' in line {p.lineno(1)} not supported")
+        if p[1] not in self.custom_gate_scoped_params:
+            raise QasmException(f"Undefined parameter '{p[1]}' in line {p.lineno(1)}'")
+        p[0] = sympy.Symbol(p[1])
+
     def p_expr_parens(self, p):
         """expr : '(' expr ')'"""
         p[0] = p[2]
@@ -464,6 +532,15 @@ class QasmParser:
     def p_quantum_arg_register(self, p):
         """qarg : ID"""
         reg = p[1]
+        if self.in_custom_gate_scope:
+            if reg not in self.custom_gate_scoped_qubits:
+                if reg not in self.qregs:
+                    msg = f"Undefined qubit '{reg}'"
+                else:
+                    msg = f"'{reg}' is a register, not a qubit"
+                raise QasmException(f"{msg} at line {p.lineno(1)}")
+            p[0] = [self.custom_gate_scoped_qubits[reg]]
+            return
         if reg not in self.qregs.keys():
             raise QasmException(f'Undefined quantum register "{reg}" at line {p.lineno(1)}')
         qubits = []
@@ -492,6 +569,8 @@ class QasmParser:
         """qarg : ID '[' NATURAL_NUMBER ']'"""
         reg = p[1]
         idx = p[3]
+        if self.in_custom_gate_scope:
+            raise QasmException(f"Unsupported indexed qreg '{reg}[{idx}]' at line {p.lineno(1)}")
         arg_name = self.make_name(idx, reg)
         if reg not in self.qregs.keys():
             raise QasmException(f'Undefined quantum register "{reg}" at line {p.lineno(1)}')
@@ -570,6 +649,60 @@ class QasmParser:
             ops.ClassicallyControlledOperation(conditions=conditions, sub_operation=tuple(p[7])[0])
         ]
 
+    def p_gate_params_multiple(self, p):
+        """gate_params : ID ',' gate_params"""
+        self.p_gate_params_single(p)
+        p[0] += p[3]
+
+    def p_gate_params_single(self, p):
+        """gate_params : ID"""
+        self.in_custom_gate_scope = True
+        self.custom_gate_scoped_params.add(p[1])
+        p[0] = [p[1]]
+
+    def p_gate_qubits_multiple(self, p):
+        """gate_qubits : ID ',' gate_qubits"""
+        self.p_gate_qubits_single(p)
+        p[0] += p[3]
+
+    def p_gate_qubits_single(self, p):
+        """gate_qubits : ID"""
+        self.in_custom_gate_scope = True
+        q = NamedQubit(p[1])
+        self.custom_gate_scoped_qubits[p[1]] = q
+        p[0] = [q]
+
+    def p_gate_ops(self, p):
+        """gate_ops : gate_op gate_ops"""
+        p[0] = [p[1]] + p[2]
+
+    def p_gate_ops_empty(self, p):
+        """gate_ops : empty"""
+        self.in_custom_gate_scope = True
+        p[0] = []
+
+    def p_gate_def_parameterized(self, p):
+        """gate_def : GATE ID '(' gate_params ')' gate_qubits '{' gate_ops '}'"""
+        self._gate_def(p, has_params=True)
+
+    def p_gate_def(self, p):
+        """gate_def : GATE ID gate_qubits '{' gate_ops '}'"""
+        self._gate_def(p, has_params=False)
+
+    def _gate_def(self, p: List[Any], *, has_params: bool):
+        name = p[2]
+        gate_params = tuple(p[4]) if has_params else ()
+        offset = 3 if has_params else 0
+        gate_qubits = tuple(p[3 + offset])
+        gate_ops = p[5 + offset]
+        circuit = Circuit(gate_ops).freeze()
+        gate_def = CustomGate(name, circuit, gate_params, gate_qubits)
+        self.gate_set[name] = gate_def
+        self.custom_gate_scoped_params.clear()
+        self.custom_gate_scoped_qubits.clear()
+        self.in_custom_gate_scope = False
+        p[0] = gate_def
+
     def p_error(self, p):
         if p is None:
             raise QasmException('Unexpected end of file')

cirq/contrib/qasm_import/_parser_test.py

@@ -12,16 +12,18 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+import re
 import textwrap
+import warnings
 from typing import Callable
 
 import numpy as np
 import pytest
 import sympy
 
-
 import cirq
 import cirq.testing as ct
+from cirq.testing import consistent_qasm as cq
 from cirq import Circuit
 from cirq.circuits.qasm_output import QasmUGate
 from cirq.contrib.qasm_import import QasmException
@@ -186,7 +188,7 @@ def test_CX_gate():
      qreg q2[2];
      CX q1[0], q1[1];
      CX q1, q2[0];
-     CX q2, q1;      
+     CX q2, q1;
 """
     parser = QasmParser()
 
@@ -390,7 +392,7 @@ def test_U_angles():
 
 def test_U_gate_zero_params_error():
     qasm = """OPENQASM 2.0;
-     qreg q[2];     
+     qreg q[2];
      U q[1];"""
 
     parser = QasmParser()
@@ -401,7 +403,7 @@ def test_U_gate_zero_params_error():
 
 def test_U_gate_too_much_params_error():
     qasm = """OPENQASM 2.0;
-     qreg q[2];     
+     qreg q[2];
      U(pi, pi, pi, pi) q[1];"""
 
     parser = QasmParser()
@@ -520,9 +522,9 @@ def test_rotation_gates(qasm_gate: str, cirq_gate: Callable[[float], cirq.Gate])
 def test_rotation_gates_wrong_number_of_args(qasm_gate: str):
     qasm = f"""
      OPENQASM 2.0;
-     include "qelib1.inc";             
-     qreg q[2];     
-     {qasm_gate}(pi) q[0], q[1];     
+     include "qelib1.inc";
+     qreg q[2];
+     {qasm_gate}(pi) q[0], q[1];
 """
 
     parser = QasmParser()
@@ -534,9 +536,9 @@ def test_rotation_gates_wrong_number_of_args(qasm_gate: str):
 @pytest.mark.parametrize('qasm_gate', [g[0] for g in rotation_gates])
 def test_rotation_gates_zero_params_error(qasm_gate: str):
     qasm = f"""OPENQASM 2.0;
-     include "qelib1.inc";             
-     qreg q[2];     
-     {qasm_gate} q[1];     
+     include "qelib1.inc";
+     qreg q[2];
+     {qasm_gate} q[1];
 """
 
     parser = QasmParser()
@@ -584,7 +586,7 @@ def test_measure_individual_bits():
          OPENQASM 2.0;
          include "qelib1.inc";
          qreg q1[2];
-         creg c1[2];                        
+         creg c1[2];
          measure q1[0] -> c1[0];
          measure q1[1] -> c1[1];
     """
@@ -612,8 +614,8 @@ def test_measure_registers():
     qasm = """OPENQASM 2.0;
          include "qelib1.inc";
          qreg q1[3];
-         creg c1[3];                        
-         measure q1 -> c1;       
+         creg c1[3];
+         measure q1 -> c1;
     """
     parser = QasmParser()
 
@@ -639,10 +641,10 @@ def test_measure_registers():
 
 def test_measure_mismatched_register_size():
     qasm = """OPENQASM 2.0;
-         include "qelib1.inc";       
+         include "qelib1.inc";
          qreg q1[2];
-         creg c1[3];                        
-         measure q1 -> c1;       
+         creg c1[3];
+         measure q1 -> c1;
     """
 
     parser = QasmParser()
@@ -653,11 +655,11 @@ def test_measure_mismatched_register_size():
 
 def test_measure_to_quantum_register():
     qasm = """OPENQASM 2.0;
-         include "qelib1.inc";       
+         include "qelib1.inc";
          qreg q1[3];
          qreg q2[3];
-         creg c1[3];                        
-         measure q2 -> q1;       
+         creg c1[3];
+         measure q2 -> q1;
     """
 
     parser = QasmParser()
@@ -668,10 +670,10 @@ def test_measure_to_quantum_register():
 
 def test_measure_undefined_classical_bit():
     qasm = """OPENQASM 2.0;
-         include "qelib1.inc";       
-         qreg q1[3];    
-         creg c1[3];                        
-         measure q1[1] -> c2[1];       
+         include "qelib1.inc";
+         qreg q1[3];
+         creg c1[3];
+         measure q1[1] -> c2[1];
     """
 
     parser = QasmParser()
@@ -682,11 +684,11 @@ def test_measure_undefined_classical_bit():
 
 def test_measure_from_classical_register():
     qasm = """OPENQASM 2.0;
-         include "qelib1.inc";       
+         include "qelib1.inc";
          qreg q1[2];
-         creg c1[3];                        
-         creg c2[3];                        
-         measure c1 -> c2;       
+         creg c1[3];
+         creg c2[3];
+         measure c1 -> c2;
     """
 
     parser = QasmParser()
@@ -698,8 +700,8 @@ def test_measure_from_classical_register():
 def test_measurement_bounds():
     qasm = """OPENQASM 2.0;
      qreg q1[3];
-     creg c1[3];                        
-     measure q1[0] -> c1[4];  
+     creg c1[3];
+     measure q1[0] -> c1[4];
 """
     parser = QasmParser()
 
@@ -741,7 +743,7 @@ def test_u1_gate():
      OPENQASM 2.0;
      include "qelib1.inc";
      qreg q[1];
-     u1(pi / 3.0) q[0];    
+     u1(pi / 3.0) q[0];
 """
     parser = QasmParser()
 
@@ -764,7 +766,7 @@ def test_u2_gate():
      OPENQASM 2.0;
      include "qelib1.inc";
      qreg q[1];
-     u2(2 * pi, pi / 3.0) q[0];    
+     u2(2 * pi, pi / 3.0) q[0];
 """
     parser = QasmParser()
 
@@ -787,7 +789,7 @@ def test_id_gate():
      OPENQASM 2.0;
      include "qelib1.inc";
      qreg q[2];
-     id q;           
+     id q;
 """
     parser = QasmParser()
 
@@ -846,7 +848,7 @@ def test_r_gate():
      OPENQASM 2.0;
      include "qelib1.inc";
      qreg q[1];
-     r(pi, pi / 2.0) q[0];    
+     r(pi, pi / 2.0) q[0];
 """
     parser = QasmParser()
 
@@ -871,9 +873,9 @@ def test_r_gate():
 def test_standard_single_qubit_gates_wrong_number_of_args(qasm_gate):
     qasm = f"""
      OPENQASM 2.0;
-     include "qelib1.inc";             
-     qreg q[2];     
-     {qasm_gate} q[0], q[1];     
+     include "qelib1.inc";
+     qreg q[2];
+     {qasm_gate} q[0], q[1];
 """
 
     parser = QasmParser()
@@ -889,9 +891,9 @@ def test_standard_single_qubit_gates_wrong_number_of_args(qasm_gate):
 )
 def test_standard_gates_wrong_params_error(qasm_gate: str, num_params: int):
     qasm = f"""OPENQASM 2.0;
-     include "qelib1.inc";             
-     qreg q[2];     
-     {qasm_gate}(pi, 2*pi, 3*pi, 4*pi, 5*pi) q[1];     
+     include "qelib1.inc";
+     qreg q[2];
+     {qasm_gate}(pi, 2*pi, 3*pi, 4*pi, 5*pi) q[1];
 """
 
     parser = QasmParser()
@@ -903,9 +905,9 @@ def test_standard_gates_wrong_params_error(qasm_gate: str, num_params: int):
         return
 
     qasm = f"""OPENQASM 2.0;
-     include "qelib1.inc";             
-     qreg q[2];     
-     {qasm_gate} q[1];     
+     include "qelib1.inc";
+     qreg q[2];
+     {qasm_gate} q[1];
     """
 
     parser = QasmParser()
@@ -1227,3 +1229,273 @@ def test_openqasm_3_0_scalar_qubit():
 
     ct.assert_same_circuits(parsed_qasm.circuit, expected_circuit)
     assert parsed_qasm.qregs == {'q': 1}
+
+
+def test_custom_gate():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[2];
+     gate g q0, q1 {
+        x q0;
+        y q0;
+        z q1;
+     }
+     g q[0], q[1];
+     g q[1], q[0];
+    """
+
+    # The gate definition should translate to this
+    q0, q1 = cirq.NamedQubit.range(2, prefix='q')
+    g = cirq.FrozenCircuit(cirq.X(q0), cirq.Y(q0), cirq.Z(q1))
+
+    # The outer circuit should then translate to this
+    q_0, q_1 = cirq.NamedQubit.range(2, prefix='q_')  # The outer qreg array
+    expected = cirq.Circuit(
+        cirq.CircuitOperation(g, qubit_map={q0: q_0, q1: q_1}),
+        cirq.CircuitOperation(g, qubit_map={q0: q_1, q1: q_0}),
+    )
+
+    # Verify
+    parser = QasmParser()
+    parsed_qasm = parser.parse(qasm)
+    assert parsed_qasm.circuit == expected
+
+    # Sanity check that this unrolls to a valid circuit
+    unrolled_expected = cirq.Circuit(
+        cirq.X(q_0), cirq.Y(q_0), cirq.Z(q_1), cirq.X(q_1), cirq.Y(q_1), cirq.Z(q_0)
+    )
+    unrolled = cirq.align_left(cirq.unroll_circuit_op(parsed_qasm.circuit, tags_to_check=None))
+    assert unrolled == unrolled_expected
+
+    # Sanity check that these have the same unitaries as the QASM.
+    cq.assert_qiskit_parsed_qasm_consistent_with_unitary(qasm, cirq.unitary(parsed_qasm.circuit))
+    cq.assert_qiskit_parsed_qasm_consistent_with_unitary(qasm, cirq.unitary(unrolled))
+
+
+def test_custom_gate_parameterized():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[2];
+     gate g(p0, p1) q0, q1 {
+        rx(p0) q0;
+        ry(p0+p1+3) q0;
+        rz(p1) q1;
+     }
+     g(1,2) q[0], q[1];
+     g(0,4) q[1], q[0];
+    """
+
+    # The gate definition should translate to this
+    p0, p1 = sympy.symbols('p0, p1')
+    q0, q1 = cirq.NamedQubit.range(2, prefix='q')
+    g = cirq.FrozenCircuit(
+        cirq.Rx(rads=p0).on(q0), cirq.Ry(rads=p0 + p1 + 3).on(q0), cirq.Rz(rads=p1).on(q1)
+    )
+
+    # The outer circuit should then translate to this
+    q_0, q_1 = cirq.NamedQubit.range(2, prefix='q_')  # The outer qreg array
+    expected = cirq.Circuit(
+        cirq.CircuitOperation(g, qubit_map={q0: q_0, q1: q_1}, param_resolver={'p0': 1, 'p1': 2}),
+        cirq.CircuitOperation(g, qubit_map={q0: q_1, q1: q_0}, param_resolver={'p0': 0, 'p1': 4}),
+    )
+
+    # Verify
+    parser = QasmParser()
+    parsed_qasm = parser.parse(qasm)
+    assert parsed_qasm.circuit == expected
+
+    # Sanity check that this unrolls to a valid circuit
+    unrolled_expected = cirq.Circuit(
+        cirq.Rx(rads=1).on(q_0),
+        cirq.Ry(rads=6).on(q_0),
+        cirq.Rz(rads=2).on(q_1),
+        cirq.Rx(rads=0).on(q_1),
+        cirq.Ry(rads=7).on(q_1),
+        cirq.Rz(rads=4).on(q_0),
+    )
+    unrolled = cirq.align_left(cirq.unroll_circuit_op(parsed_qasm.circuit, tags_to_check=None))
+    assert unrolled == unrolled_expected
+
+    # Sanity check that these have the same unitaries as the QASM.
+    cq.assert_qiskit_parsed_qasm_consistent_with_unitary(qasm, cirq.unitary(parsed_qasm.circuit))
+    cq.assert_qiskit_parsed_qasm_consistent_with_unitary(qasm, cirq.unitary(unrolled))
+
+
+def test_custom_gate_broadcast():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[3];
+     gate g q0 {
+        x q0;
+        y q0;
+        z q0;
+     }
+     g q; // broadcast to all qubits in register
+    """
+
+    # The gate definition should translate to this
+    q0 = cirq.NamedQubit('q0')
+    g = cirq.FrozenCircuit(cirq.X(q0), cirq.Y(q0), cirq.Z(q0))
+
+    # The outer circuit should then translate to this
+    q_0, q_1, q_2 = cirq.NamedQubit.range(3, prefix='q_')  # The outer qreg array
+    expected = cirq.Circuit(
+        # It is broadcast to all qubits in the qreg
+        cirq.CircuitOperation(g, qubit_map={q0: q_0}),
+        cirq.CircuitOperation(g, qubit_map={q0: q_1}),
+        cirq.CircuitOperation(g, qubit_map={q0: q_2}),
+    )
+
+    # Verify
+    parser = QasmParser()
+    parsed_qasm = parser.parse(qasm)
+    assert parsed_qasm.circuit == expected
+
+    # Sanity check that this unrolls to a valid circuit
+    unrolled_expected = cirq.Circuit(
+        cirq.X(q_0),
+        cirq.Y(q_0),
+        cirq.Z(q_0),
+        cirq.X(q_1),
+        cirq.Y(q_1),
+        cirq.Z(q_1),
+        cirq.X(q_2),
+        cirq.Y(q_2),
+        cirq.Z(q_2),
+    )
+    unrolled = cirq.align_left(cirq.unroll_circuit_op(parsed_qasm.circuit, tags_to_check=None))
+    assert unrolled == unrolled_expected
+
+    # Sanity check that these have the same unitaries as the QASM.
+    cq.assert_qiskit_parsed_qasm_consistent_with_unitary(qasm, cirq.unitary(parsed_qasm.circuit))
+    cq.assert_qiskit_parsed_qasm_consistent_with_unitary(qasm, cirq.unitary(unrolled))
+
+
+def test_custom_gate_undefined_qubit_error():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[1];
+     gate g q0 { x q1; }
+     g q
+    """
+    _test_parse_exception(
+        qasm,
+        cirq_err="Undefined qubit 'q1' at line 4",
+        qiskit_err="4,19: 'q1' is not defined in this scope",
+    )
+
+
+def test_custom_gate_qubit_scope_closure_error():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[1];
+     gate g q0 { x q; }
+     g q
+    """
+    _test_parse_exception(
+        qasm,
+        cirq_err="'q' is a register, not a qubit at line 4",
+        qiskit_err="4,19: 'q' is a quantum register, not a qubit",
+    )
+
+
+def test_custom_gate_qubit_index_error():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[1];
+     gate g q0 { x q0[0]; }
+     g q
+    """
+    _test_parse_exception(
+        qasm,
+        cirq_err="Unsupported indexed qreg 'q0[0]' at line 4",
+        qiskit_err="4,21: needed ';', but instead saw [",
+    )
+
+
+def test_custom_gate_qreg_count_error():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[2];
+     gate g q0 { x q0; }
+     g q[0], q[1];
+    """
+    _test_parse_exception(
+        qasm,
+        cirq_err="Wrong number of qregs for 'g' at line 5",
+        qiskit_err="5,5: 'g' takes 1 quantum argument, but got 2",
+    )
+
+
+def test_custom_gate_missing_param_error():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[1];
+     gate g(p) q0 { rx(p) q0; }
+     g q;
+    """
+    _test_parse_exception(
+        qasm,
+        cirq_err="Wrong number of params for 'g' at line 5",
+        qiskit_err=None,  # Qiskit bug? It's an invalid circuit that won't simulate.
+    )
+
+
+def test_custom_gate_extra_param_error():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[1];
+     gate g q0 { x q0; }
+     g(3) q;
+    """
+    _test_parse_exception(
+        qasm,
+        cirq_err="Wrong number of params for 'g' at line 5",
+        qiskit_err="5,5: 'g' takes 0 parameters, but got 1",
+    )
+
+
+def test_custom_gate_undefined_param_error():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[1];
+     gate g q0 { rx(p) q0; }
+     g q;
+    """
+    _test_parse_exception(
+        qasm,
+        cirq_err="Undefined parameter 'p' in line 4",
+        qiskit_err="4,20: 'p' is not a parameter",
+    )
+
+
+def test_top_level_param_error():
+    qasm = """OPENQASM 2.0;
+     include "qelib1.inc";
+     qreg q[1];
+     rx(p) q;
+    """
+    _test_parse_exception(
+        qasm,
+        cirq_err="Parameter 'p' in line 4 not supported",
+        qiskit_err="4,8: 'p' is not a parameter",
+    )
+
+
+def _test_parse_exception(qasm: str, cirq_err: str, qiskit_err: str | None):
+    parser = QasmParser()
+    with pytest.raises(QasmException, match=re.escape(cirq_err)):
+        parser.parse(qasm)
+    try:
+        import qiskit
+
+        if qiskit_err is None:
+            qiskit.QuantumCircuit.from_qasm_str(qasm)
+            return
+        with pytest.raises(qiskit.qasm2.exceptions.QASM2ParseError, match=re.escape(qiskit_err)):
+            qiskit.QuantumCircuit.from_qasm_str(qasm)
+    except ImportError:  # pragma: no cover
+        warnings.warn(
+            "Skipped _test_qiskit_parse_exception because "
+            "qiskit isn't installed to verify against."
+        )

{cirq_core-1.5.0.dev20250116193042.dist-info → cirq_core-1.5.0.dev20250117150435.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: cirq-core
-Version: 1.5.0.dev20250116193042
+Version: 1.5.0.dev20250117150435
 Summary: A framework for creating, editing, and invoking Noisy Intermediate Scale Quantum (NISQ) circuits.
 Home-page: http://github.com/quantumlib/cirq
 Author: The Cirq Developers

{cirq_core-1.5.0.dev20250116193042.dist-info → cirq_core-1.5.0.dev20250117150435.dist-info}/RECORD

@@ -4,8 +4,8 @@ cirq/_compat_test.py,sha256=Qq3ZcfgD-Nb81cEppQdJqhAyrVqXKtfXZYGXT0p-Wh0,34718
 cirq/_doc.py,sha256=yDyWUD_2JDS0gShfGRb-rdqRt9-WeL7DhkqX7np0Nko,2879
 cirq/_import.py,sha256=p9gMHJscbtDDkfHOaulvd3Aer0pwUF5AXpL89XR8dNw,8402
 cirq/_import_test.py,sha256=6K_v0riZJXOXUphHNkGA8MY-JcmGlezFaGmvrNhm3OQ,1015
-cirq/_version.py,sha256=QXvghHl0V3mA8QJwT7jY-pR45Mk27wAFagBcxt2R9QY,1206
-cirq/_version_test.py,sha256=YqqtIAbpKDIr_L8hhTwOlAu9t3p8aXBKP7VKIyLNW7M,147
+cirq/_version.py,sha256=itApAPrU3Nlc0VUngXvFdgN9PaFtg2kTcCJJEgOVmN8,1206
+cirq/_version_test.py,sha256=EMPy4rHRA_aLjLjLms6KEjlYqaJa0XIDyRK_fpequU8,147
 cirq/conftest.py,sha256=X7yLFL8GLhg2CjPw0hp5e_dGASfvHx1-QT03aUbhKJw,1168
 cirq/json_resolver_cache.py,sha256=cpbvJMNIh0U-l1mEVb-TqhJUEXfm2vpuR3v432ORSmg,13702
 cirq/py.typed,sha256=VFSlmh_lNwnaXzwY-ZuW-C2Ws5PkuDoVgBdNCs0jXJE,63
@@ -28,7 +28,7 @@ cirq/circuits/moment.py,sha256=y9hyP-QObxgL64a1veeTwDsqdGHbDkbE_o1VmgsfY6Y,26203
 cirq/circuits/moment_test.py,sha256=oNHNXhiPEoCKbzeh16tRwiW1qZWlg4X2O_uiVDP1D58,27375
 cirq/circuits/optimization_pass.py,sha256=uw3ne0-ebZo6GNjwfQMuQ3b5u9RCgyaXRfhpbljlxao,6468
 cirq/circuits/optimization_pass_test.py,sha256=eQB0NBJ9EvqjgSFGQMgaHIh5niQhksdnvqSXhsj3nOg,5947
-cirq/circuits/qasm_output.py,sha256=QUOeggq7NK3qm342dk47SNRi2qh4_98_gI3SdPjqRkA,13073
+cirq/circuits/qasm_output.py,sha256=fHbD2OeRzC0ZIvpN551JMaXDMTih7z9ZUIeCY6zQDQU,13090
 cirq/circuits/qasm_output_test.py,sha256=PawmzjqGpwauWgESqoi_U_iaYVZAMg_eIhZ_2VrPkPw,13634
 cirq/circuits/text_diagram_drawer.py,sha256=ctZUG5fk2pf4XswHTJG4kteQYzzH0TefL9JWUagLJvc,17232
 cirq/circuits/text_diagram_drawer_test.py,sha256=2bSoBIeQajRi0aQxqYDpbMlT2eqpx_f-Cmg9XO6A9Jk,10750
@@ -103,10 +103,10 @@ cirq/contrib/paulistring/recombine_test.py,sha256=hJ083nR67JsIs38TfmCjmBLnhqyG0r
 cirq/contrib/paulistring/separate.py,sha256=2g4l78mXYJDR6xkv51VExZDb-rm5JEvhYrpMPgWa0Us,3961
 cirq/contrib/paulistring/separate_test.py,sha256=FzR78MSHDhNJxizbXreK6u3BeYhT7xn7W1QyHfEZ34E,1267
 cirq/contrib/qasm_import/__init__.py,sha256=RKX0vGDC2Pe5rH5rM4ClXdvtrAU16ePFImQpiJtJVNo,744
-cirq/contrib/qasm_import/_lexer.py,sha256=J0ExK_6VGMoql0ha0hrxHzbFuqFYazHSSruhgznI66Y,3366
-cirq/contrib/qasm_import/_lexer_test.py,sha256=iiz-cmIt5hnhHBc4ub4btqHnbi4EPaO7BE7bsJKPet8,4142
-cirq/contrib/qasm_import/_parser.py,sha256=JroR-z7EcUhVd2-556h007H7SnzmmbqM4tsSOwsvwNw,21061
-cirq/contrib/qasm_import/_parser_test.py,sha256=EliIovGMcHYxgyxm12D41dN7LCM4oBL1okhSsUw0BzM,31706
+cirq/contrib/qasm_import/_lexer.py,sha256=DFfDArOd8F46XNjmvGR3EW-TA2d8Tn3unSoQIg_krMw,3453
+cirq/contrib/qasm_import/_lexer_test.py,sha256=lFLgL-D_-tXJOQJjwg_49tzhUqFnikvbB_SwV_s8qOg,5655
+cirq/contrib/qasm_import/_parser.py,sha256=qyU4q9Fz-hJBlh9swcEeNCwJ8YUORrgMJoc-f9bbldA,25997
+cirq/contrib/qasm_import/_parser_test.py,sha256=gW1sk7EKUgQP79t-RtgeiCeI88Vtp-zqy2f-yEHU91E,39299
 cirq/contrib/qasm_import/exception.py,sha256=Wm6cwUPIkNMPjkv-ELpQ-zSoXaiLOddOQ4iYybwuS6I,695
 cirq/contrib/qasm_import/qasm.py,sha256=CP444IWCw4zlDNA7HxsTJ2xIak4mZhQv62ZiLlUc2zo,914
 cirq/contrib/qasm_import/qasm_test.py,sha256=e5b7LVn_6FIFZ6kINqMzJFIjzgtTgutVhgXgX_DcTc0,1861
@@ -1203,8 +1203,8 @@ cirq/work/sampler.py,sha256=bE5tmVkcR6cZZMLETxDfHehdsYUMbx2RvBeIBetehI4,19187
 cirq/work/sampler_test.py,sha256=hL2UWx3dz2ukZVNxWftiKVvJcQoLplLZdQm-k1QcA40,13282
 cirq/work/zeros_sampler.py,sha256=x1C7cup66a43n-3tm8QjhiqJa07qcJW10FxNp9jJ59Q,2356
 cirq/work/zeros_sampler_test.py,sha256=JIkpBBFPJe5Ba4142vzogyWyboG1Q1ZAm0UVGgOoZn8,3279
-cirq_core-1.5.0.dev20250116193042.dist-info/LICENSE,sha256=tAkwu8-AdEyGxGoSvJ2gVmQdcicWw3j1ZZueVV74M-E,11357
-cirq_core-1.5.0.dev20250116193042.dist-info/METADATA,sha256=EigUVU1kx6_BuDpu3sMOZSL28HbwHQM2cWvKOcZiwQc,2105
-cirq_core-1.5.0.dev20250116193042.dist-info/WHEEL,sha256=tZoeGjtWxWRfdplE7E3d45VPlLNQnvbKiYnx7gwAy8A,92
-cirq_core-1.5.0.dev20250116193042.dist-info/top_level.txt,sha256=Sz9iOxHU0IEMLSFGwiwOCaN2e9K-jFbBbtpPN1hB73g,5
-cirq_core-1.5.0.dev20250116193042.dist-info/RECORD,,
+cirq_core-1.5.0.dev20250117150435.dist-info/LICENSE,sha256=tAkwu8-AdEyGxGoSvJ2gVmQdcicWw3j1ZZueVV74M-E,11357
+cirq_core-1.5.0.dev20250117150435.dist-info/METADATA,sha256=gWBedqQ5REYCU3Q306OsPbAe5WThkyD63buc3ivxSiY,2105
+cirq_core-1.5.0.dev20250117150435.dist-info/WHEEL,sha256=tZoeGjtWxWRfdplE7E3d45VPlLNQnvbKiYnx7gwAy8A,92
+cirq_core-1.5.0.dev20250117150435.dist-info/top_level.txt,sha256=Sz9iOxHU0IEMLSFGwiwOCaN2e9K-jFbBbtpPN1hB73g,5
+cirq_core-1.5.0.dev20250117150435.dist-info/RECORD,,