cirq-core 1.5.0.dev20241120163208__py3-none-any.whl → 1.5.0.dev20241120181130__py3-none-any.whl

cirq/_version.py

@@ -28,4 +28,4 @@ if sys.version_info < (3, 10, 0):  # pragma: no cover
         'of cirq (e.g. "python -m pip install cirq==1.1.*")'
     )
 
-__version__ = "1.5.0.dev20241120163208"
+__version__ = "1.5.0.dev20241120181130"

cirq/_version_test.py

@@ -3,4 +3,4 @@ import cirq
 
 
 def test_version():
-    assert cirq.__version__ == "1.5.0.dev20241120163208"
+    assert cirq.__version__ == "1.5.0.dev20241120181130"

cirq/contrib/qasm_import/_lexer.py

@@ -24,10 +24,12 @@ class QasmLexer:
     def __init__(self):
         self.lex = lex.lex(object=self, debug=False)
 
-    literals = "{}[]();,+/*-^"
+    literals = "{}[]();,+/*-^="
 
     reserved = {
+        'qubit': 'QUBIT',
         'qreg': 'QREG',
+        'bit': 'BIT',
         'creg': 'CREG',
         'measure': 'MEASURE',
         'if': 'IF',
@@ -35,9 +37,15 @@ class QasmLexer:
         '==': 'EQ',
     }
 
-    tokens = ['FORMAT_SPEC', 'NUMBER', 'NATURAL_NUMBER', 'QELIBINC', 'ID', 'PI'] + list(
-        reserved.values()
-    )
+    tokens = [
+        'FORMAT_SPEC',
+        'NUMBER',
+        'NATURAL_NUMBER',
+        'STDGATESINC',
+        'QELIBINC',
+        'ID',
+        'PI',
+    ] + list(reserved.values())
 
     def t_newline(self, t):
         r"""\n+"""
@@ -83,14 +91,26 @@ class QasmLexer:
         r"""include(\s+)"qelib1.inc";"""
         return t
 
+    def t_STDGATESINC(self, t):
+        r"""include(\s+)"stdgates.inc";"""
+        return t
+
     def t_QREG(self, t):
         r"""qreg"""
         return t
 
+    def t_QUBIT(self, t):
+        r"""qubit"""
+        return t
+
     def t_CREG(self, t):
         r"""creg"""
         return t
 
+    def t_BIT(self, t):
+        r"""bit"""
+        return t
+
     def t_MEASURE(self, t):
         r"""measure"""
         return t

cirq/contrib/qasm_import/_parser.py

@@ -270,6 +270,7 @@ class QasmParser:
 
     def p_qasm_no_format_specified_error(self, p):
         """qasm : QELIBINC
+        | STDGATESINC
         | circuit"""
         if self.supported_format is False:
             raise QasmException("Missing 'OPENQASM 2.0;' statement")
@@ -279,15 +280,21 @@ class QasmParser:
         self.qelibinc = True
         p[0] = Qasm(self.supported_format, self.qelibinc, self.qregs, self.cregs, self.circuit)
 
+    def p_qasm_include_stdgates(self, p):
+        """qasm : qasm STDGATESINC"""
+        self.qelibinc = True
+        p[0] = Qasm(self.supported_format, self.qelibinc, self.qregs, self.cregs, self.circuit)
+
     def p_qasm_circuit(self, p):
         """qasm : qasm circuit"""
         p[0] = Qasm(self.supported_format, self.qelibinc, self.qregs, self.cregs, p[2])
 
     def p_format(self, p):
         """format : FORMAT_SPEC"""
-        if p[1] != "2.0":
+        if p[1] not in ["2.0", "3.0"]:
             raise QasmException(
-                f"Unsupported OpenQASM version: {p[1]}, only 2.0 is supported currently by Cirq"
+                f"Unsupported OpenQASM version: {p[1]}, "
+                "only 2.0 and 3.0 are supported currently by Cirq"
             )
 
     # circuit : new_reg circuit
@@ -315,13 +322,28 @@ class QasmParser:
 
     def p_new_reg(self, p):
         """new_reg : QREG ID '[' NATURAL_NUMBER ']' ';'
-        | CREG ID '[' NATURAL_NUMBER ']' ';'"""
-        name, length = p[2], p[4]
+        | QUBIT '[' NATURAL_NUMBER ']' ID ';'
+        | QUBIT ID ';'
+        | CREG ID '[' NATURAL_NUMBER ']' ';'
+        | BIT '[' NATURAL_NUMBER ']' ID ';'
+        | BIT ID ';'
+        """
+        if p[1] == "qreg" or p[1] == "creg":
+            # QREG ID '[' NATURAL_NUMBER ']' ';'
+            name, length = p[2], p[4]
+        else:
+            if len(p) < 5:
+                # QUBIT ID ';' | BIT ID ';'
+                name = p[2]
+                length = 1
+            else:
+                # QUBIT '[' NATURAL_NUMBER ']' ID ';'
+                name, length = p[5], p[3]
         if name in self.qregs.keys() or name in self.cregs.keys():
             raise QasmException(f"{name} is already defined at line {p.lineno(2)}")
         if length == 0:
             raise QasmException(f"Illegal, zero-length register '{name}' at line {p.lineno(4)}")
-        if p[1] == "qreg":
+        if p[1] == "qreg" or p[1] == "qubit":
             self.qregs[name] = length
         else:
             self.cregs[name] = length
@@ -485,9 +507,14 @@ class QasmParser:
     # measurement : MEASURE qarg ARROW carg
 
     def p_measurement(self, p):
-        """measurement : MEASURE qarg ARROW carg ';'"""
-        qreg = p[2]
-        creg = p[4]
+        """measurement : MEASURE qarg ARROW carg ';'
+        | carg '=' MEASURE qarg ';'"""
+        if p[1] == 'measure':
+            qreg = p[2]
+            creg = p[4]
+        else:
+            qreg = p[4]
+            creg = p[1]
 
         if len(qreg) != len(creg):
             raise QasmException(

cirq/contrib/qasm_import/_parser_test.py

@@ -1057,3 +1057,51 @@ def test_single_qubit_gates(qasm_gate: str, cirq_gate: cirq.Gate):
 
     ct.assert_same_circuits(parsed_qasm.circuit, expected_circuit)
     assert parsed_qasm.qregs == {'q': 2}
+
+
+def test_openqasm_3_0_qubits():
+    qasm = """OPENQASM 3.0;
+     include "stdgates.inc";
+     qubit[2] q;
+     bit[2] b;
+
+     x q[0];
+
+     b[0] = measure q[0];
+    """
+    parser = QasmParser()
+
+    q0 = cirq.NamedQubit('q_0')
+
+    expected_circuit = Circuit([cirq.X.on(q0), cirq.measure(q0, key='b_0')])
+
+    parsed_qasm = parser.parse(qasm)
+
+    assert parsed_qasm.supportedFormat
+
+    ct.assert_same_circuits(parsed_qasm.circuit, expected_circuit)
+    assert parsed_qasm.qregs == {'q': 2}
+
+
+def test_openqasm_3_0_scalar_qubit():
+    qasm = """OPENQASM 3.0;
+     include "stdgates.inc";
+     qubit q;
+     bit b;
+
+     x q;
+
+     b = measure q;
+    """
+    parser = QasmParser()
+
+    q0 = cirq.NamedQubit('q_0')
+
+    expected_circuit = Circuit([cirq.X.on(q0), cirq.measure(q0, key='b_0')])
+
+    parsed_qasm = parser.parse(qasm)
+
+    assert parsed_qasm.supportedFormat
+
+    ct.assert_same_circuits(parsed_qasm.circuit, expected_circuit)
+    assert parsed_qasm.qregs == {'q': 1}

{cirq_core-1.5.0.dev20241120163208.dist-info → cirq_core-1.5.0.dev20241120181130.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: cirq-core
-Version: 1.5.0.dev20241120163208
+Version: 1.5.0.dev20241120181130
 Summary: A framework for creating, editing, and invoking Noisy Intermediate Scale Quantum (NISQ) circuits.
 Home-page: http://github.com/quantumlib/cirq
 Author: The Cirq Developers

{cirq_core-1.5.0.dev20241120163208.dist-info → cirq_core-1.5.0.dev20241120181130.dist-info}/RECORD

@@ -4,8 +4,8 @@ cirq/_compat_test.py,sha256=Qq3ZcfgD-Nb81cEppQdJqhAyrVqXKtfXZYGXT0p-Wh0,34718
 cirq/_doc.py,sha256=yDyWUD_2JDS0gShfGRb-rdqRt9-WeL7DhkqX7np0Nko,2879
 cirq/_import.py,sha256=p9gMHJscbtDDkfHOaulvd3Aer0pwUF5AXpL89XR8dNw,8402
 cirq/_import_test.py,sha256=6K_v0riZJXOXUphHNkGA8MY-JcmGlezFaGmvrNhm3OQ,1015
-cirq/_version.py,sha256=QIb3tuB9AIOt1ws8jRDyC8bOA-JqqF5WwvE4ezZjV1o,1206
-cirq/_version_test.py,sha256=xq54nxrTncU1OKYghtg2oxLQJn2tg-NwfqCpNzJRcSs,147
+cirq/_version.py,sha256=2OWqbmzoA46VRJQ_rQM1qc8-NPDWvmZUNF4rMuEp-Ho,1206
+cirq/_version_test.py,sha256=AnC_NkSCz67ZzrvoWslWbEUWf_8sw8tZ2Uc8siHDEBE,147
 cirq/conftest.py,sha256=X7yLFL8GLhg2CjPw0hp5e_dGASfvHx1-QT03aUbhKJw,1168
 cirq/json_resolver_cache.py,sha256=ytePZtNZgKjOF2NiVpUTuotB-JKZmQNOFIFdvXqsxHw,13271
 cirq/py.typed,sha256=VFSlmh_lNwnaXzwY-ZuW-C2Ws5PkuDoVgBdNCs0jXJE,63
@@ -103,10 +103,10 @@ cirq/contrib/paulistring/recombine_test.py,sha256=hJ083nR67JsIs38TfmCjmBLnhqyG0r
 cirq/contrib/paulistring/separate.py,sha256=2g4l78mXYJDR6xkv51VExZDb-rm5JEvhYrpMPgWa0Us,3961
 cirq/contrib/paulistring/separate_test.py,sha256=FzR78MSHDhNJxizbXreK6u3BeYhT7xn7W1QyHfEZ34E,1267
 cirq/contrib/qasm_import/__init__.py,sha256=RKX0vGDC2Pe5rH5rM4ClXdvtrAU16ePFImQpiJtJVNo,744
-cirq/contrib/qasm_import/_lexer.py,sha256=busw1Td1pJR-MBNGW-km1i9t2XKEqZTZ3zJnG6vXkmA,2943
+cirq/contrib/qasm_import/_lexer.py,sha256=1BGtCS2RetdiYPNOe_ZnMeoEl-AVBvvee_7y-h8tYcE,3275
 cirq/contrib/qasm_import/_lexer_test.py,sha256=iiz-cmIt5hnhHBc4ub4btqHnbi4EPaO7BE7bsJKPet8,4142
-cirq/contrib/qasm_import/_parser.py,sha256=qaFAAmHgSqTwcFgzLCYp-tM-UHcdEVlQ3fJSkwQjPdo,19234
-cirq/contrib/qasm_import/_parser_test.py,sha256=WEP1xp7IPeXRmRlQn48OHZoQtkSyW5VVSDEFT-C_ae0,27391
+cirq/contrib/qasm_import/_parser.py,sha256=e9ztG69dYm8dewM6efizbMT-Mf1n88hffg4ToBu0pig,20153
+cirq/contrib/qasm_import/_parser_test.py,sha256=2XEfhoiHWDpnGh3yYrenekGTIYapDtf52AMzYulajRY,28374
 cirq/contrib/qasm_import/exception.py,sha256=Wm6cwUPIkNMPjkv-ELpQ-zSoXaiLOddOQ4iYybwuS6I,695
 cirq/contrib/qasm_import/qasm.py,sha256=CP444IWCw4zlDNA7HxsTJ2xIak4mZhQv62ZiLlUc2zo,914
 cirq/contrib/qasm_import/qasm_test.py,sha256=e5b7LVn_6FIFZ6kINqMzJFIjzgtTgutVhgXgX_DcTc0,1861
@@ -1187,8 +1187,8 @@ cirq/work/sampler.py,sha256=y6qtCpAwO8SqZ_JKU8PwlbMLHpJskNPqGWD_pNbyZew,19779
 cirq/work/sampler_test.py,sha256=hL2UWx3dz2ukZVNxWftiKVvJcQoLplLZdQm-k1QcA40,13282
 cirq/work/zeros_sampler.py,sha256=x1C7cup66a43n-3tm8QjhiqJa07qcJW10FxNp9jJ59Q,2356
 cirq/work/zeros_sampler_test.py,sha256=JIkpBBFPJe5Ba4142vzogyWyboG1Q1ZAm0UVGgOoZn8,3279
-cirq_core-1.5.0.dev20241120163208.dist-info/LICENSE,sha256=tAkwu8-AdEyGxGoSvJ2gVmQdcicWw3j1ZZueVV74M-E,11357
-cirq_core-1.5.0.dev20241120163208.dist-info/METADATA,sha256=qflTCIVln0_4cA3bMs9u6lHgJXCJ9MsNe7eXBhCHWa0,1992
-cirq_core-1.5.0.dev20241120163208.dist-info/WHEEL,sha256=bFJAMchF8aTQGUgMZzHJyDDMPTO3ToJ7x23SLJa1SVo,92
-cirq_core-1.5.0.dev20241120163208.dist-info/top_level.txt,sha256=Sz9iOxHU0IEMLSFGwiwOCaN2e9K-jFbBbtpPN1hB73g,5
-cirq_core-1.5.0.dev20241120163208.dist-info/RECORD,,
+cirq_core-1.5.0.dev20241120181130.dist-info/LICENSE,sha256=tAkwu8-AdEyGxGoSvJ2gVmQdcicWw3j1ZZueVV74M-E,11357
+cirq_core-1.5.0.dev20241120181130.dist-info/METADATA,sha256=_6hfBHZQ9TowgdKEolGxgbVkVpsosrBA17nNJsCGl9E,1992
+cirq_core-1.5.0.dev20241120181130.dist-info/WHEEL,sha256=bFJAMchF8aTQGUgMZzHJyDDMPTO3ToJ7x23SLJa1SVo,92
+cirq_core-1.5.0.dev20241120181130.dist-info/top_level.txt,sha256=Sz9iOxHU0IEMLSFGwiwOCaN2e9K-jFbBbtpPN1hB73g,5
+cirq_core-1.5.0.dev20241120181130.dist-info/RECORD,,