boulder-opal-scale-up-sdk 1.0.6__py3-none-any.whl → 1.0.8__py3-none-any.whl

{boulder_opal_scale_up_sdk-1.0.6.dist-info → boulder_opal_scale_up_sdk-1.0.8.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.3
 Name: boulder-opal-scale-up-sdk
-Version: 1.0.6
+Version: 1.0.8
 Summary: Q-CTRL Boulder Opal Scale Up Python SDK
 License: https://q-ctrl.com/terms
 Keywords: black opal,boulder opal,fire opal,nisq,open controls,q control,q ctrl,q-control,q-ctrl,qcontrol,qctrl,quantum,quantum algorithms,quantum circuits,quantum coding,quantum coding software,quantum computing,quantum control,quantum control software,quantum control theory,quantum engineering,quantum error correction,quantum firmware,quantum fundamentals,quantum sensing,qubit,qudit
@@ -14,10 +14,8 @@ Classifier: Environment :: Console
 Classifier: Intended Audience :: Developers
 Classifier: Intended Audience :: Education
 Classifier: Intended Audience :: Science/Research
-Classifier: License :: Other/Proprietary License
 Classifier: Natural Language :: English
 Classifier: Operating System :: OS Independent
-Classifier: Programming Language :: Python :: 3
 Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Topic :: Internet :: WWW/HTTP
@@ -27,13 +25,13 @@ Classifier: Topic :: Software Development :: Embedded Systems
 Classifier: Topic :: System :: Distributed Computing
 Provides-Extra: quantum-machines
 Requires-Dist: attrs (>=25.1.0,<26.0.0)
-Requires-Dist: googleapis-common-protos (>=1.69.2,<2.0.0)
-Requires-Dist: numpy (>=1.26.4,<2.0.0)
+Requires-Dist: googleapis-common-protos (>=1.69.2,<1.70.0)
+Requires-Dist: numpy (>=2.3.3,<3.0.0)
 Requires-Dist: pydantic (>=2.10.4,<3.0.0)
 Requires-Dist: pydantic-settings (>=2.7.0,<3.0.0)
 Requires-Dist: python-dateutil (>=2.9.0.post0,<3.0.0)
 Requires-Dist: pyyaml (>=6.0.2,<7.0.0)
-Requires-Dist: qm-qua (==1.2.1) ; extra == "quantum-machines"
+Requires-Dist: qm-qua ; extra == "quantum-machines"
 Project-URL: Facebook, https://www.facebook.com/qctrl
 Project-URL: GitHub, https://github.com/qctrl
 Project-URL: Homepage, https://q-ctrl.com

{boulder_opal_scale_up_sdk-1.0.6.dist-info → boulder_opal_scale_up_sdk-1.0.8.dist-info}/RECORD

@@ -2,7 +2,7 @@ boulderopalscaleupsdk/__init__.py,sha256=nD3YDqPiE52mmuUrIlDUrYSyljpMsDJvc5HsubB
 boulderopalscaleupsdk/agent/__init__.py,sha256=aFkAtHJDOdXA126JklxYz0ix1k4lCcLLS9DQp8zUKMk,1092
 boulderopalscaleupsdk/agent/worker.py,sha256=mCwVMbWw2saAQKyQuozhEz9JJDwpezesItZim-5qWQ8,9176
 boulderopalscaleupsdk/common/__init__.py,sha256=vLaJ1FP36xV5eX6VD7nShqxVBm3UzsBMIK1pmSiTIag,550
-boulderopalscaleupsdk/common/dtypes.py,sha256=YAq0qb85-YkGP1idsO5uplm_xVvTEcED9_A81-Jco3c,10722
+boulderopalscaleupsdk/common/dtypes.py,sha256=r5ht75tCHNZUfq7jlmlUVEtKgYFOo1n35zgOWj6n6z8,11639
 boulderopalscaleupsdk/common/typeclasses.py,sha256=dUpM4vDNQCxVuB45LTyEWO7SuLyzUlG6mJuseM80Chw,3668
 boulderopalscaleupsdk/constants.py,sha256=2B3LrPH8bAQzzlkRYP5nyIkRT3LmfdIzzxiFKHWICPQ,682
 boulderopalscaleupsdk/device/__init__.py,sha256=vLaJ1FP36xV5eX6VD7nShqxVBm3UzsBMIK1pmSiTIag,550
@@ -10,70 +10,77 @@ boulderopalscaleupsdk/device/common.py,sha256=NxiFdpHXd1Es2_8iqUeAqhL4R4W-POzHoW
 boulderopalscaleupsdk/device/config_loader.py,sha256=kGUaUtYAREYN7grtQ9SUO3dPUqiHVUnVOQbXFZpXvtw,3414
 boulderopalscaleupsdk/device/controller/__init__.py,sha256=ePkrCbX1ORm05fS0BEQ8cx7DPxGGN6IkUoNH6eQL1DM,1136
 boulderopalscaleupsdk/device/controller/base.py,sha256=xuT4VzRulknxppiQpzYYn_TwuRNfV9wHMqjN2okA8Lw,793
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 boulderopalscaleupsdk/device/controller/quantum_machines.py,sha256=dkBSAqdEDADpn-qq7SkiZ-Rfnwh1NLQruqJGEW06ikU,7784
 boulderopalscaleupsdk/device/controller/resolver.py,sha256=hW5U58dmJf_IGmD4EK_bbn0XU-N9autFBFHmqbRnY2Y,3812
 boulderopalscaleupsdk/device/defcal.py,sha256=3IPmcLx89ZDv9sCPncozWA-hhnZRZK3OiOiBcAW05lI,739
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+boulderopalscaleupsdk/device/device.py,sha256=3IzYd0n_Nus4n5bgZKIraUXWLcsfoThCkjQYG0ZVSZY,2170
 boulderopalscaleupsdk/device/processor/__init__.py,sha256=YLn1UTCIX0CYfah1muLXrhujJx7sz56JZQ4Pn4DnKd0,972
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 boulderopalscaleupsdk/grpc_interceptors/__init__.py,sha256=PkdOlllLbRWycofvGCCxDY60Ydp_U0QM5l4u3Fsnno4,616
 boulderopalscaleupsdk/grpc_interceptors/auth.py,sha256=PSe_b9ckqhcb3xf1Y4jpn1TjfEWfokkarqfUHIz6HIs,4165
 boulderopalscaleupsdk/grpc_interceptors/error.py,sha256=PeEH4eFGFfRNwBw8iDuKVQo02_mItAUVehYa7AiZNqI,12067
 boulderopalscaleupsdk/plotting/__init__.py,sha256=pkdCky3YHqc3PLRy_h9puJKAO4AqSJGebb26x7XayR4,959
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 boulderopalscaleupsdk/protobuf/v1/agent_pb2.py,sha256=r8vE_d7e5iG04UCDeV0FgxOVOSflOlwmSs2I5CotDBU,6147
 boulderopalscaleupsdk/protobuf/v1/agent_pb2.pyi,sha256=bwRNbnwbwkqx7OSE4EurVS6865zqdtqmTcRjwJNH7OI,3082
 boulderopalscaleupsdk/protobuf/v1/agent_pb2_grpc.py,sha256=gfv0Ncc6_MS38Lzj6NHYXhwJVo7qK7XYQiCsi-KTl5w,8593
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 boulderopalscaleupsdk/protobuf/v1/job_pb2.py,sha256=awz-VTyt6lMJmf8ulW4kxSk-U_pYQOoZAyieww-RvaQ,4737
 boulderopalscaleupsdk/protobuf/v1/job_pb2.pyi,sha256=C6ygytheTgOohv3bA_CoCFh1Dvqcwwi_1dCsI93kTm4,2354
 boulderopalscaleupsdk/protobuf/v1/job_pb2_grpc.py,sha256=rwMHUYSaNT8uScrRxwEtR5niA3ghNjqJ6mzKVniBT9Q,6336
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 boulderopalscaleupsdk/protobuf/v1/task_pb2_grpc.py,sha256=yP2FZ148RmSYFHivatCXuM13oRBDA5wBwmvhZQNBTXQ,5826
 boulderopalscaleupsdk/py.typed,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
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+boulder_opal_scale_up_sdk-1.0.8.dist-info/METADATA,sha256=DXWuUYplUMJ_Vr9UirCcED-gLLAqrV7MTCf-zY3ow7k,2312
+boulder_opal_scale_up_sdk-1.0.8.dist-info/WHEEL,sha256=IYZQI976HJqqOpQU6PHkJ8fb3tMNBFjg-Cn-pwAbaFM,88
+boulder_opal_scale_up_sdk-1.0.8.dist-info/RECORD,,

boulderopalscaleupsdk/common/dtypes.py

@@ -33,7 +33,7 @@ from dateutil.parser import isoparse
 from pydantic import BaseModel, BeforeValidator, ConfigDict, Field, PlainSerializer, TypeAdapter
 from pydantic.dataclasses import dataclass
 
-from boulderopalscaleupsdk.plotting.dtypes import Plot  # noqa: TC001
+from boulderopalscaleupsdk.plotting import Plot
 
 GrpcMetadata = list[tuple[str, str | bytes]]
 
@@ -158,7 +158,7 @@ class Duration:
 
         self.value = int(self.value)
         try:
-            self._np_rep = np.timedelta64(self.value, self.unit)
+            self._np_rep = np.timedelta64(self.value, self.unit.value)
         except ValueError as e:
             raise err from e
 
@@ -179,12 +179,17 @@ class Duration:
             return bool(self._np_rep == other._np_rep)
         return False
 
-    def convert(self, unit: TimeUnit) -> Duration | InvalidDurationConversion:
-        val: np.float64 = self._np_rep / np.timedelta64(1, unit)
+    def __str__(self):
+        return f"{self.value} {self.unit.value}"
+
+    def convert(self, unit: TimeUnit | str) -> Duration | InvalidDurationConversion:
+        unit_enum = TimeUnit(unit) if isinstance(unit, str) else unit
+
+        val = np.float64(self._np_rep / np.timedelta64(1, unit_enum.value))
         if val.is_integer():
-            return Duration(int(val), unit)
+            return Duration(int(val), unit_enum)
         return InvalidDurationConversion(
-            f"fail to convert to {unit} with {self.value} {self.unit}.",
+            f"fail to convert to {unit_enum} with {self.value} {self.unit}.",
         )
 
     def to_ns(self) -> Duration:
@@ -342,14 +347,17 @@ class JobSummary(BaseModel):
 
 class JobDataEntry(BaseModel):
     message: str
-    created_at: ISO8601DatetimeUTCLike
-    dt: str
-    elapsed_time: str
-    plots: list[Plot] = []
 
     class Config:
         extra = "allow"
 
+    def get_display_items(self) -> list[str | Plot]:
+        items: list[str | Plot] = [self.message]
+
+        if plots := getattr(self, "plots", []):
+            items.extend(TypeAdapter(Plot).validate_python(plot) for plot in plots)
+        return items
+
 
 class JobData(BaseModel):
     id: str
@@ -359,6 +367,24 @@ class JobData(BaseModel):
     device_name: str
     data: list[JobDataEntry]
 
+    def get_display_items(self) -> list[str | Plot]:
+        items: list[str | Plot] = []
+        message = "\n".join(
+            [
+                "JobData summary:",
+                f"  - id: {self.id}",
+                f"  - name: {self.name}",
+                f"  - session_id: {self.session_id}",
+                f"  - created_at: {self.created_at.isoformat()}",
+                f"  - device_name: {self.device_name}",
+            ],
+        )
+        items.append(message)
+
+        for job_data_entry in self.data:
+            items.extend(job_data_entry.get_display_items())
+        return items
+
 
 DEFAULT_JOB_HISTORY_PAGE = 1
 DEFAULT_JOB_HISTORY_PAGE_SIZE = 10

boulderopalscaleupsdk/device/controller/qblox.py

@@ -20,7 +20,8 @@ __all__ = (
     "AcquisitionConfig",
     "BitStrideArrayEncoding",
     "ChannelType",
-    "ComplexChannel",
+    "IQChannel",
+    "IQMixedChannel",
     "IndexedData",
     "ModuleAddr",
     "ModuleAddrType",
@@ -37,11 +38,11 @@ __all__ = (
     "PortAddrType",
     "PreparedProgram",
     "PreparedSequenceProgram",
-    "RealChannel",
     "SequenceProgram",
     "SequencerAddr",
     "SequencerAddrType",
     "SequencerResults",
+    "SingleChannel",
     "process_sequencer_output",
     "validate_channel",
 )
@@ -54,7 +55,7 @@ from dataclasses import dataclass
 from typing import Annotated, Any, ClassVar, Literal, Self, TypeVar
 
 import numpy as np
-from pydantic import BaseModel, BeforeValidator, Field, PlainSerializer, model_validator
+from pydantic import BaseModel, BeforeValidator, ConfigDict, Field, PlainSerializer, model_validator
 
 from boulderopalscaleupsdk.device.controller.base import Backend, ControllerType
 
@@ -204,10 +205,20 @@ PortAddrType = Annotated[PortAddr, _addr_validator(PortAddr), PlainSerializer(st
 # ==================================================================================================
 # Signalling Channels
 # ==================================================================================================
-class RealChannel(BaseModel):
-    """A real channel targeting a single hardware port on a QBLOX module."""
+class IQMixedChannel(BaseModel):
+    """
+    An IQ-mixed channel.
+
+    Both sequencer AWG paths are mixed internally and routed to a single module port.
+
+    ┌─────────┐Path 0           Port
+    │         ├───────►│IQMixed ┌─┐
+    │Sequencer│        │───────►│─│
+    │         ├───────►│Ch      └─┘
+    └─────────┘Path 1
+    """
 
-    mode: Literal["real"] = "real"
+    mode: Literal["iq-mixed"] = "iq-mixed"
     port: PortAddrType
 
     @property
@@ -219,13 +230,26 @@ class RealChannel(BaseModel):
         return self.port.direction
 
     def __str__(self) -> str:
-        return f"{self.port!s}[R]"
+        return f"{self.port!s}[1]"
+
 
+class IQChannel(BaseModel):
+    """
+    An IQ channel.
 
-class ComplexChannel(BaseModel):
-    """A Complex channel targeting a single hardware port on a QBLOX module."""
+    The sequencer AWG paths target separate ports for external IQ mixing.
 
-    mode: Literal["complex"] = "complex"
+                                IPort
+    ┌─────────┐Path 0           ┌─┐
+    │         ├───────►├───────►│─│
+    │Sequencer│        │IQ Ch   ├─┤
+    │         ├───────►├───────►│─│
+    └─────────┘Path 1           └─┘
+                                QPort
+
+    """
+
+    mode: Literal["iq"] = "iq"
     i_port: PortAddrType
     q_port: PortAddrType
 
@@ -238,10 +262,10 @@ class ComplexChannel(BaseModel):
         return self.i_port.direction
 
     def __str__(self) -> str:
-        return f"{self.i_port!s}_{self.q_port.number}[Z]"
+        return f"{self.i_port!s}_{self.q_port.number}[iq]"
 
     @model_validator(mode="after")
-    def validate_i_q_ports(self) -> "ComplexChannel":
+    def validate_i_q_ports(self) -> "IQChannel":
         ii = self.i_port
         qq = self.q_port
         if ii.cluster != qq.cluster or ii.slot != qq.slot:
@@ -251,7 +275,36 @@ class ComplexChannel(BaseModel):
         return self
 
 
-ChannelType = RealChannel | ComplexChannel
+class SingleChannel(BaseModel):
+    """
+    Single channel.
+
+    A single sequencer path is routed to a single port.
+
+    ┌─────────┐Path 0           Port
+    │         ├───────►│Single  ┌─┐
+    │Sequencer│        ├───────►│─│
+    │         │        │Ch      └─┘
+    └─────────┘
+    """
+
+    mode: Literal["single"] = "single"
+    port: PortAddrType
+    path: Literal[0, 1] = 0
+
+    @property
+    def module(self) -> ModuleAddr:
+        return ModuleAddr(self.port.cluster, self.port.slot)
+
+    @property
+    def direction(self) -> Literal["out", "in"]:
+        return self.port.direction
+
+    def __str__(self) -> str:
+        return f"{self.port!s}_{self.port.number}[single]"
+
+
+ChannelType = IQMixedChannel | IQChannel | SingleChannel
 
 
 # ==================================================================================================
@@ -318,12 +371,28 @@ class QBLOXControllerInfo(BaseModel):  # pragma: no cover
     modules: dict[ModuleAddrType, ModuleType]
     port_config: dict[str, PortConnection]
 
+    @model_validator(mode="after")
+    def validate_channels(self) -> Self:
+        for port, port_conn in self.port_config.items():
+            mod_addr = port_conn.ch_out.module
+            mod_type = self.modules[mod_addr]
+
+            mod_constraints = DEFAULT_MODULE_CONSTRAINTS[mod_type]
+            if ch_iss := validate_channel(port_conn.ch_out, mod_constraints):
+                raise ValueError(f"Invalid channel for port {port}: {ch_iss}")
+            if port_conn.ch_in and (ch_iss := validate_channel(port_conn.ch_in, mod_constraints)):
+                raise ValueError(f"Invalid channel for port {port}: {ch_iss}")
+
+        return self
+
 
 # ==================================================================================================
 # Instrument management
 # ==================================================================================================
 class SequencerParams(BaseModel):
-    nco_freq: float | None = Field(default=None)
+    model_config = ConfigDict(validate_assignment=True)
+
+    nco_freq: float | None = Field(default=None, ge=-500e6, le=500e6)
     gain_awg_path0: float | None = Field(default=None, ge=-1.0, le=1.0)
     offset_awg_path0: float | None = Field(default=None, ge=-1.0, le=1.0)
     gain_awg_path1: float | None = Field(default=None, ge=-1.0, le=1.0)
@@ -338,6 +407,8 @@ class SequencerParams(BaseModel):
 
 
 class QcmParams(BaseModel):
+    model_config = ConfigDict(validate_assignment=True)
+
     out0_offset: float | None = Field(default=None, ge=-2.5, le=2.5)
     out1_offset: float | None = Field(default=None, ge=-2.5, le=2.5)
     out2_offset: float | None = Field(default=None, ge=-2.5, le=2.5)
@@ -354,6 +425,8 @@ class QcmParams(BaseModel):
 
 
 class QcmRfParams(BaseModel):
+    model_config = ConfigDict(validate_assignment=True)
+
     out0_att: int | None = Field(default=None, ge=0, le=60, multiple_of=2)
     out1_att: int | None = Field(default=None, ge=0, le=60, multiple_of=2)
 
@@ -375,6 +448,8 @@ class QcmRfParams(BaseModel):
 
 
 class QrmRfParams(BaseModel):
+    model_config = ConfigDict(validate_assignment=True)
+
     out0_att: int | None = Field(default=None, ge=0, le=60, multiple_of=2)
 
     out0_in0_lo_freq: float | None = Field(default=None, gt=0)
@@ -744,6 +819,9 @@ class BitStrideArrayEncoding:
 # ==================================================================================================
 # Utilities
 # ==================================================================================================
+Q1_MAX_WAVEFORM_MEMORY = 16384  # samples
+
+
 @dataclasses.dataclass
 class ModuleConstraints:
     """Physical constraints of a module."""
@@ -753,6 +831,7 @@ class ModuleConstraints:
     n_ch_out: int = 0
     n_ch_in: int = 0
     n_digital_io: int = 0
+    is_rf: bool = False
 
     # TODO: Confirm if ordering is important.
     ch_out_iq_pairs: list[set[int]] = dataclasses.field(default_factory=list)
@@ -773,6 +852,7 @@ DEFAULT_MODULE_CONSTRAINTS: dict[ModuleType, ModuleConstraints] = {
         n_markers=2,
         n_ch_out=2,
         n_ch_in=0,
+        is_rf=True,
     ),
     ModuleType.QRM: ModuleConstraints(
         n_sequencers=6,
@@ -787,6 +867,7 @@ DEFAULT_MODULE_CONSTRAINTS: dict[ModuleType, ModuleConstraints] = {
         n_markers=2,
         n_ch_out=1,
         n_ch_in=1,
+        is_rf=True,
     ),
     ModuleType.QRC: ModuleConstraints(
         n_sequencers=12,
@@ -835,53 +916,77 @@ def validate_channel(ch: ChannelType, constraint: ModuleConstraints) -> list[str
     return _validate_input_channel(ch, constraint)
 
 
-def _validate_output_channel(ch_out: ChannelType, constraint: ModuleConstraints) -> list[str]:
+def _validate_output_channel(ch_out: ChannelType, constraint: ModuleConstraints) -> list[str]:  # noqa: C901
     issues = []
-    if isinstance(ch_out, RealChannel):
-        po_out = ch_out.port
-        if constraint.n_ch_out == 0:
-            issues.append("module has no output ports.")
-        elif po_out.number < 0 or po_out.number >= constraint.n_ch_out:
-            issues.append(
-                f"output port number {po_out.number} out-of-bounds for module, "
-                f"must be between [0, {constraint.n_ch_out}).",
-            )
-    else:
-        valid_pairs = constraint.ch_out_iq_pairs
-        if not valid_pairs:
-            issues.append("module does not support complex output channels.")
-        else:
-            po_out_i = ch_out.i_port
-            po_out_q = ch_out.q_port
-            if {po_out_i.number, po_out_q.number} not in valid_pairs:
+    match ch_out:
+        case IQMixedChannel():
+            po_out = ch_out.port
+            if constraint.n_ch_out == 0:
+                issues.append("module has no output ports.")
+            elif po_out.number < 0 or po_out.number >= constraint.n_ch_out:
                 issues.append(
-                    f"invalid output IQ pair {{{po_out_i.number}, {po_out_q.number}}}, module only "
-                    f"supports pairs {valid_pairs}.",
+                    f"output port number {po_out.number} out-of-bounds for module, "
+                    f"must be between [0, {constraint.n_ch_out}).",
+                )
+        case IQChannel():
+            valid_pairs = constraint.ch_out_iq_pairs
+            if not valid_pairs:
+                issues.append("module does not support IQ output channels.")
+            else:
+                po_out_i = ch_out.i_port
+                po_out_q = ch_out.q_port
+                if {po_out_i.number, po_out_q.number} not in valid_pairs:
+                    issues.append(
+                        f"invalid output IQ pair {{{po_out_i.number}, {po_out_q.number}}}, "
+                        f"module only supports pairs {valid_pairs}.",
+                    )
+        case SingleChannel():
+            po_out = ch_out.port
+            if constraint.is_rf:
+                issues.append("RF modules cannot use single channels.")
+            if constraint.n_ch_out == 0:
+                issues.append("module has no output ports.")
+            elif po_out.number < 0 or po_out.number >= constraint.n_ch_out:
+                issues.append(
+                    f"output port number {po_out.number} out-of-bounds for module, "
+                    f"must be between [0, {constraint.n_ch_out}).",
                 )
     return issues
 
 
-def _validate_input_channel(ch_in: ChannelType, constraint: ModuleConstraints) -> list[str]:
+def _validate_input_channel(ch_in: ChannelType, constraint: ModuleConstraints) -> list[str]:  # noqa: C901
     issues = []
-    if isinstance(ch_in, RealChannel):
-        po_in = ch_in.port
-        if constraint.n_ch_in == 0:
-            issues.append("module has no input ports.")
-        elif po_in.number < 0 or po_in.number >= constraint.n_ch_in:
-            issues.append(
-                f"input port number {po_in.number} out-of-bounds for module, "
-                f"must be between [0, {constraint.n_ch_in}).",
-            )
-    else:
-        valid_pairs = constraint.ch_in_iq_pairs
-        if not valid_pairs:
-            issues.append("module does not support complex input channels.")
-        else:
-            po_in_i = ch_in.i_port
-            po_in_q = ch_in.q_port
-            if {po_in_i.number, po_in_q.number} not in valid_pairs:
+    match ch_in:
+        case IQMixedChannel():
+            po_in = ch_in.port
+            if constraint.n_ch_in == 0:
+                issues.append("module has no input ports.")
+            elif po_in.number < 0 or po_in.number >= constraint.n_ch_in:
+                issues.append(
+                    f"input port number {po_in.number} out-of-bounds for module, "
+                    f"must be between [0, {constraint.n_ch_in}).",
+                )
+        case IQChannel():
+            valid_pairs = constraint.ch_in_iq_pairs
+            if not valid_pairs:
+                issues.append("module does not support IQ input channels.")
+            else:
+                po_in_i = ch_in.i_port
+                po_in_q = ch_in.q_port
+                if {po_in_i.number, po_in_q.number} not in valid_pairs:
+                    issues.append(
+                        f"invalid input IQ pair {{{po_in_i.number}, {po_in_q.number}}}, "
+                        f"module only supports pairs {valid_pairs}.",
+                    )
+        case SingleChannel():
+            po_in = ch_in.port
+            if constraint.is_rf:
+                issues.append("RF modules cannot use single channels.")
+            if constraint.n_ch_in == 0:
+                issues.append("module has no input ports.")
+            elif po_in.number < 0 or po_in.number >= constraint.n_ch_in:
                 issues.append(
-                    f"invalid input IQ pair {{{po_in_i.number}, {po_in_q.number}}}, module only "
-                    f"supports pairs {valid_pairs}.",
+                    f"input port number {po_in.number} out-of-bounds for module, "
+                    f"must be between [0, {constraint.n_ch_in}).",
                 )
     return issues

boulderopalscaleupsdk/device/device.py

@@ -61,7 +61,6 @@ class DeviceSummary(BaseModel):
     provider: str
     updated_at: ISO8601DatetimeUTCLike
     created_at: ISO8601DatetimeUTCLike
-    copied_from: DeviceName | None = None
 
     def __str__(self):
         return f'DeviceSummary(name="{self.name}", id="{self.id}")'