angr 9.2.62__py3-none-win_amd64.whl → 9.2.63__py3-none-win_amd64.whl
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- angr/__init__.py +1 -1
- angr/analyses/cfg/cfg_fast.py +18 -20
- angr/analyses/decompiler/clinic.py +144 -0
- angr/analyses/decompiler/condition_processor.py +4 -2
- angr/analyses/decompiler/peephole_optimizations/eager_eval.py +2 -0
- angr/analyses/decompiler/structured_codegen/c.py +9 -1
- angr/analyses/disassembly.py +7 -11
- angr/analyses/reaching_definitions/engine_ail.py +6 -1
- angr/analyses/reaching_definitions/engine_vex.py +16 -3
- angr/analyses/reaching_definitions/function_handler.py +9 -3
- angr/analyses/reaching_definitions/reaching_definitions.py +70 -9
- angr/analyses/variable_recovery/variable_recovery_fast.py +5 -0
- angr/calling_conventions.py +28 -0
- angr/knowledge_plugins/key_definitions/live_definitions.py +3 -0
- angr/knowledge_plugins/key_definitions/rd_model.py +22 -3
- angr/knowledge_plugins/variables/variable_manager.py +26 -4
- angr/lib/angr_native.dll +0 -0
- angr/project.py +2 -2
- angr/sim_type.py +2 -2
- angr/storage/memory_mixins/multi_value_merger_mixin.py +7 -2
- {angr-9.2.62.dist-info → angr-9.2.63.dist-info}/METADATA +15 -15
- {angr-9.2.62.dist-info → angr-9.2.63.dist-info}/RECORD +25 -25
- {angr-9.2.62.dist-info → angr-9.2.63.dist-info}/WHEEL +1 -1
- {angr-9.2.62.dist-info → angr-9.2.63.dist-info}/LICENSE +0 -0
- {angr-9.2.62.dist-info → angr-9.2.63.dist-info}/top_level.txt +0 -0
angr/__init__.py
CHANGED
angr/analyses/cfg/cfg_fast.py
CHANGED
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@@ -2714,30 +2714,28 @@ class CFGFast(ForwardAnalysis[CFGNode, CFGNode, CFGJob, int], CFGBase): # pylin
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2714
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for segment in self.project.loader.main_object.segments:
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if segment.vaddr + segment.memsize == data_addr:
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# yeah!
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-
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-
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-
self.kb.xrefs.add_xref(cr)
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+
self.model.add_memory_data(data_addr, MemoryDataSort.SegmentBoundary, data_size=0)
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cr = XRef(
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ins_addr=insn_addr,
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block_addr=irsb_addr,
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stmt_idx=stmt_idx,
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memory_data=self.model.memory_data[data_addr],
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xref_type=XRefType.Offset,
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)
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self.kb.xrefs.add_xref(cr)
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break
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return
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-
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-
self.kb.xrefs.add_xref(cr)
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self.model.add_memory_data(data_addr, data_type, data_size=data_size)
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cr = XRef(
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ins_addr=insn_addr,
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block_addr=irsb_addr,
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stmt_idx=stmt_idx,
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memory_data=self.model.memory_data[data_addr],
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xref_type=XRefType.Offset,
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)
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self.kb.xrefs.add_xref(cr)
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if is_arm_arch(self.project.arch):
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if (irsb_addr & 1) == 1 and data_addr == (insn_addr & 0xFFFF_FFFF_FFFF_FFFE) + 4:
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@@ -176,6 +176,7 @@ class Clinic(Analysis):
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self._convert_all()
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ail_graph = self._make_ailgraph()
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+
self._rewrite_ite_expressions(ail_graph)
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self._remove_redundant_jump_blocks(ail_graph)
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if self._insert_labels:
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self._insert_block_labels(ail_graph)
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@@ -1000,6 +1001,7 @@ class Clinic(Analysis):
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kb=tmp_kb,
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track_sp=False,
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func_args=arg_list,
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unify_variables=False,
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)
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# get ground-truth types
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var_manager = tmp_kb.variables[self.function.addr]
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@@ -1284,6 +1286,148 @@ class Clinic(Analysis):
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return graph
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+
def _rewrite_ite_expressions(self, ail_graph):
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for block in list(ail_graph):
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ite_ins_addrs = []
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for stmt in block.statements:
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if isinstance(stmt, ailment.Stmt.Assignment) and isinstance(stmt.src, ailment.Expr.ITE):
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if stmt.ins_addr not in ite_ins_addrs:
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ite_ins_addrs.append(stmt.ins_addr)
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if ite_ins_addrs:
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block_addr = block.addr
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for ite_ins_addr in ite_ins_addrs:
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block_addr = self._create_triangle_for_ite_expression(ail_graph, block_addr, ite_ins_addr)
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if block_addr is None or block_addr >= block.addr + block.original_size:
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break
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def _create_triangle_for_ite_expression(self, ail_graph, block_addr: int, ite_ins_addr: int):
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# lift the ite instruction to get its size
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ite_insn_size = self.project.factory.block(ite_ins_addr, num_inst=1).size
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if ite_insn_size <= 1: # we need an address for true_block and another address for false_block
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return None
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# relift the head and the ITE instruction
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new_head = self.project.factory.block(
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block_addr, size=ite_ins_addr - block_addr + ite_insn_size, cross_insn_opt=False
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)
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new_head_ail = ailment.IRSBConverter.convert(new_head.vex, self._ail_manager)
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# remove all statements between the ITE expression and the very end of the block
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ite_expr_stmt_idx = None
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ite_expr_stmt = None
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for idx, stmt in enumerate(new_head_ail.statements):
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if isinstance(stmt, ailment.Stmt.Assignment) and isinstance(stmt.src, ailment.Expr.ITE):
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ite_expr_stmt_idx = idx
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ite_expr_stmt = stmt
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break
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if ite_expr_stmt_idx is None:
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return None
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ite_expr: ailment.Expr.ITE = ite_expr_stmt.src
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new_head_ail.statements = new_head_ail.statements[:ite_expr_stmt_idx]
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# build the conditional jump
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true_block_addr = ite_ins_addr
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1330
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false_block_addr = ite_ins_addr + 1
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cond_jump_stmt = ailment.Stmt.ConditionalJump(
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ite_expr_stmt.idx,
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ite_expr.cond,
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ailment.Expr.Const(None, None, true_block_addr, self.project.arch.bits),
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ailment.Expr.Const(None, None, false_block_addr, self.project.arch.bits),
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**ite_expr_stmt.tags,
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)
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new_head_ail.statements.append(cond_jump_stmt)
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# build the true block
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true_block = self.project.factory.block(ite_ins_addr, num_inst=1)
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true_block_ail = ailment.IRSBConverter.convert(true_block.vex, self._ail_manager)
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true_block_ail.addr = true_block_addr
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ite_expr_stmt_idx = None
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1346
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ite_expr_stmt = None
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1347
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for idx, stmt in enumerate(true_block_ail.statements):
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1348
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if isinstance(stmt, ailment.Stmt.Assignment) and isinstance(stmt.src, ailment.Expr.ITE):
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1349
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ite_expr_stmt_idx = idx
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1350
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ite_expr_stmt = stmt
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break
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1352
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if ite_expr_stmt_idx is None:
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1353
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return None
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1354
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1355
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true_block_ail.statements[ite_expr_stmt_idx] = ailment.Stmt.Assignment(
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ite_expr_stmt.idx, ite_expr_stmt.dst, ite_expr_stmt.src.iftrue, **ite_expr_stmt.tags
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)
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# build the false block
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false_block = self.project.factory.block(ite_ins_addr, num_inst=1)
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false_block_ail = ailment.IRSBConverter.convert(false_block.vex, self._ail_manager)
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false_block_ail.addr = false_block_addr
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ite_expr_stmt_idx = None
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ite_expr_stmt = None
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for idx, stmt in enumerate(false_block_ail.statements):
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1367
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if isinstance(stmt, ailment.Stmt.Assignment) and isinstance(stmt.src, ailment.Expr.ITE):
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1368
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+
ite_expr_stmt_idx = idx
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1369
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ite_expr_stmt = stmt
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1370
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break
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1371
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if ite_expr_stmt_idx is None:
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1372
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+
return None
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1373
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+
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1374
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+
false_block_ail.statements[ite_expr_stmt_idx] = ailment.Stmt.Assignment(
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1375
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+
ite_expr_stmt.idx, ite_expr_stmt.dst, ite_expr_stmt.src.iffalse, **ite_expr_stmt.tags
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1376
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+
)
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1377
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+
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1378
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original_block = next(iter(b for b in ail_graph if b.addr == block_addr))
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1379
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+
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1380
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+
original_block_in_edges = list(ail_graph.in_edges(original_block))
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1381
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+
original_block_out_edges = list(ail_graph.out_edges(original_block))
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1382
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+
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1383
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+
# build the target block if the target block does not exist in the current function
|
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1384
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+
end_block_addr = ite_ins_addr + ite_insn_size
|
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1385
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+
if block_addr < end_block_addr < block_addr + original_block.original_size:
|
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1386
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+
end_block = self.project.factory.block(
|
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1387
|
+
ite_ins_addr + ite_insn_size,
|
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1388
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+
size=block_addr + original_block.original_size - (ite_ins_addr + ite_insn_size),
|
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1389
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+
cross_insn_opt=False,
|
|
1390
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+
)
|
|
1391
|
+
end_block_ail = ailment.IRSBConverter.convert(end_block.vex, self._ail_manager)
|
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1392
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+
else:
|
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1393
|
+
end_block_ail = next(iter(b for b in ail_graph if b.addr == end_block_addr))
|
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1394
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+
|
|
1395
|
+
# last check: if the first instruction of the end block has Sar, then we bail (due to the peephole optimization
|
|
1396
|
+
# SarToSignedDiv)
|
|
1397
|
+
for stmt in end_block_ail.statements:
|
|
1398
|
+
if stmt.ins_addr > end_block_ail.addr:
|
|
1399
|
+
break
|
|
1400
|
+
if (
|
|
1401
|
+
isinstance(stmt, ailment.Stmt.Assignment)
|
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1402
|
+
and isinstance(stmt.src, ailment.Expr.BinaryOp)
|
|
1403
|
+
and stmt.src.op == "Sar"
|
|
1404
|
+
):
|
|
1405
|
+
return None
|
|
1406
|
+
|
|
1407
|
+
ail_graph.remove_node(original_block)
|
|
1408
|
+
|
|
1409
|
+
if end_block_ail not in ail_graph:
|
|
1410
|
+
# newly created. add it and the necessary edges into the graph
|
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1411
|
+
for _, dst in original_block_out_edges:
|
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1412
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+
if dst is original_block:
|
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1413
|
+
ail_graph.add_edge(end_block_ail, new_head_ail)
|
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1414
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+
else:
|
|
1415
|
+
ail_graph.add_edge(end_block_ail, dst)
|
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1416
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+
|
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1417
|
+
# in edges
|
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1418
|
+
for src, _ in original_block_in_edges:
|
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1419
|
+
if src is original_block:
|
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1420
|
+
raise ValueError("Unexpected...")
|
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1421
|
+
ail_graph.add_edge(src, new_head_ail)
|
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1422
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+
|
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1423
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+
# triangle
|
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1424
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+
ail_graph.add_edge(new_head_ail, true_block_ail)
|
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1425
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+
ail_graph.add_edge(new_head_ail, false_block_ail)
|
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1426
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+
ail_graph.add_edge(true_block_ail, end_block_ail)
|
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1427
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+
ail_graph.add_edge(false_block_ail, end_block_ail)
|
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1428
|
+
|
|
1429
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+
return end_block_ail.addr
|
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1430
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+
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1287
1431
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@staticmethod
|
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1288
1432
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def _remove_redundant_jump_blocks(ail_graph):
|
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1289
1433
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def first_conditional_jump(block: ailment.Block) -> Optional[ailment.Stmt.ConditionalJump]:
|
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@@ -93,7 +93,8 @@ _ail2claripy_op_mapping = {
|
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93
93
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"Div": lambda expr, conv, _: conv(expr.operands[0], nobool=True) / conv(expr.operands[1], nobool=True),
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94
94
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"Mod": lambda expr, conv, _: conv(expr.operands[0], nobool=True) % conv(expr.operands[1], nobool=True),
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95
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"Not": lambda expr, conv, _: claripy.Not(conv(expr.operand)),
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96
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-
"Neg": lambda expr, conv, _:
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96
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+
"Neg": lambda expr, conv, _: -conv(expr.operand),
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97
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+
"BitwiseNeg": lambda expr, conv, _: ~conv(expr.operand),
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97
98
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"Xor": lambda expr, conv, _: conv(expr.operands[0], nobool=True) ^ conv(expr.operands[1], nobool=True),
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98
99
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"And": lambda expr, conv, _: conv(expr.operands[0], nobool=True) & conv(expr.operands[1], nobool=True),
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99
100
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"Or": lambda expr, conv, _: conv(expr.operands[0], nobool=True) | conv(expr.operands[1], nobool=True),
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@@ -642,7 +643,8 @@ class ConditionProcessor:
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642
643
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643
644
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_mapping = {
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644
645
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"Not": lambda cond_, tags: _unary_op_reduce("Not", cond_.args[0], tags),
|
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645
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-
"
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646
|
+
"__neg__": lambda cond_, tags: _unary_op_reduce("Not", cond_.args[0], tags),
|
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647
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+
"__invert__": lambda cond_, tags: _unary_op_reduce("BitwiseNeg", cond_.args[0], tags),
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646
648
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"And": lambda cond_, tags: _binary_op_reduce("LogicalAnd", cond_.args, tags),
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647
649
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"Or": lambda cond_, tags: _binary_op_reduce("LogicalOr", cond_.args, tags),
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648
650
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"__le__": lambda cond_, tags: _binary_op_reduce("CmpLE", cond_.args, tags, signed=True),
|
|
@@ -88,6 +88,8 @@ class EagerEvaluation(PeepholeOptimizationExprBase):
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|
88
88
|
expr.signed,
|
|
89
89
|
**expr.tags,
|
|
90
90
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)
|
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91
|
+
if isinstance(expr.operands[0], Const) and expr.operands[0].value == 0:
|
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92
|
+
return UnaryOp(expr.idx, "Neg", expr.operands[1], **expr.tags)
|
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91
93
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|
92
94
|
elif expr.op == "And":
|
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93
95
|
if isinstance(expr.operands[0], Const) and isinstance(expr.operands[1], Const):
|
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@@ -1576,6 +1576,7 @@ class CUnaryOp(CExpression):
|
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|
1576
1576
|
OP_MAP = {
|
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1577
1577
|
"Not": self._c_repr_chunks_not,
|
|
1578
1578
|
"Neg": self._c_repr_chunks_neg,
|
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1579
|
+
"BitwiseNeg": self._c_repr_chunks_bitwiseneg,
|
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1579
1580
|
"Reference": self._c_repr_chunks_reference,
|
|
1580
1581
|
"Dereference": self._c_repr_chunks_dereference,
|
|
1581
1582
|
}
|
|
@@ -1597,13 +1598,20 @@ class CUnaryOp(CExpression):
|
|
|
1597
1598
|
yield from CExpression._try_c_repr_chunks(self.operand)
|
|
1598
1599
|
yield ")", paren
|
|
1599
1600
|
|
|
1600
|
-
def
|
|
1601
|
+
def _c_repr_chunks_bitwiseneg(self):
|
|
1601
1602
|
paren = CClosingObject("(")
|
|
1602
1603
|
yield "~", self
|
|
1603
1604
|
yield "(", paren
|
|
1604
1605
|
yield from CExpression._try_c_repr_chunks(self.operand)
|
|
1605
1606
|
yield ")", paren
|
|
1606
1607
|
|
|
1608
|
+
def _c_repr_chunks_neg(self):
|
|
1609
|
+
paren = CClosingObject("(")
|
|
1610
|
+
yield "-", self
|
|
1611
|
+
yield "(", paren
|
|
1612
|
+
yield from CExpression._try_c_repr_chunks(self.operand)
|
|
1613
|
+
yield ")", paren
|
|
1614
|
+
|
|
1607
1615
|
def _c_repr_chunks_reference(self):
|
|
1608
1616
|
yield "&", self
|
|
1609
1617
|
yield from CExpression._try_c_repr_chunks(self.operand)
|
angr/analyses/disassembly.py
CHANGED
|
@@ -214,10 +214,6 @@ class Instruction(DisassemblyPiece):
|
|
|
214
214
|
assert hasattr(self.insn, "operands")
|
|
215
215
|
|
|
216
216
|
op_str = self.insn.op_str
|
|
217
|
-
# NOTE: the size of dummy_operands is not necessarily equal to
|
|
218
|
-
# operands count of capstone disasm result. If we check
|
|
219
|
-
# len(self.operands) == len(self.insn.operands)
|
|
220
|
-
# special cases in arm disassembly will mess up the code
|
|
221
217
|
dummy_operands = self.split_arm_op_string(op_str)
|
|
222
218
|
|
|
223
219
|
for operand in dummy_operands:
|
|
@@ -278,16 +274,16 @@ class Instruction(DisassemblyPiece):
|
|
|
278
274
|
|
|
279
275
|
@staticmethod
|
|
280
276
|
def split_arm_op_string(op_str: str):
|
|
281
|
-
# Split arm operand string
|
|
277
|
+
# Split arm operand string with commas outside the square brackets
|
|
282
278
|
pieces = []
|
|
283
|
-
|
|
279
|
+
in_square_brackets = False
|
|
284
280
|
cur_opr = ""
|
|
285
281
|
for c in op_str:
|
|
286
|
-
if c == "["
|
|
287
|
-
|
|
288
|
-
if c == "]"
|
|
289
|
-
|
|
290
|
-
if c == "," and
|
|
282
|
+
if c == "[":
|
|
283
|
+
in_square_brackets = True
|
|
284
|
+
if c == "]":
|
|
285
|
+
in_square_brackets = False
|
|
286
|
+
if c == "," and not in_square_brackets:
|
|
291
287
|
pieces.append(cur_opr)
|
|
292
288
|
cur_opr = ""
|
|
293
289
|
continue
|
|
@@ -256,6 +256,11 @@ class SimEngineRDAIL(
|
|
|
256
256
|
ip = Register(self.arch.ip_offset, self.arch.bytes)
|
|
257
257
|
self.state.kill_definitions(ip)
|
|
258
258
|
|
|
259
|
+
statement = self.block.statements[self.stmt_idx]
|
|
260
|
+
caller_will_handle_single_ret = True
|
|
261
|
+
if hasattr(statement, "dst") and statement.dst != stmt.ret_expr:
|
|
262
|
+
caller_will_handle_single_ret = False
|
|
263
|
+
|
|
259
264
|
data = FunctionCallData(
|
|
260
265
|
self.state.codeloc,
|
|
261
266
|
self._function_handler.make_function_codeloc(
|
|
@@ -267,7 +272,7 @@ class SimEngineRDAIL(
|
|
|
267
272
|
name=func_name,
|
|
268
273
|
args_values=[self._expr(arg) for arg in stmt.args] if stmt.args is not None else None,
|
|
269
274
|
redefine_locals=stmt.args is None and not is_expr,
|
|
270
|
-
caller_will_handle_single_ret=
|
|
275
|
+
caller_will_handle_single_ret=caller_will_handle_single_ret,
|
|
271
276
|
ret_atoms={Atom.from_ail_expr(stmt.ret_expr, self.arch)} if stmt.ret_expr is not None else None,
|
|
272
277
|
)
|
|
273
278
|
|
|
@@ -213,7 +213,10 @@ class SimEngineRDVEX(
|
|
|
213
213
|
atom = MemoryLocation(a, size)
|
|
214
214
|
tags = None
|
|
215
215
|
elif self.state.is_stack_address(a):
|
|
216
|
-
|
|
216
|
+
offset = self.state.get_stack_offset(a)
|
|
217
|
+
if offset is None:
|
|
218
|
+
continue
|
|
219
|
+
atom = MemoryLocation(SpOffset(self.arch.bits, offset), size)
|
|
217
220
|
function_address = None # we cannot get the function address in the middle of a store if a CFG
|
|
218
221
|
# does not exist. you should backpatch the function address later using
|
|
219
222
|
# the 'ins_addr' metadata entry.
|
|
@@ -269,6 +272,14 @@ class SimEngineRDVEX(
|
|
|
269
272
|
_ = self._expr(stmt.guard)
|
|
270
273
|
target = stmt.dst.value
|
|
271
274
|
self.state.mark_guard(target)
|
|
275
|
+
if self.state.analysis is not None:
|
|
276
|
+
self.state.analysis.exit_observe(
|
|
277
|
+
self.block.addr,
|
|
278
|
+
self.stmt_idx,
|
|
279
|
+
self.block,
|
|
280
|
+
self.state,
|
|
281
|
+
node_idx=self.block.block_idx if hasattr(self.block, "block_idx") else None,
|
|
282
|
+
)
|
|
272
283
|
if (
|
|
273
284
|
self.block.instruction_addrs
|
|
274
285
|
and self.ins_addr in self.block.instruction_addrs
|
|
@@ -671,12 +682,14 @@ class SimEngineRDVEX(
|
|
|
671
682
|
# we do not support division between two real multivalues
|
|
672
683
|
r = MultiValues(self.state.top(bits))
|
|
673
684
|
elif expr0_v is None and expr1_v is not None:
|
|
674
|
-
if
|
|
685
|
+
if expr1_v == 0:
|
|
686
|
+
r = MultiValues(self.state.top(bits))
|
|
687
|
+
elif expr0.count() == 1 and 0 in expr0:
|
|
675
688
|
vs = {v / expr1_v for v in expr0[0]}
|
|
676
689
|
r = MultiValues(offset_to_values={0: vs})
|
|
677
690
|
elif expr0_v is not None and expr1_v is None:
|
|
678
691
|
if expr1.count() == 1 and 0 in expr1:
|
|
679
|
-
vs = {
|
|
692
|
+
vs = {expr0_v / v for v in expr1[0] if (not v.concrete) or v.concrete_value != 0}
|
|
680
693
|
r = MultiValues(offset_to_values={0: vs})
|
|
681
694
|
else:
|
|
682
695
|
if expr0_v.concrete and expr1_v.concrete:
|
|
@@ -52,7 +52,7 @@ class FunctionCallData:
|
|
|
52
52
|
|
|
53
53
|
Function handler contract:
|
|
54
54
|
|
|
55
|
-
- If redefine_locals is unset, do not adjust any artifacts of the function call
|
|
55
|
+
- If redefine_locals is unset, do not adjust any artifacts of the function call abstraction, such as the stack
|
|
56
56
|
pointer, the caller saved registers, etc.
|
|
57
57
|
- If caller_will_handle_single_ret is set, and there is a single entry in `ret_atoms`, do not apply to the state
|
|
58
58
|
effects modifying this atom. Instead, set `ret_values` and `ret_values_deps` to the values and deps which are
|
|
@@ -137,7 +137,13 @@ class FunctionCallData:
|
|
|
137
137
|
)
|
|
138
138
|
else:
|
|
139
139
|
self.effects.append(
|
|
140
|
-
FunctionEffect(
|
|
140
|
+
FunctionEffect(
|
|
141
|
+
dest,
|
|
142
|
+
set(sources),
|
|
143
|
+
value=value,
|
|
144
|
+
apply_at_callsite=apply_at_callsite,
|
|
145
|
+
tags=tags,
|
|
146
|
+
)
|
|
141
147
|
)
|
|
142
148
|
|
|
143
149
|
|
|
@@ -333,7 +339,7 @@ class FunctionHandler:
|
|
|
333
339
|
mv, defs = state.kill_and_add_definition(
|
|
334
340
|
effect.dest,
|
|
335
341
|
value,
|
|
336
|
-
endness=
|
|
342
|
+
endness=None,
|
|
337
343
|
uses=effect.sources_defns or set(),
|
|
338
344
|
tags=effect.tags,
|
|
339
345
|
)
|
|
@@ -28,7 +28,9 @@ from .dep_graph import DepGraph
|
|
|
28
28
|
if TYPE_CHECKING:
|
|
29
29
|
from typing import Literal
|
|
30
30
|
|
|
31
|
-
ObservationPoint = Tuple[
|
|
31
|
+
ObservationPoint = Tuple[
|
|
32
|
+
Literal["insn", "node", "stmt", "exit"], Union[int, Tuple[int, int], Tuple[int, int, int]], ObservationPointType
|
|
33
|
+
]
|
|
32
34
|
|
|
33
35
|
l = logging.getLogger(name=__name__)
|
|
34
36
|
|
|
@@ -228,11 +230,18 @@ class ReachingDefinitionsAnalysis(
|
|
|
228
230
|
|
|
229
231
|
return self.observed_results[key]
|
|
230
232
|
|
|
231
|
-
def node_observe(
|
|
233
|
+
def node_observe(
|
|
234
|
+
self,
|
|
235
|
+
node_addr: int,
|
|
236
|
+
state: ReachingDefinitionsState,
|
|
237
|
+
op_type: ObservationPointType,
|
|
238
|
+
node_idx: Optional[int] = None,
|
|
239
|
+
) -> None:
|
|
232
240
|
"""
|
|
233
241
|
:param node_addr: Address of the node.
|
|
234
242
|
:param state: The analysis state.
|
|
235
|
-
:param op_type: Type of the
|
|
243
|
+
:param op_type: Type of the observation point. Must be one of the following: OP_BEFORE, OP_AFTER.
|
|
244
|
+
:param node_idx: ID of the node. Used in AIL to differentiate blocks with the same address.
|
|
236
245
|
"""
|
|
237
246
|
|
|
238
247
|
key = None
|
|
@@ -241,15 +250,21 @@ class ReachingDefinitionsAnalysis(
|
|
|
241
250
|
|
|
242
251
|
if self._observe_all:
|
|
243
252
|
observe = True
|
|
244
|
-
key: ObservationPoint = (
|
|
253
|
+
key: ObservationPoint = (
|
|
254
|
+
("node", node_addr, op_type) if node_idx is None else ("node", (node_addr, node_idx), op_type)
|
|
255
|
+
)
|
|
245
256
|
elif self._observation_points is not None:
|
|
246
|
-
key: ObservationPoint = (
|
|
257
|
+
key: ObservationPoint = (
|
|
258
|
+
("node", node_addr, op_type) if node_idx is None else ("node", (node_addr, node_idx), op_type)
|
|
259
|
+
)
|
|
247
260
|
if key in self._observation_points:
|
|
248
261
|
observe = True
|
|
249
262
|
elif self._observe_callback is not None:
|
|
250
|
-
observe = self._observe_callback("node", addr=node_addr, state=state, op_type=op_type)
|
|
263
|
+
observe = self._observe_callback("node", addr=node_addr, state=state, op_type=op_type, node_idx=node_idx)
|
|
251
264
|
if observe:
|
|
252
|
-
key: ObservationPoint = (
|
|
265
|
+
key: ObservationPoint = (
|
|
266
|
+
("node", node_addr, op_type) if node_idx is None else ("node", (node_addr, node_idx), op_type)
|
|
267
|
+
)
|
|
253
268
|
|
|
254
269
|
if observe:
|
|
255
270
|
self.observed_results[key] = state.live_definitions
|
|
@@ -351,6 +366,52 @@ class ReachingDefinitionsAnalysis(
|
|
|
351
366
|
# it's an AIL block
|
|
352
367
|
self.observed_results[key] = state.live_definitions.copy()
|
|
353
368
|
|
|
369
|
+
def exit_observe(
|
|
370
|
+
self,
|
|
371
|
+
node_addr: int,
|
|
372
|
+
exit_stmt_idx: int,
|
|
373
|
+
block: Union[Block, ailment.Block],
|
|
374
|
+
state: ReachingDefinitionsState,
|
|
375
|
+
node_idx: Optional[int] = None,
|
|
376
|
+
):
|
|
377
|
+
observe = False
|
|
378
|
+
key = None
|
|
379
|
+
|
|
380
|
+
if self._observe_all:
|
|
381
|
+
observe = True
|
|
382
|
+
key = (
|
|
383
|
+
("exit", (node_addr, exit_stmt_idx), ObservationPointType.OP_AFTER)
|
|
384
|
+
if node_idx is None
|
|
385
|
+
else ("exit", (node_addr, node_idx, exit_stmt_idx), ObservationPointType.OP_AFTER)
|
|
386
|
+
)
|
|
387
|
+
elif self._observation_points is not None:
|
|
388
|
+
key = (
|
|
389
|
+
("exit", (node_addr, exit_stmt_idx), ObservationPointType.OP_AFTER)
|
|
390
|
+
if node_idx is None
|
|
391
|
+
else ("exit", (node_addr, node_idx, exit_stmt_idx), ObservationPointType.OP_AFTER)
|
|
392
|
+
)
|
|
393
|
+
if key in self._observation_points:
|
|
394
|
+
observe = True
|
|
395
|
+
elif self._observe_callback is not None:
|
|
396
|
+
observe = self._observe_callback(
|
|
397
|
+
"exit",
|
|
398
|
+
node_addr=node_addr,
|
|
399
|
+
exit_stmt_idx=exit_stmt_idx,
|
|
400
|
+
block=block,
|
|
401
|
+
state=state,
|
|
402
|
+
)
|
|
403
|
+
if observe:
|
|
404
|
+
key = (
|
|
405
|
+
("exit", (node_addr, exit_stmt_idx), ObservationPointType.OP_AFTER)
|
|
406
|
+
if node_idx is None
|
|
407
|
+
else ("exit", (node_addr, node_idx, exit_stmt_idx), ObservationPointType.OP_AFTER)
|
|
408
|
+
)
|
|
409
|
+
|
|
410
|
+
if not observe:
|
|
411
|
+
return
|
|
412
|
+
|
|
413
|
+
self.observed_results[key] = state.live_definitions.copy()
|
|
414
|
+
|
|
354
415
|
@property
|
|
355
416
|
def subject(self):
|
|
356
417
|
return self._subject
|
|
@@ -411,7 +472,8 @@ class ReachingDefinitionsAnalysis(
|
|
|
411
472
|
l.warning("Unsupported node type %s.", node.__class__)
|
|
412
473
|
return False, state.copy(discard_tmpdefs=True)
|
|
413
474
|
|
|
414
|
-
|
|
475
|
+
state = state.copy(discard_tmpdefs=True)
|
|
476
|
+
self.node_observe(node.addr, state.copy(), OP_BEFORE)
|
|
415
477
|
|
|
416
478
|
if self.subject.type == SubjectType.Function:
|
|
417
479
|
node_parents = [
|
|
@@ -425,7 +487,6 @@ class ReachingDefinitionsAnalysis(
|
|
|
425
487
|
node_parents,
|
|
426
488
|
)
|
|
427
489
|
|
|
428
|
-
state = state.copy(discard_tmpdefs=True)
|
|
429
490
|
state = engine.process(
|
|
430
491
|
state,
|
|
431
492
|
block=block,
|
|
@@ -241,6 +241,7 @@ class VariableRecoveryFast(ForwardAnalysis, VariableRecoveryBase): # pylint:dis
|
|
|
241
241
|
track_sp=True,
|
|
242
242
|
func_args: Optional[List[SimVariable]] = None,
|
|
243
243
|
store_live_variables=False,
|
|
244
|
+
unify_variables=True,
|
|
244
245
|
):
|
|
245
246
|
if not isinstance(func, Function):
|
|
246
247
|
func = self.kb.functions[func]
|
|
@@ -268,6 +269,7 @@ class VariableRecoveryFast(ForwardAnalysis, VariableRecoveryBase): # pylint:dis
|
|
|
268
269
|
self._job_ctr = 0
|
|
269
270
|
self._track_sp = track_sp and self.project.arch.sp_offset is not None
|
|
270
271
|
self._func_args = func_args
|
|
272
|
+
self._unify_variables = unify_variables
|
|
271
273
|
|
|
272
274
|
self._ail_engine = SimEngineVRAIL(self.project, self.kb, call_info=call_info)
|
|
273
275
|
self._vex_engine = SimEngineVRVEX(self.project, self.kb, call_info=call_info)
|
|
@@ -460,6 +462,9 @@ class VariableRecoveryFast(ForwardAnalysis, VariableRecoveryBase): # pylint:dis
|
|
|
460
462
|
state.downsize_region(state.stack_region),
|
|
461
463
|
)
|
|
462
464
|
|
|
465
|
+
if self._unify_variables:
|
|
466
|
+
self.variable_manager[self.function.addr].unify_variables()
|
|
467
|
+
|
|
463
468
|
# unify type variables for global variables
|
|
464
469
|
for var, typevars in self.var_to_typevars.items():
|
|
465
470
|
if len(typevars) > 1 and isinstance(var, SimMemoryVariable) and not isinstance(var, SimStackVariable):
|
angr/calling_conventions.py
CHANGED
|
@@ -158,6 +158,12 @@ def refine_locs_with_struct_type(
|
|
|
158
158
|
for field, field_ty in arg_type.fields.items()
|
|
159
159
|
}
|
|
160
160
|
return SimStructArg(arg_type, locs)
|
|
161
|
+
if isinstance(arg_type, SimUnion):
|
|
162
|
+
# Treat a SimUnion as functionality equivalent to its longest member
|
|
163
|
+
for member in arg_type.members.values():
|
|
164
|
+
if member.size == arg_type.size:
|
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return refine_locs_with_struct_type(arch, locs, member, offset)
|
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+
|
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|
raise TypeError("I don't know how to lay out a %s" % arg_type)
|
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|
|
|
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169
|
|
|
@@ -1813,6 +1819,24 @@ class SimCCAArch64LinuxSyscall(SimCCSyscall):
|
|
|
1813
1819
|
return state.regs.x8
|
|
1814
1820
|
|
|
1815
1821
|
|
|
1822
|
+
class SimCCRISCV64LinuxSyscall(SimCCSyscall):
|
|
1823
|
+
# TODO: Make sure all the information is correct
|
|
1824
|
+
ARG_REGS = ["a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7"]
|
|
1825
|
+
FP_ARG_REGS = [] # TODO: ???
|
|
1826
|
+
RETURN_VAL = SimRegArg("a0", 8)
|
|
1827
|
+
RETURN_ADDR = SimRegArg("ip_at_syscall", 4)
|
|
1828
|
+
ARCH = archinfo.ArchRISCV64
|
|
1829
|
+
|
|
1830
|
+
@classmethod
|
|
1831
|
+
def _match(cls, arch, args, sp_delta): # pylint: disable=unused-argument
|
|
1832
|
+
# never appears anywhere except syscalls
|
|
1833
|
+
return False
|
|
1834
|
+
|
|
1835
|
+
@staticmethod
|
|
1836
|
+
def syscall_num(state):
|
|
1837
|
+
return state.regs.a0
|
|
1838
|
+
|
|
1839
|
+
|
|
1816
1840
|
class SimCCO32(SimCC):
|
|
1817
1841
|
ARG_REGS = ["a0", "a1", "a2", "a3"]
|
|
1818
1842
|
FP_ARG_REGS = [
|
|
@@ -2292,6 +2316,10 @@ SYSCALL_CC: Dict[str, Dict[str, Type[SimCCSyscall]]] = {
|
|
|
2292
2316
|
"default": SimCCS390XLinuxSyscall,
|
|
2293
2317
|
"Linux": SimCCS390XLinuxSyscall,
|
|
2294
2318
|
},
|
|
2319
|
+
"RISCV64": {
|
|
2320
|
+
"default": SimCCRISCV64LinuxSyscall,
|
|
2321
|
+
"Linux": SimCCRISCV64LinuxSyscall,
|
|
2322
|
+
},
|
|
2295
2323
|
}
|
|
2296
2324
|
|
|
2297
2325
|
|
|
@@ -495,6 +495,9 @@ class LiveDefinitions:
|
|
|
495
495
|
except SimMemoryError:
|
|
496
496
|
l.warning("Failed to store register definition %s at %d.", d, atom.reg_offset, exc_info=True)
|
|
497
497
|
elif isinstance(atom, MemoryLocation):
|
|
498
|
+
if endness is None:
|
|
499
|
+
endness = atom.endness
|
|
500
|
+
|
|
498
501
|
if isinstance(atom.addr, SpOffset):
|
|
499
502
|
if atom.addr.offset is not None:
|
|
500
503
|
stack_addr = self.stack_offset_to_stack_addr(atom.addr.offset)
|
|
@@ -120,12 +120,18 @@ class ReachingDefinitionsModel:
|
|
|
120
120
|
return self.observed_results.get(("insn", ins_addr.ins_addr, kind))
|
|
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121
|
|
|
122
122
|
def get_observation_by_node(
|
|
123
|
-
self, node_addr: Union[int, "CodeLocation"], kind: ObservationPointType
|
|
123
|
+
self, node_addr: Union[int, "CodeLocation"], kind: ObservationPointType, node_idx: Optional[int] = None
|
|
124
124
|
) -> Optional[LiveDefinitions]:
|
|
125
125
|
if isinstance(node_addr, int):
|
|
126
|
-
|
|
126
|
+
key = ("node", node_addr, kind) if node_idx is None else ("node", (node_addr, node_idx), kind)
|
|
127
|
+
return self.observed_results.get(key, None)
|
|
127
128
|
else:
|
|
128
|
-
|
|
129
|
+
key = (
|
|
130
|
+
("node", node_addr.block_addr, kind)
|
|
131
|
+
if node_idx is None
|
|
132
|
+
else ("node", (node_addr.block_addr, node_idx), kind)
|
|
133
|
+
)
|
|
134
|
+
return self.observed_results.get(key, None)
|
|
129
135
|
|
|
130
136
|
@overload
|
|
131
137
|
def get_observation_by_stmt(self, codeloc: "CodeLocation", kind: ObservationPointType) -> Optional[LiveDefinitions]:
|
|
@@ -150,3 +156,16 @@ class ReachingDefinitionsModel:
|
|
|
150
156
|
return self.observed_results.get(("stmt", (arg1.block_addr, arg1.stmt_idx), arg2), None)
|
|
151
157
|
else:
|
|
152
158
|
return self.observed_results.get(("stmt", (arg1.block_addr, arg1.stmt_idx, block_idx), arg2), None)
|
|
159
|
+
|
|
160
|
+
def get_observation_by_exit(
|
|
161
|
+
self,
|
|
162
|
+
node_addr: int,
|
|
163
|
+
stmt_idx: int,
|
|
164
|
+
src_node_idx: Optional[int] = None,
|
|
165
|
+
) -> Optional[LiveDefinitions]:
|
|
166
|
+
key = (
|
|
167
|
+
("exit", (node_addr, stmt_idx), ObservationPointType.OP_AFTER)
|
|
168
|
+
if src_node_idx is None
|
|
169
|
+
else ("exit", (node_addr, src_node_idx, stmt_idx), ObservationPointType.OP_AFTER)
|
|
170
|
+
)
|
|
171
|
+
return self.observed_results.get(key, None)
|
|
@@ -1,4 +1,4 @@
|
|
|
1
|
-
from typing import Set, List, Tuple, Dict, Union, Optional, TYPE_CHECKING
|
|
1
|
+
from typing import Set, List, Tuple, Dict, Union, Optional, Literal, TYPE_CHECKING
|
|
2
2
|
import logging
|
|
3
3
|
from collections import defaultdict
|
|
4
4
|
from itertools import count, chain
|
|
@@ -591,14 +591,15 @@ class VariableManagerInternal(Serializable):
|
|
|
591
591
|
|
|
592
592
|
return accesses
|
|
593
593
|
|
|
594
|
-
def get_variables(
|
|
594
|
+
def get_variables(
|
|
595
|
+
self, sort: Optional[Literal["stack", "reg"]] = None, collapse_same_ident=False
|
|
596
|
+
) -> List[Union[SimStackVariable, SimRegisterVariable]]:
|
|
595
597
|
"""
|
|
596
598
|
Get a list of variables.
|
|
597
599
|
|
|
598
|
-
:param
|
|
600
|
+
:param sort: Sort of the variable to get.
|
|
599
601
|
:param collapse_same_ident: Whether variables of the same identifier should be collapsed or not.
|
|
600
602
|
:return: A list of variables.
|
|
601
|
-
:rtype: list
|
|
602
603
|
"""
|
|
603
604
|
|
|
604
605
|
variables = []
|
|
@@ -615,6 +616,27 @@ class VariableManagerInternal(Serializable):
|
|
|
615
616
|
|
|
616
617
|
return variables
|
|
617
618
|
|
|
619
|
+
def get_unified_variables(
|
|
620
|
+
self, sort: Optional[Literal["stack", "reg"]] = None
|
|
621
|
+
) -> List[Union[SimStackVariable, SimRegisterVariable]]:
|
|
622
|
+
"""
|
|
623
|
+
Get a list of unified variables.
|
|
624
|
+
|
|
625
|
+
:param sort: Sort of the variable to get.
|
|
626
|
+
:return: A list of variables.
|
|
627
|
+
"""
|
|
628
|
+
|
|
629
|
+
variables = []
|
|
630
|
+
|
|
631
|
+
for var in self._unified_variables:
|
|
632
|
+
if sort == "stack" and not isinstance(var, SimStackVariable):
|
|
633
|
+
continue
|
|
634
|
+
if sort == "reg" and not isinstance(var, SimRegisterVariable):
|
|
635
|
+
continue
|
|
636
|
+
variables.append(var)
|
|
637
|
+
|
|
638
|
+
return variables
|
|
639
|
+
|
|
618
640
|
def get_global_variables(self, addr):
|
|
619
641
|
"""
|
|
620
642
|
Get global variable by the address of the variable.
|
angr/lib/angr_native.dll
CHANGED
|
Binary file
|
angr/project.py
CHANGED
|
@@ -268,8 +268,8 @@ class Project:
|
|
|
268
268
|
"""
|
|
269
269
|
Initializes self.analyses using a given preset.
|
|
270
270
|
"""
|
|
271
|
-
self.
|
|
272
|
-
self.
|
|
271
|
+
self._analyses = cast("AnalysesHubWithDefault", AnalysesHub(self))
|
|
272
|
+
self._analyses.use_plugin_preset(self._analyses_preset if self._analyses_preset is not None else "default")
|
|
273
273
|
|
|
274
274
|
def _register_object(self, obj, sim_proc_arch):
|
|
275
275
|
"""
|
angr/sim_type.py
CHANGED
|
@@ -849,7 +849,7 @@ class SimTypeFunction(SimType):
|
|
|
849
849
|
_fields = ("args", "returnty")
|
|
850
850
|
base = False
|
|
851
851
|
|
|
852
|
-
def __init__(self, args, returnty, label=None, arg_names=None, variadic=False):
|
|
852
|
+
def __init__(self, args: List[SimType], returnty: Optional[SimType], label=None, arg_names=None, variadic=False):
|
|
853
853
|
"""
|
|
854
854
|
:param label: The type label
|
|
855
855
|
:param args: A tuple of types representing the arguments to the function
|
|
@@ -857,7 +857,7 @@ class SimTypeFunction(SimType):
|
|
|
857
857
|
:param variadic: Whether the function accepts varargs
|
|
858
858
|
"""
|
|
859
859
|
super().__init__(label=label)
|
|
860
|
-
self.args = args
|
|
860
|
+
self.args: List[SimType] = args
|
|
861
861
|
self.returnty: Optional[SimType] = returnty
|
|
862
862
|
self.arg_names = arg_names if arg_names else ()
|
|
863
863
|
self.variadic = variadic
|
|
@@ -21,11 +21,16 @@ class MultiValueMergerMixin(MemoryMixin):
|
|
|
21
21
|
# try to merge it in the traditional way
|
|
22
22
|
if len(values_set) > self._element_limit:
|
|
23
23
|
# strip annotations from each value and see how many raw values there are in total
|
|
24
|
-
|
|
24
|
+
# We have to use cache_key to determine uniqueness here, because if __hash__ collides,
|
|
25
|
+
# python implicitly calls __eq__ to determine if the two objects are actually the same
|
|
26
|
+
# and that just results in a new AST for a BV. Python then tries to convert that AST to a bool
|
|
27
|
+
# which fails with the safeguard in claripy.ast.bool.Bool.__bool__.
|
|
28
|
+
stripped_values_set = {v._apply_to_annotations(lambda alist: None).cache_key for v in values_set}
|
|
25
29
|
if len(stripped_values_set) > 1:
|
|
26
30
|
ret_val = self._top_func(merged_size * self.state.arch.byte_width)
|
|
27
31
|
else:
|
|
28
|
-
|
|
32
|
+
# Get the AST back from the cache_key
|
|
33
|
+
ret_val = next(iter(stripped_values_set)).ast
|
|
29
34
|
# migrate annotations
|
|
30
35
|
annotations = []
|
|
31
36
|
for v in values_set:
|
|
@@ -1,6 +1,6 @@
|
|
|
1
1
|
Metadata-Version: 2.1
|
|
2
2
|
Name: angr
|
|
3
|
-
Version: 9.2.
|
|
3
|
+
Version: 9.2.63
|
|
4
4
|
Summary: A multi-architecture binary analysis toolkit, with the ability to perform dynamic symbolic execution and various static analyses on binaries
|
|
5
5
|
Home-page: https://github.com/angr/angr
|
|
6
6
|
License: BSD-2-Clause
|
|
@@ -16,27 +16,27 @@ Description-Content-Type: text/markdown
|
|
|
16
16
|
License-File: LICENSE
|
|
17
17
|
Requires-Dist: CppHeaderParser
|
|
18
18
|
Requires-Dist: GitPython
|
|
19
|
-
Requires-Dist: ailment
|
|
20
|
-
Requires-Dist: archinfo
|
|
19
|
+
Requires-Dist: ailment ==9.2.63
|
|
20
|
+
Requires-Dist: archinfo ==9.2.63
|
|
21
21
|
Requires-Dist: cachetools
|
|
22
|
-
Requires-Dist: capstone
|
|
23
|
-
Requires-Dist: cffi
|
|
24
|
-
Requires-Dist: claripy
|
|
25
|
-
Requires-Dist: cle
|
|
22
|
+
Requires-Dist: capstone !=5.0.0rc2,>=3.0.5rc2
|
|
23
|
+
Requires-Dist: cffi >=1.14.0
|
|
24
|
+
Requires-Dist: claripy ==9.2.63
|
|
25
|
+
Requires-Dist: cle ==9.2.63
|
|
26
26
|
Requires-Dist: dpkt
|
|
27
27
|
Requires-Dist: itanium-demangler
|
|
28
28
|
Requires-Dist: mulpyplexer
|
|
29
29
|
Requires-Dist: nampa
|
|
30
|
-
Requires-Dist: networkx
|
|
31
|
-
Requires-Dist: protobuf
|
|
30
|
+
Requires-Dist: networkx !=2.8.1,>=2.0
|
|
31
|
+
Requires-Dist: protobuf >=3.19.0
|
|
32
32
|
Requires-Dist: psutil
|
|
33
|
-
Requires-Dist: pycparser
|
|
34
|
-
Requires-Dist: pyvex
|
|
35
|
-
Requires-Dist: rich
|
|
33
|
+
Requires-Dist: pycparser >=2.18
|
|
34
|
+
Requires-Dist: pyvex ==9.2.63
|
|
35
|
+
Requires-Dist: rich >=13.1.0
|
|
36
36
|
Requires-Dist: rpyc
|
|
37
37
|
Requires-Dist: sortedcontainers
|
|
38
38
|
Requires-Dist: sympy
|
|
39
|
-
Requires-Dist: unicorn
|
|
39
|
+
Requires-Dist: unicorn ==2.0.1.post1
|
|
40
40
|
Requires-Dist: colorama ; platform_system == "Windows"
|
|
41
41
|
Provides-Extra: angrdb
|
|
42
42
|
Requires-Dist: sqlalchemy ; extra == 'angrdb'
|
|
@@ -46,10 +46,10 @@ Requires-Dist: myst-parser ; extra == 'docs'
|
|
|
46
46
|
Requires-Dist: sphinx ; extra == 'docs'
|
|
47
47
|
Requires-Dist: sphinx-autodoc-typehints ; extra == 'docs'
|
|
48
48
|
Provides-Extra: pcode
|
|
49
|
-
Requires-Dist: pypcode
|
|
49
|
+
Requires-Dist: pypcode >=1.1 ; extra == 'pcode'
|
|
50
50
|
Provides-Extra: testing
|
|
51
51
|
Requires-Dist: keystone-engine ; extra == 'testing'
|
|
52
|
-
Requires-Dist: pypcode
|
|
52
|
+
Requires-Dist: pypcode >=1.1 ; extra == 'testing'
|
|
53
53
|
Requires-Dist: pytest ; extra == 'testing'
|
|
54
54
|
Requires-Dist: pytest-split ; extra == 'testing'
|
|
55
55
|
Requires-Dist: pytest-xdist ; extra == 'testing'
|
|
@@ -1,16 +1,16 @@
|
|
|
1
|
-
angr/__init__.py,sha256=
|
|
1
|
+
angr/__init__.py,sha256=_fNDmP91K4YZntgKbJuPKWxw112jMpQv-ysV3f9GMbw,2800
|
|
2
2
|
angr/annocfg.py,sha256=dK5JAdN4Ig_jgxTBZeZXwk3kAS4-IQUvE6T02GBZTDQ,10818
|
|
3
3
|
angr/blade.py,sha256=1f5cqw1w6mKtYszN2-5QMxaoP_bbqpIaVlE7Vpf8yjc,15161
|
|
4
4
|
angr/block.py,sha256=RXro1XdUTztfPL2r62m2YA1XTNe7bP0lkBUDYzz_FyE,14371
|
|
5
5
|
angr/callable.py,sha256=p98KlOijfkcGnUx1C-lNt-R5ncYF4md6oxC7aBKc8Ws,5513
|
|
6
|
-
angr/calling_conventions.py,sha256=
|
|
6
|
+
angr/calling_conventions.py,sha256=RiJO0pz7EImjZA4wJzQ4M_Ez8d26QTs-d2RXbFLzgQo,88701
|
|
7
7
|
angr/code_location.py,sha256=_EXS1uAEkoOKBoxtvxAOluLsbKkcjyAWnCnviHdBK7w,4720
|
|
8
8
|
angr/codenode.py,sha256=uF9iObkowp87iBZimrpNl-JSr7vQanhL94dWESnw1Ks,3759
|
|
9
9
|
angr/errors.py,sha256=uYZEr2kYrKeylLIkrfNOtLy68sA0R3OJ9CD77Ucg4NQ,8191
|
|
10
10
|
angr/factory.py,sha256=rHwRkt47EeJW2tsL9aIq_NjantEJwCsqdd34mg2HmVk,17141
|
|
11
11
|
angr/graph_utils.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
|
|
12
12
|
angr/keyed_region.py,sha256=vgaJ7sUkUeGfXY-dRcRl40qNtB-JDbIWaL7xRdcDGdQ,17363
|
|
13
|
-
angr/project.py,sha256=
|
|
13
|
+
angr/project.py,sha256=2Wi1VBGb94EQl8DeGi5cAE1_joF17O-kt5R0FFhHkw8,37023
|
|
14
14
|
angr/py.typed,sha256=SQuN8RfR7Scqb98Wf7vJndZle4ROvVL1kp6l5M7EpmY,7
|
|
15
15
|
angr/serializable.py,sha256=6cljvzAqFwsLqFu9ouCno7hMpgstha5-8C7RyWNCRXc,1502
|
|
16
16
|
angr/service.py,sha256=9R50bFaCf6zjxybiEIVIkODSVCsE2VcTul_KjjsjaGU,1102
|
|
@@ -19,7 +19,7 @@ angr/sim_options.py,sha256=OuT01xS_F3ifBD9MAfZmNCnfjtTg0HulZlrKcs1LNSY,18057
|
|
|
19
19
|
angr/sim_procedure.py,sha256=uM4poyQYkVy_zlJqgyM_CbtVcDRbSsyZ1Z50i4yFwNw,25822
|
|
20
20
|
angr/sim_state.py,sha256=BxL2lvo4bWmen5PKs1TegedOgnM8EFBgDJ-rsZf-XkE,37869
|
|
21
21
|
angr/sim_state_options.py,sha256=lfP7ygngjGe0AGV5rkE24tvBazJBZG-RTdrKj4rL9XE,12530
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+
angr-9.2.63.dist-info/top_level.txt,sha256=dKw0KWTbwLXytFvv15oAAG4sUs3ey47tt6DorJG9-hw,5
|
|
1189
|
+
angr-9.2.63.dist-info/RECORD,,
|
|
File without changes
|
|
File without changes
|