angr 9.2.163__cp310-abi3-manylinux2014_x86_64.whl → 9.2.164__cp310-abi3-manylinux2014_x86_64.whl

angr/analyses/decompiler/region_identifier.py

@@ -99,7 +99,7 @@ class RegionIdentifier(Analysis):
 
     def _analyze(self):
         # make a copy of the graph
-        graph = networkx.DiGraph(self._graph)
+        graph = self._pick_one_connected_component(self._graph, as_copy=True)
 
         # preprocess: make it a super graph
         self._make_supergraph(graph)
@@ -113,6 +113,27 @@ class RegionIdentifier(Analysis):
         # make regions into block address lists
         self.regions_by_block_addrs = self._make_regions_by_block_addrs()
 
+    def _pick_one_connected_component(self, digraph: networkx.DiGraph, as_copy: bool = False) -> networkx.DiGraph:
+        g = networkx.Graph(digraph)
+        components = list(networkx.connected_components(g))
+        if len(components) <= 1:
+            return networkx.DiGraph(digraph) if as_copy else digraph
+
+        the_component = None
+        largest_component = None
+        for component in components:
+            if largest_component is None or len(component) > len(largest_component):
+                largest_component = component
+            if any((block.addr, block.idx) == self.entry_node_addr for block in component):
+                the_component = component
+                break
+
+        if the_component is None:
+            the_component = largest_component
+
+        assert the_component is not None
+        return digraph.subgraph(the_component).to_directed()
+
     @staticmethod
     def _compute_node_order(graph: networkx.DiGraph) -> dict[Any, tuple[int, int]]:
         sorted_nodes = GraphUtils.quasi_topological_sort_nodes(graph)

angr/analyses/decompiler/structuring/phoenix.py

@@ -13,7 +13,7 @@ from angr.ailment.block import Block
 from angr.ailment.statement import Statement, ConditionalJump, Jump, Label, Return
 from angr.ailment.expression import Const, UnaryOp, MultiStatementExpression, BinaryOp
 
-from angr.utils.graph import GraphUtils
+from angr.utils.graph import GraphUtils, Dominators, compute_dominance_frontier
 from angr.utils.ail import is_phi_assignment, is_head_controlled_loop_block
 from angr.knowledge_plugins.cfg import IndirectJump, IndirectJumpType
 from angr.utils.constants import SWITCH_MISSING_DEFAULT_NODE_ADDR
@@ -669,7 +669,7 @@ class PhoenixStructurer(StructurerBase):
         continue_node = loop_head
 
         is_while, result_while = self._refine_cyclic_is_while_loop(graph, fullgraph, loop_head, head_succs)
-        is_dowhile, result_dowhile = self._refine_cyclic_is_dowhile_loop(graph, fullgraph, loop_head, head_succs)
+        is_dowhile, result_dowhile = self._refine_cyclic_is_dowhile_loop(graph, fullgraph, loop_head)
 
         continue_edges: list[tuple[BaseNode, BaseNode]] = []
         outgoing_edges: list = []
@@ -702,22 +702,12 @@ class PhoenixStructurer(StructurerBase):
 
         if loop_type is None:
             # natural loop. select *any* exit edge to determine the successor
-            # well actually, to maintain determinism, we select the successor with the highest address
-            successor_candidates = set()
-            for node in networkx.descendants(graph, loop_head):
-                for succ in fullgraph.successors(node):
-                    if succ not in graph:
-                        successor_candidates.add(succ)
-                    if loop_head is succ:
-                        continue_edges.append((node, succ))
-            if successor_candidates:
-                successor_candidates = sorted(successor_candidates, key=lambda x: x.addr)
-                successor = successor_candidates[0]
-                # virtualize all other edges
-                for succ in successor_candidates:
-                    for pred in fullgraph.predecessors(succ):
-                        if pred in graph:
-                            outgoing_edges.append((pred, succ))
+            is_natural, result_natural = self._refine_cyclic_make_natural_loop(graph, fullgraph, loop_head)
+            if not is_natural:
+                # cannot refine this loop
+                return False
+            assert result_natural is not None
+            continue_edges, outgoing_edges, successor = result_natural
 
         if outgoing_edges:
             # if there is a single successor, we convert all out-going edges into breaks;
@@ -963,8 +953,8 @@ class PhoenixStructurer(StructurerBase):
                 return True, (continue_edges, outgoing_edges, loop_head, successor)
         return False, None
 
-    def _refine_cyclic_is_dowhile_loop(  # pylint:disable=unused-argument
-        self, graph, fullgraph, loop_head, head_succs
+    def _refine_cyclic_is_dowhile_loop(
+        self, graph, fullgraph, loop_head
     ) -> tuple[bool, tuple[list, list, BaseNode, BaseNode] | None]:
         # check if there is an out-going edge from the loop tail
         head_preds = list(fullgraph.predecessors(loop_head))
@@ -996,6 +986,64 @@ class PhoenixStructurer(StructurerBase):
                     return True, (continue_edges, outgoing_edges, continue_node, successor)
         return False, None
 
+    def _refine_cyclic_make_natural_loop(
+        self, graph, fullgraph, loop_head
+    ) -> tuple[bool, tuple[list, list, Any] | None]:
+        continue_edges = []
+        outgoing_edges = []
+
+        # find dominance frontier
+        doms = Dominators(fullgraph, self._region.head)
+        dom_frontiers = compute_dominance_frontier(fullgraph, doms.dom)
+
+        if loop_head not in dom_frontiers:
+            return False, None
+        dom_frontier = dom_frontiers[loop_head]
+
+        # now this is a little complex
+        dom_frontier = {node for node in dom_frontier if node is not loop_head}
+        if len(dom_frontier) == 0:
+            # the dominance frontier is empty (the loop head dominates all nodes in the full graph). however, this does
+            # not mean that the loop head must dominate all the nodes, because we only have a limited view of the full
+            # graph (e.g., some predecessors of the successor may not be in this full graph). as such, successors are
+            # the ones that are in the fullgraph but not in the graph.
+            successor_candidates = set()
+            for node in networkx.descendants(graph, loop_head):
+                for succ in fullgraph.successors(node):
+                    if succ not in graph:
+                        successor_candidates.add(succ)
+                    if loop_head is succ:
+                        continue_edges.append((node, succ))
+
+        else:
+            # this loop has a single successor
+            successor_candidates = dom_frontier
+            # traverse the loop body to find all continue edges
+            tmp_graph = networkx.DiGraph(graph)
+            tmp_graph.remove_nodes_from(successor_candidates)
+            for node in networkx.descendants(tmp_graph, loop_head):
+                if tmp_graph.has_edge(node, loop_head):
+                    continue_edges.append((node, loop_head))
+
+        if len(successor_candidates) == 0:
+            successor = None
+        else:
+            # one or multiple successors; try to pick a successor in graph, and prioritize the one with the lowest
+            # address
+            successor_candidates_in_graph = {nn for nn in successor_candidates if nn in graph}
+            if successor_candidates_in_graph:
+                # pick the one with the lowest address
+                successor = next(iter(sorted(successor_candidates_in_graph, key=lambda x: x.addr)))
+            else:
+                successor = next(iter(sorted(successor_candidates, key=lambda x: x.addr)))
+            # mark all edges as outgoing edges so they will be virtualized if they don't lead to the successor
+            for node in successor_candidates:
+                for pred in fullgraph.predecessors(node):
+                    if networkx.has_path(doms.dom, loop_head, pred):
+                        outgoing_edges.append((pred, node))
+
+        return True, (continue_edges, outgoing_edges, successor)
+
     def _analyze_acyclic(self) -> bool:
         # match against known schemas
         l.debug("Matching acyclic schemas for region %r.", self._region)
@@ -1219,6 +1267,10 @@ class PhoenixStructurer(StructurerBase):
         node_a = next(iter(nn for nn in graph.nodes if nn.addr == target), None)
         if node_a is None:
             return False
+        if node_a is self._region.head:
+            # avoid structuring if node_a is the region head; this means the current node is a duplicated switch-case
+            # head (instead of the original one), which is not something we want to structure
+            return False
 
         # the default case
         node_b_addr = next(iter(t for t in successor_addrs if t != target), None)

angr/analyses/decompiler/structuring/recursive_structurer.py

@@ -3,8 +3,6 @@ import itertools
 from typing import TYPE_CHECKING
 import logging
 
-import networkx
-
 from angr.analyses import Analysis, register_analysis
 from angr.analyses.decompiler.condition_processor import ConditionProcessor
 from angr.analyses.decompiler.graph_region import GraphRegion
@@ -12,6 +10,7 @@ from angr.analyses.decompiler.jumptable_entry_condition_rewriter import JumpTabl
 from angr.analyses.decompiler.empty_node_remover import EmptyNodeRemover
 from angr.analyses.decompiler.jump_target_collector import JumpTargetCollector
 from angr.analyses.decompiler.redundant_label_remover import RedundantLabelRemover
+from angr.utils.graph import GraphUtils
 from .structurer_nodes import BaseNode
 from .structurer_base import StructurerBase
 from .dream import DreamStructurer
@@ -61,7 +60,7 @@ class RecursiveStructurer(Analysis):
             current_region = stack[-1]
 
             has_region = False
-            for node in networkx.dfs_postorder_nodes(current_region.graph, current_region.head):
+            for node in GraphUtils.dfs_postorder_nodes_deterministic(current_region.graph, current_region.head):
                 subnodes = []
                 if type(node) is GraphRegion:
                     if node.cyclic:
@@ -177,7 +176,7 @@ class RecursiveStructurer(Analysis):
         for node in region.graph.nodes:
             if not isinstance(node, BaseNode):
                 continue
-            if node.addr == self.function.addr:
+            if self.function is not None and node.addr == self.function.addr:
                 return node
             if min_node is None or (min_node.addr is not None and node.addr is not None and min_node.addr < node.addr):
                 min_node = node

angr/analyses/decompiler/structuring/structurer_nodes.py

@@ -392,6 +392,9 @@ class IncompleteSwitchCaseNode(BaseNode):
         self.head = head
         self.cases: list = cases
 
+    def __repr__(self):
+        return f"<IncompleteSwitchCase {self.addr:#x} with {len(self.cases)} cases>"
+
 
 #
 # The following classes are custom AIL statements (not nodes, unfortunately)

angr/analyses/decompiler/utils.py

@@ -158,10 +158,14 @@ def switch_extract_cmp_bounds(
         return None
 
     # TODO: Add more operations
-    if isinstance(last_stmt.condition, ailment.Expr.BinaryOp) and last_stmt.condition.op == "CmpLE":
+    if isinstance(last_stmt.condition, ailment.Expr.BinaryOp) and last_stmt.condition.op in {"CmpLE", "CmpLT"}:
         if not isinstance(last_stmt.condition.operands[1], ailment.Expr.Const):
             return None
-        cmp_ub = last_stmt.condition.operands[1].value
+        cmp_ub = (
+            last_stmt.condition.operands[1].value
+            if last_stmt.condition.op == "CmpLE"
+            else last_stmt.condition.operands[1].value - 1
+        )
         cmp_lb = 0
         cmp = last_stmt.condition.operands[0]
         if (
@@ -250,6 +254,10 @@ def switch_extract_bitwiseand_jumptable_info(last_stmt: ailment.Stmt.Jump) -> tu
              size=4, endness=Iend_LE) + 0x4530e4<32>))
     )
 
+    Another example:
+
+    Load(addr=(((vvar_9{reg 36} & 0x3<32>) * 0x4<32>) + 0x42cd28<32>), size=4, endness=Iend_LE)
+
     :param last_stmt:   The last statement of the switch-case header node.
     :return:            A tuple of (index expression, lower bound, upper bound), or None
     """
@@ -269,16 +277,20 @@ def switch_extract_bitwiseand_jumptable_info(last_stmt: ailment.Stmt.Jump) -> tu
             continue
         if isinstance(target, ailment.Expr.BinaryOp) and target.op == "Add":
             if isinstance(target.operands[0], ailment.Expr.Const) and isinstance(target.operands[1], ailment.Expr.Load):
-                jump_addr_offset = target.operands[0]
+                jump_addr_offset = target.operands[0].value
                 jumptable_load_addr = target.operands[1].addr
                 break
             if isinstance(target.operands[1], ailment.Expr.Const) and isinstance(target.operands[0], ailment.Expr.Load):
-                jump_addr_offset = target.operands[1]
+                jump_addr_offset = target.operands[1].value
                 jumptable_load_addr = target.operands[0].addr
                 break
             return None
         if isinstance(target, ailment.Expr.Const):
             return None
+        if isinstance(target, ailment.Expr.Load):
+            jumptable_load_addr = target.addr
+            jump_addr_offset = 0
+            break
         break
 
     if jump_addr_offset is None or jumptable_load_addr is None:
@@ -655,7 +667,7 @@ def _flatten_structured_node(packed_node: SequenceNode | MultiNode) -> list[ailm
 
 def _find_node_in_graph(node: ailment.Block, graph: networkx.DiGraph) -> ailment.Block | None:
     for bb in graph:
-        if bb.addr == node.addr and bb.idx == node.idx:
+        if isinstance(bb, ailment.Block) and bb.addr == node.addr and bb.idx == node.idx:
             return bb
     return None
 

angr/analyses/s_reaching_definitions/s_rda_view.py

@@ -37,7 +37,8 @@ class RegVVarPredicate:
         if cc is not None:
             reg_list = cc.CALLER_SAVED_REGS
             if isinstance(cc.RETURN_VAL, SimRegArg):
-                reg_list.append(cc.RETURN_VAL.reg_name)
+                # do not update reg_list directly, otherwise you may update cc.CALLER_SAVED_REGS!
+                reg_list = [*reg_list, cc.RETURN_VAL.reg_name]
             return {self.arch.registers[reg_name][0] for reg_name in reg_list}
         log.warning("Cannot determine registers that are clobbered by call statement %r.", stmt)
         return set()

angr/analyses/typehoon/typeconsts.py

@@ -245,7 +245,9 @@ class Struct(TypeConstant):
         if not self.fields:
             return 0
         max_field_off = max(self.fields.keys())
-        return max_field_off + self.fields[max_field_off].size
+        return max_field_off + (
+            self.fields[max_field_off].size if not isinstance(self.fields[max_field_off], BottomType) else 1
+        )
 
     @memoize
     def __repr__(self, memo=None):

angr/blade.py

@@ -40,6 +40,7 @@ class Blade:
         cross_insn_opt=False,
         max_predecessors: int = 10,
         include_imarks: bool = True,
+        control_dependence: bool = True,
     ):
         """
         :param graph:                   A graph representing the control flow graph. Note that it does not take
@@ -56,6 +57,8 @@ class Blade:
         :param stop_at_calls:           Limit slicing within a single function. Do not proceed when encounters a call
                                         edge.
         :param include_imarks:          Should IMarks (instruction boundaries) be included in the slice.
+        :param control_dependence:      Whether to consider control dependencies. If True, the temps controlling
+                                        conditional exits will be added to the tainting set.
         :return: None
         """
 
@@ -70,6 +73,7 @@ class Blade:
         self._cross_insn_opt = cross_insn_opt
         self._max_predecessors = max_predecessors
         self._include_imarks = include_imarks
+        self._control_dependence = control_dependence
 
         self._slice = networkx.DiGraph()
 
@@ -347,7 +351,7 @@ class Blade:
         except (SimTranslationError, BadJumpkindNotification):
             return
 
-        if exit_stmt_idx is None or exit_stmt_idx == DEFAULT_STATEMENT:
+        if self._control_dependence and (exit_stmt_idx is None or exit_stmt_idx == DEFAULT_STATEMENT):
             # Initialize the temps set with whatever in the `next` attribute of this irsb
             next_expr = self._get_irsb(run).next
             if type(next_expr) is pyvex.IRExpr.RdTmp:
@@ -357,20 +361,21 @@ class Blade:
         self._inslice_callback(DEFAULT_STATEMENT, None, {"irsb_addr": irsb_addr, "prev": prev})
         prev = irsb_addr, DEFAULT_STATEMENT
 
-        # if there are conditional exits, we *always* add them into the slice (so if they should not be taken, we do not
-        # lose the condition)
-        for stmt_idx_, s_ in enumerate(self._get_irsb(run).statements):
-            if type(s_) is not pyvex.IRStmt.Exit:
-                continue
-            if s_.jumpkind != "Ijk_Boring":
-                continue
-
-            if type(s_.guard) is pyvex.IRExpr.RdTmp:
-                temps.add(s_.guard.tmp)
-
-            # Put it in our slice
-            self._inslice_callback(stmt_idx_, s_, {"irsb_addr": irsb_addr, "prev": prev})
-            prev = (irsb_addr, stmt_idx_)
+        if self._control_dependence:
+            # if there are conditional exits, we *always* add them into the slice (so if they should not be taken, we
+            # do not lose the condition)
+            for stmt_idx_, s_ in enumerate(self._get_irsb(run).statements):
+                if type(s_) is not pyvex.IRStmt.Exit:
+                    continue
+                if s_.jumpkind != "Ijk_Boring":
+                    continue
+
+                if type(s_.guard) is pyvex.IRExpr.RdTmp:
+                    temps.add(s_.guard.tmp)
+
+                # Put it in our slice
+                self._inslice_callback(stmt_idx_, s_, {"irsb_addr": irsb_addr, "prev": prev})
+                prev = (irsb_addr, stmt_idx_)
 
         infodict = {"irsb_addr": irsb_addr, "prev": prev, "has_statement": False}
 

angr/engines/icicle.py

@@ -123,7 +123,7 @@ class IcicleEngine(ConcreteEngine):
         if proj is None:
             raise ValueError("IcicleEngine requires a project to be set")
 
-        emu = Icicle(icicle_arch, PROCESSORS_DIR)
+        emu = Icicle(icicle_arch, PROCESSORS_DIR, True)
 
         copied_registers = set()
 
@@ -194,7 +194,8 @@ class IcicleEngine(ConcreteEngine):
             addr = page_num * state.memory.page_size
             state.memory.store(addr, emu.mem_read(addr, state.memory.page_size))
 
-        # 3. Set history.jumpkind
+        # 3. Set history
+        # 3.1 history.jumpkind
         exc = emu.exception_code
         if status == VmExit.UnhandledException:
             if exc in (
@@ -216,6 +217,10 @@ class IcicleEngine(ConcreteEngine):
         else:
             state.history.jumpkind = "Ijk_Boring"
 
+        # 3.2 history.recent_bbl_addrs
+        # Skip the last block, because it will be added by Successors
+        state.history.recent_bbl_addrs.extend([b[0] for b in emu.recent_blocks][:-1])
+
         # 4. Set history.recent_instruction_count
         state.history.recent_instruction_count = emu.cpu_icount - translation_data.initial_cpu_icount
 

angr/knowledge_plugins/propagations/propagation_model.py

@@ -19,6 +19,7 @@ class PropagationModel(Serializable):
         "_initial_state",
         "block_initial_reg_values",
         "equivalence",
+        "function_block_count",
         "graph_visitor",
         "input_states",
         "key",
@@ -37,6 +38,7 @@ class PropagationModel(Serializable):
         equivalence: set | None = None,
         function: Function | None = None,
         input_states: dict | None = None,
+        function_block_count: int | None = None,
     ):
         self.key = prop_key
         self.node_iterations = node_iterations if node_iterations is not None else defaultdict(int)
@@ -49,6 +51,11 @@ class PropagationModel(Serializable):
         self.graph_visitor = None
         self._initial_state = None
         self._function = function
+        self.function_block_count = (
+            function_block_count
+            if function_block_count is not None
+            else len(function.block_addrs_set) if function is not None else None
+        )
 
     def downsize(self):
         self.node_iterations = None

angr/sim_type.py

@@ -1789,6 +1789,7 @@ class SimCppClass(SimStruct):
         vtable_ptrs=None,
         pack: bool = False,
         align=None,
+        size: int | None = None,
     ):
         super().__init__(members or {}, name=name, pack=pack, align=align)
         self.unique_name = unique_name
@@ -1797,6 +1798,10 @@ class SimCppClass(SimStruct):
         # this should also be added to the fields once we know the offsets of the members of this object
         self.vtable_ptrs = [] if vtable_ptrs is None else vtable_ptrs
 
+        # we can force the size (in bits) of a class because sometimes the class can be opaque and we don't know its
+        # layout
+        self._size = size
+
     @property
     def members(self):
         return self.fields
@@ -1805,6 +1810,12 @@ class SimCppClass(SimStruct):
     def members(self, value):
         self.fields = value
 
+    @property
+    def size(self):
+        if self._size is not None:
+            return self._size
+        return super().size
+
     def __repr__(self):
         return f"class {self.name}" if not self.name.startswith("class") else self.name
 
@@ -1848,6 +1859,7 @@ class SimCppClass(SimStruct):
             vtable_ptrs=self.vtable_ptrs,
             pack=self._pack,
             align=self._align,
+            size=self._size,
         )
         out._arch = arch
         self._arch_memo[arch.name] = out
@@ -1877,6 +1889,7 @@ class SimCppClass(SimStruct):
             align=self._align,
             function_members=self.function_members,
             vtable_ptrs=self.vtable_ptrs,
+            size=self._size,
         )
 
 
@@ -2029,6 +2042,8 @@ BASIC_TYPES: dict[str, SimType] = {
     "long long int": SimTypeLongLong(True),
     "signed long long int": SimTypeLongLong(True),
     "unsigned long long int": SimTypeLongLong(False),
+    "__int32": SimTypeInt(True),
+    "__int64": SimTypeLongLong(True),
     "__int128": SimTypeNum(128, True),
     "unsigned __int128": SimTypeNum(128, False),
     "__int256": SimTypeNum(256, True),
@@ -3563,7 +3578,7 @@ def _cpp_decl_to_type(
             t = ALL_TYPES[lbl]
         elif opaque_classes is True:
             # create a class without knowing the internal members
-            t = SimCppClass(unique_name=lbl, name=lbl, members={})
+            t = SimCppClass(unique_name=lbl, name=lbl, members={}, size=32)
         else:
             raise TypeError(f'Unknown type "{lbl}"')
 

angr/utils/constants.py

@@ -6,4 +6,4 @@ MAX_POINTSTO_BITS = -1330 * 8
 
 
 def is_alignment_mask(n):
-    return n in {0xFFFFFFFFFFFFFFE0, 0xFFFFFFFFFFFFFFF0, 0xFFFFFFF0, 0xFFFFFFFC, 0xFFFFFFF8}
+    return n in {0xFFFFFFFFFFFFFFE0, 0xFFFFFFFFFFFFFFF0, 0xFFFFFFE0, 0xFFFFFFF0, 0xFFFFFFFC, 0xFFFFFFF8}

angr/utils/graph.py

@@ -76,7 +76,7 @@ def to_acyclic_graph(
     for src, dst in graph.edges():
         src_order = node_order[src]
         dst_order = node_order[dst]
-        if src_order > dst_order:
+        if src_order >= dst_order:
             # this is a back edge, we need to remove it
             edges_to_remove.append((src, dst))
 

angr/utils/vex.py

@@ -0,0 +1,11 @@
+from __future__ import annotations
+
+from pyvex import IRSB
+from pyvex.stmt import WrTmp
+
+
+def get_tmp_def_stmt(vex_block: IRSB, tmp_idx: int) -> int | None:
+    for i, stmt in enumerate(vex_block.statements):
+        if isinstance(stmt, WrTmp) and stmt.tmp == tmp_idx:
+            return i
+    return None

{angr-9.2.163.dist-info → angr-9.2.164.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: angr
-Version: 9.2.163
+Version: 9.2.164
 Summary: A multi-architecture binary analysis toolkit, with the ability to perform dynamic symbolic execution and various static analyses on binaries
 License: BSD-2-Clause
 Project-URL: Homepage, https://angr.io/
@@ -16,12 +16,12 @@ Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: cxxheaderparser
 Requires-Dist: GitPython
-Requires-Dist: archinfo==9.2.163
+Requires-Dist: archinfo==9.2.164
 Requires-Dist: cachetools
 Requires-Dist: capstone==5.0.3
 Requires-Dist: cffi>=1.14.0
-Requires-Dist: claripy==9.2.163
-Requires-Dist: cle==9.2.163
+Requires-Dist: claripy==9.2.164
+Requires-Dist: cle==9.2.164
 Requires-Dist: mulpyplexer
 Requires-Dist: networkx!=2.8.1,>=2.0
 Requires-Dist: protobuf>=5.28.2
@@ -30,7 +30,7 @@ Requires-Dist: pycparser>=2.18
 Requires-Dist: pydemumble
 Requires-Dist: pyformlang
 Requires-Dist: pypcode<4.0,>=3.2.1
-Requires-Dist: pyvex==9.2.163
+Requires-Dist: pyvex==9.2.164
 Requires-Dist: rich>=13.1.0
 Requires-Dist: sortedcontainers
 Requires-Dist: sympy