angr 9.2.150__py3-none-macosx_10_9_x86_64.whl → 9.2.152__py3-none-macosx_10_9_x86_64.whl

angr/__init__.py

@@ -2,7 +2,7 @@
 # pylint: disable=wrong-import-position
 from __future__ import annotations
 
-__version__ = "9.2.150"
+__version__ = "9.2.152"
 
 if bytes is str:
     raise Exception(

angr/analyses/calling_convention/calling_convention.py

@@ -21,6 +21,7 @@ from angr.calling_conventions import (
     default_cc,
     SimCCMicrosoftThiscall,
 )
+from angr.errors import SimTranslationError
 from angr.sim_type import (
     SimTypeCppFunction,
     SimTypeInt,
@@ -585,16 +586,23 @@ class CallingConventionAnalysis(Analysis):
             # include its successor.
 
             # Re-lift the target block
-            dst_bb = self.project.factory.block(dst.addr, func.get_block_size(dst.addr), opt_level=1)
+            dst_block_size = func.get_block_size(dst.addr)
+            if dst_block_size is not None and dst_block_size > 0:
+                dst_bb = self.project.factory.block(dst.addr, dst_block_size, opt_level=1)
+                try:
+                    vex_block = dst_bb.vex
+                except SimTranslationError:
+                    # failed to lift the block
+                    continue
 
-            # If there is only one 'IMark' statement in vex --> the target block contains only direct jump
-            if (
-                len(dst_bb.vex.statements) == 1
-                and dst_bb.vex.statements[0].tag == "Ist_IMark"
-                and func.graph.out_degree(dst) == 1
-            ):
-                for _, jmp_dst, jmp_data in func_graph.out_edges(dst, data=True):
-                    subgraph.add_edge(dst, jmp_dst, **jmp_data)
+                # If there is only one 'IMark' statement in vex --> the target block contains only direct jump
+                if (
+                    len(vex_block.statements) == 1
+                    and vex_block.statements[0].tag == "Ist_IMark"
+                    and func.graph.out_degree(dst) == 1
+                ):
+                    for _, jmp_dst, jmp_data in func_graph.out_edges(dst, data=True):
+                        subgraph.add_edge(dst, jmp_dst, **jmp_data)
 
         return subgraph
 

angr/analyses/decompiler/ccall_rewriters/amd64_ccalls.py

@@ -412,6 +412,45 @@ class AMD64CCallRewriter(CCallRewriterBase):
                     )
                     return Expr.Convert(None, r.bits, ccall.bits, False, r, **ccall.tags)
 
+                elif (
+                    cond_v == AMD64_CondTypes["CondNS"]
+                    and op_v
+                    in {
+                        AMD64_OpTypes["G_CC_OP_LOGICB"],
+                        AMD64_OpTypes["G_CC_OP_LOGICW"],
+                        AMD64_OpTypes["G_CC_OP_LOGICL"],
+                        AMD64_OpTypes["G_CC_OP_LOGICQ"],
+                    }
+                    and isinstance(dep_2, Expr.Const)
+                    and dep_2.value == 0
+                ):
+                    # dep_1 >= 0
+                    dep_1 = self._fix_size(
+                        dep_1,
+                        op_v,
+                        AMD64_OpTypes["G_CC_OP_LOGICB"],
+                        AMD64_OpTypes["G_CC_OP_LOGICW"],
+                        AMD64_OpTypes["G_CC_OP_LOGICL"],
+                        ccall.tags,
+                    )
+                    dep_2 = self._fix_size(
+                        dep_2,
+                        op_v,
+                        AMD64_OpTypes["G_CC_OP_LOGICB"],
+                        AMD64_OpTypes["G_CC_OP_LOGICW"],
+                        AMD64_OpTypes["G_CC_OP_LOGICL"],
+                        ccall.tags,
+                    )
+
+                    r = Expr.BinaryOp(
+                        ccall.idx,
+                        "CmpGE",
+                        (dep_1, dep_2),
+                        True,
+                        **ccall.tags,
+                    )
+                    return Expr.Convert(None, r.bits, ccall.bits, False, r, **ccall.tags)
+
         elif ccall.callee == "amd64g_calculate_rflags_c":
             # calculate the carry flag
             op = ccall.operands[0]

angr/analyses/decompiler/clinic.py

@@ -483,6 +483,9 @@ class Clinic(Analysis):
         arg_vvars = self._create_function_argument_vvars(arg_list)
         func_args = {arg_vvar for arg_vvar, _ in arg_vvars.values()}
 
+        # duplicate orphaned conditional jump blocks
+        ail_graph = self._duplicate_orphaned_cond_jumps(ail_graph)
+
         # Transform the graph into partial SSA form
         self._update_progress(35.0, text="Transforming to partial-SSA form")
         ail_graph = self._transform_to_ssa_level0(ail_graph, func_args)
@@ -1892,6 +1895,19 @@ class Clinic(Analysis):
                 self._link_variables_on_expr(variable_manager, global_variables, block, stmt_idx, stmt, stmt.dst)
                 self._link_variables_on_expr(variable_manager, global_variables, block, stmt_idx, stmt, stmt.src)
 
+            elif stmt_type is ailment.Stmt.CAS:
+                for expr in [
+                    stmt.addr,
+                    stmt.data_lo,
+                    stmt.data_hi,
+                    stmt.expd_lo,
+                    stmt.expd_hi,
+                    stmt.old_lo,
+                    stmt.old_hi,
+                ]:
+                    if expr is not None:
+                        self._link_variables_on_expr(variable_manager, global_variables, block, stmt_idx, stmt, expr)
+
             elif stmt_type is ailment.Stmt.ConditionalJump:
                 self._link_variables_on_expr(variable_manager, global_variables, block, stmt_idx, stmt, stmt.condition)
 
@@ -2123,6 +2139,45 @@ class Clinic(Analysis):
 
         return graph
 
+    @staticmethod
+    def _duplicate_orphaned_cond_jumps(ail_graph) -> networkx.DiGraph:
+        """
+        Find conditional jumps that are orphaned (e.g., being the only instruction of the block). If these blocks have
+        multiple predecessors, duplicate them to all predecessors. This is a workaround for cases where these
+        conditional jumps rely on comparisons in more than one predecessor and we cannot resolve ccalls into
+        comparisons.
+
+        This pass runs before any SSA transformations.
+
+        # 140017162     jz      short 1400171e1
+        """
+
+        for block in list(ail_graph):
+            if len(block.statements) > 1 and block.statements[0].ins_addr == block.statements[-1].ins_addr:
+                preds = list(ail_graph.predecessors(block))
+                if len(preds) > 1 and block not in preds:
+                    has_ccall = any(
+                        isinstance(stmt, ailment.Stmt.Assignment)
+                        and isinstance(stmt.src, ailment.Expr.VEXCCallExpression)
+                        for stmt in block.statements
+                    )
+                    if has_ccall:
+                        # duplicate this block to its predecessors!
+                        preds = sorted(preds, key=lambda x: x.addr)
+                        succs = sorted(ail_graph.successors(block), key=lambda x: x.addr)
+                        # FIXME: We should track block IDs globally and ensure block IDs do not collide
+                        block_idx_start = block.idx + 1 if block.idx is not None else 1
+                        for pred in preds[1:]:
+                            ail_graph.remove_edge(pred, block)
+                            new_block = block.copy()
+                            new_block.idx = block_idx_start
+                            block_idx_start += 1
+                            ail_graph.add_edge(pred, new_block)
+                            for succ in succs:
+                                ail_graph.add_edge(new_block, succ if succ is not block else new_block)
+
+        return ail_graph
+
     def _rewrite_ite_expressions(self, ail_graph):
         cfg = self._cfg
         for block in list(ail_graph):
@@ -2130,11 +2185,16 @@ class Clinic(Analysis):
                 continue
 
             ite_ins_addrs = []
+            cas_ins_addrs = set()
             for stmt in block.statements:
-                if (
+                if isinstance(stmt, ailment.Stmt.CAS):
+                    # we do not rewrite ITE statements that are caused by CAS statements
+                    cas_ins_addrs.add(stmt.ins_addr)
+                elif (
                     isinstance(stmt, ailment.Stmt.Assignment)
                     and isinstance(stmt.src, ailment.Expr.ITE)
                     and stmt.ins_addr not in ite_ins_addrs
+                    and stmt.ins_addr not in cas_ins_addrs
                 ):
                     ite_ins_addrs.append(stmt.ins_addr)
 
@@ -2998,6 +3058,12 @@ class Clinic(Analysis):
                             and last_stmt.addr.offset < 0
                             and isinstance(last_stmt.data, ailment.Expr.Const)
                             and last_stmt.data.value == succ.addr
+                        ) or (
+                            isinstance(last_stmt, ailment.Stmt.Assignment)
+                            and last_stmt.dst.was_stack
+                            and last_stmt.dst.stack_offset < 0
+                            and isinstance(last_stmt.src, ailment.Expr.Const)
+                            and last_stmt.src.value == succ.addr
                         ):
                             # remove the statement that pushes the return address
                             node.statements = node.statements[:-1]
@@ -3031,6 +3097,12 @@ class Clinic(Analysis):
                             and last_stmt.addr.offset < 0
                             and isinstance(last_stmt.data, ailment.Expr.Const)
                             and last_stmt.data.value == succ.addr
+                        ) or (
+                            isinstance(last_stmt, ailment.Stmt.Assignment)
+                            and last_stmt.dst.was_stack
+                            and last_stmt.dst.stack_offset < 0
+                            and isinstance(last_stmt.src, ailment.Expr.Const)
+                            and last_stmt.src.value == succ.addr
                         ):
                             # remove the statement that pushes the return address
                             node.statements = node.statements[:-1]

angr/analyses/decompiler/dephication/rewriting_engine.py

@@ -1,4 +1,4 @@
-# pylint:disable=unused-argument,no-self-use
+# pylint:disable=unused-argument,no-self-use,too-many-boolean-expressions
 from __future__ import annotations
 import logging
 
@@ -8,12 +8,14 @@ from ailment.statement import (
     Assignment,
     Store,
     Call,
+    CAS,
     Return,
     ConditionalJump,
     DirtyStatement,
     WeakAssignment,
 )
 from ailment.expression import (
+    Atom,
     Expression,
     VirtualVariable,
     Load,
@@ -121,6 +123,40 @@ class SimEngineDephiRewriting(SimEngineNostmtAIL[None, Expression | None, Statem
             )
         return None
 
+    def _handle_stmt_CAS(self, stmt: CAS) -> CAS | None:
+        new_addr = self._expr(stmt.addr)
+        new_data_lo = self._expr(stmt.data_lo)
+        new_data_hi = self._expr(stmt.data_hi) if stmt.data_hi is not None else None
+        new_expd_lo = self._expr(stmt.expd_lo)
+        new_expd_hi = self._expr(stmt.expd_hi) if stmt.expd_hi is not None else None
+        new_old_lo = self._expr(stmt.old_lo)
+        new_old_hi = self._expr(stmt.old_hi) if stmt.old_hi is not None else None
+        assert new_old_lo is None or isinstance(new_old_lo, Atom)
+        assert new_old_hi is None or isinstance(new_old_hi, Atom)
+
+        if (
+            new_addr is not None
+            or new_old_lo is not None
+            or new_old_hi is not None
+            or new_data_lo is not None
+            or new_data_hi is not None
+            or new_expd_lo is not None
+            or new_expd_hi is not None
+        ):
+            return CAS(
+                stmt.idx,
+                stmt.addr if new_addr is None else new_addr,
+                stmt.data_lo if new_data_lo is None else new_data_lo,
+                stmt.data_hi if new_data_hi is None else new_data_hi,
+                stmt.expd_lo if new_expd_lo is None else new_expd_lo,
+                stmt.expd_hi if new_expd_hi is None else new_expd_hi,
+                stmt.old_lo if new_old_lo is None else new_old_lo,
+                stmt.old_hi if new_old_hi is None else new_old_hi,
+                stmt.endness,
+                **stmt.tags,
+            )
+        return None
+
     def _handle_stmt_Store(self, stmt):
         new_addr = self._expr(stmt.addr)
         new_data = self._expr(stmt.data)
@@ -179,6 +215,7 @@ class SimEngineDephiRewriting(SimEngineNostmtAIL[None, Expression | None, Statem
         dirty = self._expr(stmt.dirty)
         if dirty is None or dirty is stmt.dirty:
             return None
+        assert isinstance(dirty, DirtyExpression)
         return DirtyStatement(stmt.idx, dirty, **stmt.tags)
 
     def _handle_expr_Load(self, expr):

angr/analyses/decompiler/optimization_passes/condition_constprop.py

@@ -107,6 +107,12 @@ class ConditionConstantPropagation(OptimizationPass):
                 cconds_by_src[src] = []
             cconds_by_src[src].append(ccond)
 
+        # eliminate sources with more than one in-edges; this is because the condition may not hold on all in-edges!
+        for src in list(cconds_by_src):
+            block = self._get_block(src[0], idx=src[1])
+            if block is not None and block in self._graph and self._graph.in_degree[block] > 1:
+                del cconds_by_src[src]
+
         # eliminate conflicting conditions
         for src in list(cconds_by_src):
             cconds = cconds_by_src[src]

angr/analyses/decompiler/optimization_passes/engine_base.py

@@ -86,6 +86,11 @@ class SimplifierAILEngine(
 
         return stmt
 
+    def _handle_stmt_CAS(self, stmt: ailment.statement.CAS) -> ailment.statement.CAS:
+        # we assume that we never have to deal with CAS statements at this point; they should have been rewritten to
+        # intrinsics
+        return stmt
+
     def _handle_stmt_Store(self, stmt):
         addr = self._expr(stmt.addr)
         data = self._expr(stmt.data)

angr/analyses/decompiler/peephole_optimizations/__init__.py

@@ -8,6 +8,7 @@ from .a_sub_a_div_const_mul_const import ASubADivConstMulConst
 from .a_sub_a_shr_const_shr_const import ASubAShrConstShrConst
 from .arm_cmpf import ARMCmpF
 from .bswap import Bswap
+from .cas_intrinsics import CASIntrinsics
 from .coalesce_same_cascading_ifs import CoalesceSameCascadingIfs
 from .constant_derefs import ConstantDereferences
 from .const_mull_a_shift import ConstMullAShift
@@ -64,6 +65,7 @@ ALL_PEEPHOLE_OPTS: list[type[PeepholeOptimizationExprBase]] = [
     ASubAShrConstShrConst,
     ARMCmpF,
     Bswap,
+    CASIntrinsics,
     CoalesceSameCascadingIfs,
     ConstantDereferences,
     ConstMullAShift,

angr/analyses/decompiler/peephole_optimizations/cas_intrinsics.py

@@ -0,0 +1,115 @@
+# pylint:disable=arguments-differ,too-many-boolean-expressions
+from __future__ import annotations
+
+from ailment.expression import BinaryOp, Load
+from ailment.statement import CAS, ConditionalJump, Statement, Assignment, Call
+
+from .base import PeepholeOptimizationMultiStmtBase
+
+
+_INTRINSICS_NAMES = {
+    "xchg": {"Win32": "InterlockedExchange", "Linux": "atomic_exchange"},
+    "cmpxchg": {"Win32": "InterlockedCompareExchange", "Linux": "atomic_compare_exchange"},
+}
+
+
+class CASIntrinsics(PeepholeOptimizationMultiStmtBase):
+    """
+    Rewrite lock-prefixed instructions (or rather, their VEX/AIL forms) into intrinsic calls.
+
+    Case 1.
+
+                 mov eax, r12d
+    0x140014b57: xchg eax, [0x14000365f8]
+
+    LABEL_0x140014b57:
+    CAS(0x1400365f8<64>, Conv(64->32, vvar_365{reg 112}), Load(addr=0x1400365f8<64>, size=4, endness=Iend_LE),
+        vvar_27756)
+    if (CasCmpNE(vvar_27756, g_1400365f8))
+        goto LABEL_0x140014b57;
+
+    => vvar_27756 = _InterlockedExchange(0x1400365f8, vvar_365{reg 112})
+
+
+    Case 2.
+
+    lock cmpxchg cs:g_WarbirdSecureFunctionsLock, r14d
+
+    CAS(0x1400365f8<64>, 0x1<32>, 0x0<32>, vvar_27751)
+
+    => var_27751 = _InterlockedCompareExchange(0x1400365f8, 0x1<32>, 0x0<32>)
+    """
+
+    __slots__ = ()
+
+    NAME = "Rewrite compare-and-swap instructions into intrinsics."
+    stmt_classes = ((CAS, ConditionalJump), (CAS, Statement))
+
+    def optimize(self, stmts: list[Statement], stmt_idx: int | None = None, block=None, **kwargs):
+        assert len(stmts) == 2
+        cas_stmt = stmts[0]
+        next_stmt = stmts[1]
+        assert isinstance(cas_stmt, CAS)
+
+        # TODO: We ignored endianness. Are there cases where the endianness is different from the host's?
+
+        if (
+            isinstance(next_stmt, ConditionalJump)
+            and isinstance(next_stmt.condition, BinaryOp)
+            and next_stmt.condition.op == "CasCmpNE"
+            and next_stmt.ins_addr == cas_stmt.ins_addr
+        ):
+            addr = cas_stmt.addr
+            if (
+                isinstance(cas_stmt.expd_lo, Load)
+                and cas_stmt.expd_lo.addr.likes(addr)
+                and isinstance(next_stmt.condition.operands[1], Load)
+                and next_stmt.condition.operands[1].addr.likes(addr)
+                and cas_stmt.old_lo.likes(next_stmt.condition.operands[0])
+                and cas_stmt.old_hi is None
+            ):
+                # TODO: Support cases where cas_stmt.old_hi is not None
+                # Case 1
+                call_expr = Call(
+                    cas_stmt.idx,
+                    self._get_instrincs_name("xchg"),
+                    args=[addr, cas_stmt.data_lo],
+                    bits=cas_stmt.bits,
+                    ins_addr=cas_stmt.ins_addr,
+                )
+                stmt = Assignment(cas_stmt.idx, cas_stmt.old_lo, call_expr, **cas_stmt.tags)
+                return [stmt]
+
+        if next_stmt.ins_addr <= cas_stmt.ins_addr:
+            # avoid matching against statements prematurely
+            return None
+
+        if cas_stmt.old_hi is None:
+            # TODO: Support cases where cas_stmt.old_hi is not None
+            call_expr = Call(
+                cas_stmt.idx,
+                self._get_instrincs_name("cmpxchg"),
+                args=[
+                    cas_stmt.addr,
+                    cas_stmt.data_lo,
+                    cas_stmt.expd_lo,
+                ],
+                bits=cas_stmt.bits,
+                ins_addr=cas_stmt.ins_addr,
+            )
+            stmt = Assignment(cas_stmt.idx, cas_stmt.old_lo, call_expr, **cas_stmt.tags)
+            return [stmt, next_stmt]
+
+        return None
+
+    def _get_instrincs_name(self, mnemonic: str) -> str:
+        if mnemonic in _INTRINSICS_NAMES:
+            os = (
+                self.project.simos.name
+                if self.project is not None and self.project.simos is not None and self.project.simos.name is not None
+                else "Linux"
+            )
+            if os not in _INTRINSICS_NAMES[mnemonic]:
+                os = "Linux"
+            return _INTRINSICS_NAMES[mnemonic][os]
+        return mnemonic

angr/analyses/decompiler/ssailification/rewriting_engine.py

@@ -1,4 +1,4 @@
-# pylint:disable=no-self-use,unused-argument
+# pylint:disable=no-self-use,unused-argument,too-many-boolean-expressions
 from __future__ import annotations
 from typing import Literal
 import logging
@@ -9,6 +9,7 @@ from ailment.manager import Manager
 from ailment.statement import (
     Statement,
     Assignment,
+    CAS,
     Store,
     Call,
     Return,
@@ -18,6 +19,7 @@ from ailment.statement import (
     WeakAssignment,
 )
 from ailment.expression import (
+    Atom,
     Expression,
     Register,
     VirtualVariable,
@@ -204,6 +206,40 @@ class SimEngineSSARewriting(
             )
         return None
 
+    def _handle_stmt_CAS(self, stmt: CAS) -> CAS | None:
+        new_addr = self._expr(stmt.addr)
+        new_data_lo = self._expr(stmt.data_lo)
+        new_data_hi = self._expr(stmt.data_hi) if stmt.data_hi is not None else None
+        new_expd_lo = self._expr(stmt.expd_lo)
+        new_expd_hi = self._expr(stmt.expd_hi) if stmt.expd_hi is not None else None
+        new_old_lo = self._expr(stmt.old_lo)
+        new_old_hi = self._expr(stmt.old_hi) if stmt.old_hi is not None else None
+        assert new_old_lo is None or isinstance(new_old_lo, Atom)
+        assert new_old_hi is None or isinstance(new_old_hi, Atom)
+
+        if (
+            new_addr is not None
+            or new_old_lo is not None
+            or new_old_hi is not None
+            or new_data_lo is not None
+            or new_data_hi is not None
+            or new_expd_lo is not None
+            or new_expd_hi is not None
+        ):
+            return CAS(
+                stmt.idx,
+                stmt.addr if new_addr is None else new_addr,
+                stmt.data_lo if new_data_lo is None else new_data_lo,
+                stmt.data_hi if new_data_hi is None else new_data_hi,
+                stmt.expd_lo if new_expd_lo is None else new_expd_lo,
+                stmt.expd_hi if new_expd_hi is None else new_expd_hi,
+                stmt.old_lo if new_old_lo is None else new_old_lo,
+                stmt.old_hi if new_old_hi is None else new_old_hi,
+                stmt.endness,
+                **stmt.tags,
+            )
+        return None
+
     def _handle_stmt_Store(self, stmt: Store) -> Store | Assignment | tuple[Assignment, ...] | None:
         new_data = self._expr(stmt.data)
         if stmt.guard is None:

angr/analyses/decompiler/ssailification/traversal_engine.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 from collections import OrderedDict
 
-from ailment.statement import Call, Store, ConditionalJump
+from ailment.statement import Call, Store, ConditionalJump, CAS
 from ailment.expression import Register, BinaryOp, StackBaseOffset, ITE, VEXCCallExpression, Tmp, DirtyExpression, Load
 
 from angr.engines.light import SimEngineLightAIL
@@ -64,6 +64,15 @@ class SimEngineSSATraversal(SimEngineLightAIL[TraversalState, None, None, None])
         self._expr(stmt.src)
         self._expr(stmt.dst)
 
+    def _handle_stmt_CAS(self, stmt: CAS):
+        self._expr(stmt.addr)
+        self._expr(stmt.data_lo)
+        if stmt.data_hi is not None:
+            self._expr(stmt.data_hi)
+        self._expr(stmt.expd_lo)
+        if stmt.expd_hi is not None:
+            self._expr(stmt.expd_hi)
+
     def _handle_stmt_Store(self, stmt: Store):
         self._expr(stmt.addr)
         self._expr(stmt.data)

angr/analyses/reaching_definitions/engine_ail.py

@@ -143,6 +143,26 @@ class SimEngineRDAIL(
         else:
             l.warning("Unsupported type of Assignment dst %s.", type(dst).__name__)
 
+    def _handle_stmt_CAS(self, stmt: ailment.statement.CAS):
+        addr = self._expr(stmt.addr)
+        old_lo = stmt.old_lo
+        old_hi = stmt.old_hi
+
+        self._expr(stmt.data_lo)
+        if stmt.data_hi is not None:
+            self._expr(stmt.data_hi)
+        self._expr(stmt.expd_lo)
+        if stmt.expd_hi is not None:
+            self._expr(stmt.expd_hi)
+
+        if isinstance(old_lo, ailment.Tmp):
+            self.state.kill_and_add_definition(Tmp(old_lo.tmp_idx, old_lo.size), addr)
+            self.tmps[old_lo.tmp_idx] = self._top(old_lo.size)
+
+        if isinstance(old_hi, ailment.Tmp):
+            self.state.kill_and_add_definition(Tmp(old_hi.tmp_idx, old_hi.size), addr)
+            self.tmps[old_hi.tmp_idx] = self._top(old_hi.size)
+
     def _handle_stmt_Store(self, stmt: ailment.Stmt.Store) -> None:
         data = self._expr(stmt.data)
         addr = self._expr_bv(stmt.addr)

angr/analyses/s_propagator.py

@@ -511,5 +511,33 @@ class SPropagatorAnalysis(Analysis):
         }
         return (block_1.addr, block_1.idx) in stmt_0_targets
 
+    @staticmethod
+    def vvar_dep_graph(blocks, vvar_def_locs, vvar_use_locs) -> networkx.DiGraph:
+        g = networkx.DiGraph()
+
+        for var_id in vvar_def_locs:
+            # where is it used?
+            for _, use_loc in vvar_use_locs[var_id]:
+                if isinstance(use_loc, ExternalCodeLocation):
+                    g.add_edge(var_id, "ExternalCodeLocation")
+                    continue
+                assert use_loc.block_addr is not None
+                assert use_loc.stmt_idx is not None
+                block = blocks[(use_loc.block_addr, use_loc.block_idx)]
+                stmt = block.statements[use_loc.stmt_idx]
+                if isinstance(stmt, Assignment):
+                    if isinstance(stmt.dst, VirtualVariable):
+                        g.add_edge(var_id, stmt.dst.varid)
+                    else:
+                        g.add_edge(var_id, f"Assignment@{stmt.ins_addr:#x}")
+                elif isinstance(stmt, Store):
+                    # store to memory
+                    g.add_edge(var_id, f"Store@{stmt.ins_addr:#x}")
+                else:
+                    # other statements
+                    g.add_edge(var_id, f"{stmt.__class__.__name__}@{stmt.ins_addr:#x}")
+
+        return g
+
 
 register_analysis(SPropagatorAnalysis, "SPropagator")

angr/analyses/stack_pointer_tracker.py

@@ -791,7 +791,8 @@ class StackPointerTracker(Analysis, ForwardAnalysis):
                                     sp_adjusted = True
                                     sp_v = state.regs[self.project.arch.sp_offset]
                                     sp_v -= Constant(stmt.data.con.value)
-                                    state.put(self.project.arch.sp_offset, sp_v, force=True)
+                                    state.put(self.project.arch.sp_offset, sp_v, force=True)  # sp -= OFFSET
+                                    state.put(stmt.offset, Constant(0), force=True)  # rax = 0
                                     break
 
                 callee_cleanups = [

angr/analyses/variable_recovery/engine_ail.py

@@ -115,6 +115,15 @@ class SimEngineVRAIL(
             tc = typevars.Subtype(src.typevar, dst.typevar)
             self.state.add_type_constraint(tc)
 
+    def _handle_stmt_CAS(self, stmt) -> None:
+        self._expr(stmt.addr)
+        self._expr(stmt.data_lo)
+        if stmt.data_hi is not None:
+            self._expr(stmt.data_hi)
+        self._expr(stmt.expd_lo)
+        if stmt.expd_hi is not None:
+            self._expr(stmt.expd_hi)
+
     def _handle_stmt_Store(self, stmt: ailment.Stmt.Store):
         addr_r = self._expr_bv(stmt.addr)
         data = self._expr(stmt.data)

angr/engines/light/engine.py

@@ -533,6 +533,7 @@ class SimEngineLightAIL(
     def __init__(self, *args, **kwargs):
         self._stmt_handlers: dict[str, Callable[[Any], StmtDataType]] = {
             "Assignment": self._handle_stmt_Assignment,
+            "CAS": self._handle_stmt_CAS,
             "WeakAssignment": self._handle_stmt_WeakAssignment,
             "Store": self._handle_stmt_Store,
             "Jump": self._handle_stmt_Jump,
@@ -698,6 +699,9 @@ class SimEngineLightAIL(
     @abstractmethod
     def _handle_stmt_Assignment(self, stmt: ailment.statement.Assignment) -> StmtDataType: ...
 
+    @abstractmethod
+    def _handle_stmt_CAS(self, stmt: ailment.statement.CAS) -> StmtDataType: ...
+
     @abstractmethod
     def _handle_stmt_WeakAssignment(self, stmt: ailment.statement.WeakAssignment) -> StmtDataType: ...
 
@@ -1013,6 +1017,9 @@ class SimEngineNostmtAIL(
     def _handle_stmt_WeakAssignment(self, stmt) -> StmtDataType | None:
         pass
 
+    def _handle_stmt_CAS(self, stmt) -> StmtDataType | None:
+        pass
+
     def _handle_stmt_Store(self, stmt) -> StmtDataType | None:
         pass
 

angr/storage/memory_mixins/clouseau_mixin.py

@@ -68,6 +68,7 @@ class InspectMixinHigh(MemoryMixin):
         if not inspect or not self.state.supports_inspect:
             return super().load(addr, size=size, condition=condition, endness=endness, inspect=inspect, **kwargs)
 
+        r = None
         if self.category == "reg":
             self.state._inspect(
                 "reg_read",
@@ -76,7 +77,9 @@ class InspectMixinHigh(MemoryMixin):
                 reg_read_length=size,
                 reg_read_condition=condition,
                 reg_read_endness=endness,
+                reg_read_expr=None,
             )
+            r = self.state._inspect_getattr("reg_read_expr", None)
             addr = self.state._inspect_getattr("reg_read_offset", addr)
             size = self.state._inspect_getattr("reg_read_length", size)
             condition = self.state._inspect_getattr("reg_read_condition", condition)
@@ -89,13 +92,16 @@ class InspectMixinHigh(MemoryMixin):
                 mem_read_length=size,
                 mem_read_condition=condition,
                 mem_read_endness=endness,
+                mem_read_expr=None,
             )
+            r = self.state._inspect_getattr("mem_read_expr", None)
             addr = self.state._inspect_getattr("mem_read_address", addr)
             size = self.state._inspect_getattr("mem_read_length", size)
             condition = self.state._inspect_getattr("mem_read_condition", condition)
             endness = self.state._inspect_getattr("mem_read_endness", endness)
 
-        r = super().load(addr, size=size, condition=condition, endness=endness, inspect=inspect, **kwargs)
+        if r is None:
+            r = super().load(addr, size=size, condition=condition, endness=endness, inspect=inspect, **kwargs)
 
         if self.category == "mem":
             self.state._inspect(

angr/utils/graph.py

@@ -734,13 +734,18 @@ class GraphUtils:
 
         # find all strongly connected components in the graph
         sccs = [scc for scc in networkx.strongly_connected_components(graph) if len(scc) > 1]
+        comp_indices = {}
+        for i, scc in enumerate(sccs):
+            for node in scc:
+                if node not in comp_indices:
+                    comp_indices[node] = i
 
         # collapse all strongly connected components
         for src, dst in sorted(graph.edges(), key=GraphUtils._sort_edge):
-            scc_index = GraphUtils._components_index_node(sccs, src)
+            scc_index = comp_indices.get(src)
             if scc_index is not None:
                 src = SCCPlaceholder(scc_index)
-            scc_index = GraphUtils._components_index_node(sccs, dst)
+            scc_index = comp_indices.get(dst)
             if scc_index is not None:
                 dst = SCCPlaceholder(scc_index)
 
@@ -781,13 +786,6 @@ class GraphUtils:
             return ordered_nodes
         return [n for n in ordered_nodes if n in set(nodes)]
 
-    @staticmethod
-    def _components_index_node(components, node):
-        for i, comp in enumerate(components):
-            if node in comp:
-                return i
-        return None
-
     @staticmethod
     def _append_scc(
         graph: networkx.DiGraph,
@@ -810,9 +808,9 @@ class GraphUtils:
 
         if loop_head_candidates is not None:
             # find the first node that appears in loop_heads
-            loop_head_candidates = set(loop_head_candidates)
+            loop_head_candidates_set = set(loop_head_candidates)
             for n in scc:
-                if n in loop_head_candidates:
+                if n in loop_head_candidates_set:
                     loop_head = n
                     break
 
@@ -844,7 +842,7 @@ class GraphUtils:
             # pick the first one
             loop_head = sorted(scc, key=GraphUtils._sort_node)[0]
 
-        subgraph: networkx.DiGraph = graph.subgraph(scc).copy()
+        subgraph: networkx.DiGraph = graph.subgraph(scc).copy()  # type: ignore
         for src, _ in list(subgraph.in_edges(loop_head)):
             subgraph.remove_edge(src, loop_head)
 

angr/utils/ssa/__init__.py

@@ -8,7 +8,7 @@ import networkx
 import archinfo
 from ailment import Expression, Block
 from ailment.expression import VirtualVariable, Const, Phi, Tmp, Load, Register, StackBaseOffset, DirtyExpression, ITE
-from ailment.statement import Statement, Assignment, Call, Store
+from ailment.statement import Statement, Assignment, Call, Store, CAS
 from ailment.block_walker import AILBlockWalkerBase
 
 from angr.knowledge_plugins.key_definitions import atoms
@@ -126,6 +126,11 @@ def get_tmp_deflocs(blocks) -> dict[CodeLocation, dict[atoms.Tmp, int]]:
         for stmt_idx, stmt in enumerate(block.statements):
             if isinstance(stmt, Assignment) and isinstance(stmt.dst, Tmp):
                 tmp_to_loc[codeloc][atoms.Tmp(stmt.dst.tmp_idx, stmt.dst.bits)] = stmt_idx
+            if isinstance(stmt, CAS):
+                if isinstance(stmt.old_lo, Tmp):
+                    tmp_to_loc[codeloc][atoms.Tmp(stmt.old_lo.tmp_idx, stmt.old_lo.bits)] = stmt_idx
+                if stmt.old_hi is not None and isinstance(stmt.old_hi, Tmp):
+                    tmp_to_loc[codeloc][atoms.Tmp(stmt.old_hi.tmp_idx, stmt.old_hi.bits)] = stmt_idx
 
     return tmp_to_loc
 

{angr-9.2.150.dist-info → angr-9.2.152.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: angr
-Version: 9.2.150
+Version: 9.2.152
 Summary: A multi-architecture binary analysis toolkit, with the ability to perform dynamic symbolic execution and various static analyses on binaries
 License: BSD-2-Clause
 Project-URL: Homepage, https://angr.io/
@@ -17,13 +17,13 @@ Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: cxxheaderparser
 Requires-Dist: GitPython
-Requires-Dist: ailment==9.2.150
-Requires-Dist: archinfo==9.2.150
+Requires-Dist: ailment==9.2.152
+Requires-Dist: archinfo==9.2.152
 Requires-Dist: cachetools
 Requires-Dist: capstone==5.0.3
 Requires-Dist: cffi>=1.14.0
-Requires-Dist: claripy==9.2.150
-Requires-Dist: cle==9.2.150
+Requires-Dist: claripy==9.2.152
+Requires-Dist: cle==9.2.152
 Requires-Dist: mulpyplexer
 Requires-Dist: networkx!=2.8.1,>=2.0
 Requires-Dist: protobuf>=5.28.2
@@ -31,7 +31,7 @@ Requires-Dist: psutil
 Requires-Dist: pycparser>=2.18
 Requires-Dist: pydemumble
 Requires-Dist: pyformlang
-Requires-Dist: pyvex==9.2.150
+Requires-Dist: pyvex==9.2.152
 Requires-Dist: rich>=13.1.0
 Requires-Dist: sortedcontainers
 Requires-Dist: sympy

{angr-9.2.150.dist-info → angr-9.2.152.dist-info}/RECORD

@@ -1,4 +1,4 @@
-angr/__init__.py,sha256=DwSePTIbe8xdMgBvvZlfejFZYiB6mXcJjYv_z_rrli0,9153
+angr/__init__.py,sha256=I7kOb1_OagvgZ0ckx5c3aCv2LU7e2Xm4vSrXEYT4tQE,9153
 angr/__main__.py,sha256=AK9V6uPZ58UuTKmmiH_Kgn5pG9AvjnmJCPOku69A-WU,4993
 angr/annocfg.py,sha256=0NIvcuCskwz45hbBzigUTAuCrYutjDMwEXtMJf0y0S0,10742
 angr/blade.py,sha256=NhesOPloKJC1DQJRv_HBT18X7oNxK16JwAfNz2Lc1o0,15384
@@ -53,10 +53,10 @@ angr/analyses/pathfinder.py,sha256=_prNqmRUSuSt2ZCP8qbvNN7pw7mtM8pWr9IL0AO6XL8,1
 angr/analyses/proximity_graph.py,sha256=-g7pNpbP2HQhKW3w1Eff23K8vAsgWWYoe3wVxRh3Lhk,16066
 angr/analyses/reassembler.py,sha256=UXrDQNJtn4RUurpbIyMVpQ3AZ0VGVQZatoGHziEHvU0,98357
 angr/analyses/s_liveness.py,sha256=K4soSrcQE9pIn7Yf2Lb3LZEu1ymuQVpWzOqLKunFDGQ,7974
-angr/analyses/s_propagator.py,sha256=ChFdiT4wCN0p5mY0UsFGopH3ZH0zM5V_2Ur5cN15Kcc,23667
+angr/analyses/s_propagator.py,sha256=4MUmjo1aozCT-UeN9IMYlxtMjCoTM6hWwYaYTTjwvCQ,24904
 angr/analyses/smc.py,sha256=0fvLPUpjlg6GCjYnfSqanXkGYlthmPwqMYR-ZYBHsbo,5075
 angr/analyses/soot_class_hierarchy.py,sha256=R4xeacn-a_Q7PxSyj_stu5mnglZkPB5US5srKChX3mk,8740
-angr/analyses/stack_pointer_tracker.py,sha256=NoFUWzwPhmHztB3P3jESLTshkuV_4oBQkstnFcZwlVk,37710
+angr/analyses/stack_pointer_tracker.py,sha256=XcqCwqurI8x-N4mU_yfQWwIQNkj3fTtXYkUvw2PFIzw,37821
 angr/analyses/static_hooker.py,sha256=AYJXoHtdq2m-MgpJbx4eur7wy7llrKXvsVM5NdPcKHU,1852
 angr/analyses/veritesting.py,sha256=M6WNsbgiv4ScFPQIaFzujNFya66rQ9GSieaRLuC6RSo,25062
 angr/analyses/vfg.py,sha256=04X_mup9P82bkQIXMju3_DBPPJB1TytA_7RR9uAu3tU,72868
@@ -64,7 +64,7 @@ angr/analyses/vsa_ddg.py,sha256=PNJ1vQNdHKYCcuXrsXZohtjrxznaWn6GZY2TfhBoY2Q,1613
 angr/analyses/vtable.py,sha256=1Ed7jzr99rk9VgOGzcxBw_6GFqby5mIdSTGPqQPhcZM,3872
 angr/analyses/xrefs.py,sha256=vs6cpVmwXHOmxrI9lJUwCRMYbPSqvIQXS5_fINMaOGI,10290
 angr/analyses/calling_convention/__init__.py,sha256=bK5VS6AxT5l86LAhTL7l1HUT9IuvXG9x9ikbIohIFoE,194
-angr/analyses/calling_convention/calling_convention.py,sha256=GpXdhHYDK8nW8Xnma8-iJWaqAIO6o0aykI6QEXrghHo,46229
+angr/analyses/calling_convention/calling_convention.py,sha256=4QeL92Ec05cVArhunJc43rCgZD3ScHaasOmCmFfsOpU,46601
 angr/analyses/calling_convention/fact_collector.py,sha256=dIQGPHHFDNGgAcx6w4cGmjsdxKEZyu_JFBc8tsk2kWw,28885
 angr/analyses/calling_convention/utils.py,sha256=twkO073RvkkFXnOTc-KYQT1GKUtz0OPjxh0N6AWIriQ,2110
 angr/analyses/cfg/__init__.py,sha256=-w8Vd6FD6rtjlQaQ7MxwmliFgS2zt-kZepAY4gHas04,446
@@ -107,7 +107,7 @@ angr/analyses/decompiler/block_io_finder.py,sha256=xMwG8Bi69OGNYVs0U0F4yxM8kEsny
 angr/analyses/decompiler/block_similarity.py,sha256=SseCdWgh-kS9q_C_BRxlQ4OwCRQfg-9IyncxKXm_OG8,6849
 angr/analyses/decompiler/block_simplifier.py,sha256=Di5UXgBIXp0pa3_ubHY4k9vj927xAFR3oCUZ16Q3WvE,14229
 angr/analyses/decompiler/callsite_maker.py,sha256=ZjtLdxDCLS0WPqOik9bCek2LyuAtQNYA4V-yqGLeENo,23032
-angr/analyses/decompiler/clinic.py,sha256=b6H-t_uxGE21zXujPpyKk3fSg17waZEYo2BiQ0Zaneg,140692
+angr/analyses/decompiler/clinic.py,sha256=GyRoxuRtsQDv6uzvTYJXZ-GYGOFa5etFTa03UzSuvTE,144399
 angr/analyses/decompiler/condition_processor.py,sha256=61VDwVA1e-oKsv0N8kvh3c5QOdQixrkBZcm3RLuw7KU,52679
 angr/analyses/decompiler/decompilation_cache.py,sha256=oNkeyrEXhyinrN7-fKeDEuGP6I_oAclGjRS4Aa36FoE,1488
 angr/analyses/decompiler/decompilation_options.py,sha256=NDB67DI1L-stvJ4b1eQkfV26HgDJ_rG9-6PEv08G9-8,8195
@@ -128,7 +128,7 @@ angr/analyses/decompiler/sequence_walker.py,sha256=FsTQSMAm28xOdI0tbLS0UE51jDNBn
 angr/analyses/decompiler/stack_item.py,sha256=4HpYE54sOnODzMLrNX1m-Mb9RlQYjojJqNKjjDz9jxU,814
 angr/analyses/decompiler/utils.py,sha256=li5ijfTZpkRvDFh0zvLj90jyoBLDIgDapc9suc5OT6s,40443
 angr/analyses/decompiler/ccall_rewriters/__init__.py,sha256=TrnykR5cGCXy85f8OApJBjWSQ8WQSzjrnpND2fODWG8,207
-angr/analyses/decompiler/ccall_rewriters/amd64_ccalls.py,sha256=llCGH-p9AzfECO_fWTsSUYhX1SzIUr1BKRDTLfc8aXs,23426
+angr/analyses/decompiler/ccall_rewriters/amd64_ccalls.py,sha256=2kw0H-QNTt03xEm_CKIx-WwXuh7JVMeNDlENdHvXxDU,24953
 angr/analyses/decompiler/ccall_rewriters/rewriter_base.py,sha256=VbCENcybYUGrBD6U1Bp4nonNeEf05z_qhrpHBcyJw_4,496
 angr/analyses/decompiler/ccall_rewriters/x86_ccalls.py,sha256=3osgrQXaq4ArvnJNOChvzaNtovahEjfEl7igPddh-0c,2499
 angr/analyses/decompiler/counters/__init__.py,sha256=UT5K0cWgkVTAXZxy1qBBzrQip3YR2BOBVpxlAuNlt5o,480
@@ -141,13 +141,13 @@ angr/analyses/decompiler/dephication/dephication_base.py,sha256=9HdE_zKnakLSYJZr
 angr/analyses/decompiler/dephication/graph_dephication.py,sha256=xjm_OrWgcuDIoDCEAhbW4xGzCHwOPw9ya8IroZH3qf4,2169
 angr/analyses/decompiler/dephication/graph_rewriting.py,sha256=vhBGSu1VN2Yl7eethD5fiatHPOjGNs4JSov5x-SMFFw,3400
 angr/analyses/decompiler/dephication/graph_vvar_mapping.py,sha256=Pd9CETFFRuCS72dAjYlH4tqq7hzzx4CiWTSR6giDjdE,13931
-angr/analyses/decompiler/dephication/rewriting_engine.py,sha256=Sub1-9Z_tXu8vZJJPDphwwrJNgA2bC9RcrGJObd5GrA,16018
+angr/analyses/decompiler/dephication/rewriting_engine.py,sha256=x_sYM1gg56JqeQNOWNHoZ83AN-2h-nAwzgKBoeiotLQ,17646
 angr/analyses/decompiler/dephication/seqnode_dephication.py,sha256=Y5On7C6glk3VztwbQFzKYlTTRf2vu9bB5fcRH3rbuhQ,4802
 angr/analyses/decompiler/optimization_passes/__init__.py,sha256=y7ND9Wg98M5SoMGuOespoLeh1s-wFqKyeW2_4esDsiw,5236
 angr/analyses/decompiler/optimization_passes/base_ptr_save_simplifier.py,sha256=4IITiIXYK1p1D1_ynr32kdnwKgJwj0Zs0jN4DZXtSgQ,5978
 angr/analyses/decompiler/optimization_passes/call_stmt_rewriter.py,sha256=G1CEWo62dAMrm-3V4DfEDxT6kwXxuks10bcTtW9C_tA,1320
 angr/analyses/decompiler/optimization_passes/code_motion.py,sha256=7o6lf-qahXv5H8jLqEASVXHaz-_PGo3r6l7qH5PbDtU,15343
-angr/analyses/decompiler/optimization_passes/condition_constprop.py,sha256=8uU6jDkwgPwX0JtO0dmygtN8lYbV-a5q2ghC_lzrULw,8762
+angr/analyses/decompiler/optimization_passes/condition_constprop.py,sha256=S4pxO6I9XFYMwVWHbJfqGxL56MLuweZ45y_0c6uEUy8,9111
 angr/analyses/decompiler/optimization_passes/const_derefs.py,sha256=z9owQb8xNtIaVZddpFY1quHQOPEbBRnuQvmXEyiPHo0,10490
 angr/analyses/decompiler/optimization_passes/const_prop_reverter.py,sha256=N8pDb1WmIETjF8qb47YZEX8EPDbGVs9HmWxHxF0bGi0,13243
 angr/analyses/decompiler/optimization_passes/cross_jump_reverter.py,sha256=DzvgsAhU4GqvS0yN0Q2JezkJAuo2KInCgZ7fsB-ibz4,4021
@@ -155,7 +155,7 @@ angr/analyses/decompiler/optimization_passes/deadblock_remover.py,sha256=yqW4Ba4
 angr/analyses/decompiler/optimization_passes/determine_load_sizes.py,sha256=oc_sz2NmGy5SZEpO2Alv9HOOORqpn4tPcmwzHbbPfGI,2231
 angr/analyses/decompiler/optimization_passes/div_simplifier.py,sha256=fdMyGtykG9QepIUFL2_KN9lqsJFqHsVwNoJ1p8GlQ7A,18739
 angr/analyses/decompiler/optimization_passes/eager_std_string_concatenation.py,sha256=YtzDxrc3k_aWwNbqN_U4QXDJBYhJ66TLRan1NFjs1V0,7072
-angr/analyses/decompiler/optimization_passes/engine_base.py,sha256=YFYerod0qOGYoZdiKCaA8h3-NK3YR8aAw44zYZc8dl0,17287
+angr/analyses/decompiler/optimization_passes/engine_base.py,sha256=XsJPLc0SINzu_4vawmZTs28wGil0LpbSdg891zJ47p4,17532
 angr/analyses/decompiler/optimization_passes/expr_op_swapper.py,sha256=PJMJ0INWiINSkv1eD5QsMJS81XtfuyKqoqe6NTkU120,4715
 angr/analyses/decompiler/optimization_passes/flip_boolean_cmp.py,sha256=DFJjYsWf_PXNsUBX98Jh0JsWd3XXEdzbyhQrnEK8Fjw,5118
 angr/analyses/decompiler/optimization_passes/inlined_string_transformation_simplifier.py,sha256=AyAJEiResDPqEzNDOb_CbNVJL0xmwgS2mdf3V49_Wng,25446
@@ -182,7 +182,7 @@ angr/analyses/decompiler/optimization_passes/duplication_reverter/duplication_re
 angr/analyses/decompiler/optimization_passes/duplication_reverter/errors.py,sha256=dJq1F3jbGBFWi0zIUmDu8bwUAKPt-JyAh5iegY9rYuU,527
 angr/analyses/decompiler/optimization_passes/duplication_reverter/similarity.py,sha256=V5NDaCYuzoJl-i74JKKV4t9FihXsnmNbki7_4SxJfwo,4406
 angr/analyses/decompiler/optimization_passes/duplication_reverter/utils.py,sha256=szGv6t397GDMIZbn_VS14tAndKUBRF4jYETUMvlVnyU,5145
-angr/analyses/decompiler/peephole_optimizations/__init__.py,sha256=fA6RITlDQCcldmCMVU23Tfh4Dq0FEdLf4tFjGK5-qzU,4798
+angr/analyses/decompiler/peephole_optimizations/__init__.py,sha256=jNsMxMq7NW8DlhzeArTocI9wBCp55YzR30kiJKuthTM,4859
 angr/analyses/decompiler/peephole_optimizations/a_div_const_add_a_mul_n_div_const.py,sha256=4iCV9lkADp8lvcPk9vjTwyAG8j5HTBVO9NgBuB7bYhA,1636
 angr/analyses/decompiler/peephole_optimizations/a_mul_const_div_shr_const.py,sha256=I_AznhlOZG_RDBOJrGsOamH2piOX7XgqxMSt5zX8HqQ,1374
 angr/analyses/decompiler/peephole_optimizations/a_mul_const_sub_a.py,sha256=noCM779o2T8spHyQn27Wxc0B6efexlwqsNcH8aqls6c,1153
@@ -198,6 +198,7 @@ angr/analyses/decompiler/peephole_optimizations/basepointeroffset_and_mask.py,sh
 angr/analyses/decompiler/peephole_optimizations/bitwise_or_to_logical_or.py,sha256=bozJ8fGjwYHjz4wS4P5S8y_I_h9WMvp1y9VSraWrBFM,1301
 angr/analyses/decompiler/peephole_optimizations/bool_expr_xor_1.py,sha256=zyitj8lWSd1rfuVe4GDlr-HnqNAqi_uflvbM0J7WpAA,990
 angr/analyses/decompiler/peephole_optimizations/bswap.py,sha256=70XLV0WLbWFgrYFcSReR6bVgJNoacejSlzR-uzJNEqY,6410
+angr/analyses/decompiler/peephole_optimizations/cas_intrinsics.py,sha256=KdzY6alNq8TtGN2rx2zbVoRETxOqRWnvkZ381GSeYd8,4119
 angr/analyses/decompiler/peephole_optimizations/cmpord_rewriter.py,sha256=4ERanmpCQq06B6RE-AO_-jgPloyP9Jg5wcUja9iA_gI,2652
 angr/analyses/decompiler/peephole_optimizations/coalesce_adjacent_shrs.py,sha256=xZ129l0U5hoPXtczxZFUfZL59V7d0u2amQTO4phIpQU,1409
 angr/analyses/decompiler/peephole_optimizations/coalesce_same_cascading_ifs.py,sha256=h3m9FIxsMpElPE3ecFfa0vnzuxwG5oJLNEqvLuMpMgI,1062
@@ -255,11 +256,11 @@ angr/analyses/decompiler/region_simplifiers/switch_cluster_simplifier.py,sha256=
 angr/analyses/decompiler/region_simplifiers/switch_expr_simplifier.py,sha256=CngQ_LSACeEVIjuU6kIW2Y0ZSMJWFBwpL95Yh_7w3O4,3335
 angr/analyses/decompiler/ssailification/__init__.py,sha256=zcHoI7e2El2RSU_bHTpQRd1XRLHOfFScG6f3cm5y_lQ,108
 angr/analyses/decompiler/ssailification/rewriting.py,sha256=JW_StoLWuDs2LGyG8XjRUbzvQl7-7s2B8j1GKVaYoDo,15045
-angr/analyses/decompiler/ssailification/rewriting_engine.py,sha256=mcEQqX9MAPw8tpReACG4MrXDzc6d5z43d9lio565fvA,39327
+angr/analyses/decompiler/ssailification/rewriting_engine.py,sha256=WpgymMtZPYBPnyHZwzrcGrLHZ1juX0-NgPfPLOH937M,40905
 angr/analyses/decompiler/ssailification/rewriting_state.py,sha256=L7apDXQLPiItuLdQFoQdut5RMUE8MRV1zRc3CsnuH6E,1883
 angr/analyses/decompiler/ssailification/ssailification.py,sha256=GC8ue6Ywxtv0xG1XmxRUZz1HFpc19iOGk05yAsXRNvw,11035
 angr/analyses/decompiler/ssailification/traversal.py,sha256=kZcua4SlDZ8u4EIkjc1Qh85EEYGX63PZ2NYPNq78Kzs,4011
-angr/analyses/decompiler/ssailification/traversal_engine.py,sha256=wDXSAwA0jF7K49lh72kl30W-Xxs6eYFQJ-u2Ad-tmnY,11126
+angr/analyses/decompiler/ssailification/traversal_engine.py,sha256=oXTf4Z3Q2vPSGAlAPxsSKrqqDVJ3vRcg6LpNK0qJ51k,11419
 angr/analyses/decompiler/ssailification/traversal_state.py,sha256=RDs2mTc6GYnbMom2gBfNfNMcazKMSkhemEmse8uELTY,1558
 angr/analyses/decompiler/structured_codegen/__init__.py,sha256=mxG4yruPAab8735wVgXZ1zu8qFPz-njKe0m5UcywE3o,633
 angr/analyses/decompiler/structured_codegen/base.py,sha256=DEeNrBOC8AAJb-qFyUoYeX8fpHSPmAsutCDF-0UhaQ4,3782
@@ -341,7 +342,7 @@ angr/analyses/propagator/vex_vars.py,sha256=PRZOccwfdNRqEywPU-Mor3LGhakM5ItK1lRf
 angr/analyses/reaching_definitions/__init__.py,sha256=lqe-S7Jl9ZlCGgJT0kUZtNMLzmySokDz72v0pQBHh4w,2060
 angr/analyses/reaching_definitions/call_trace.py,sha256=osabHpgiV-dvifwej3mwOxckeZmG6JIXb6FDSCFzfVI,2170
 angr/analyses/reaching_definitions/dep_graph.py,sha256=yOuYhAYQQSi2aN6GIWYkgzquqg0_u4TMBbKVEupJrL4,15554
-angr/analyses/reaching_definitions/engine_ail.py,sha256=BvLsafjUOf5N0aoDYFb0IAzBKIWF0DzYRZVYZd8Bjfc,45861
+angr/analyses/reaching_definitions/engine_ail.py,sha256=7w3I1mWwvk1FxPTbPS-UCR9Mdbn_YJ_Ltyvbo4Mx5hU,46623
 angr/analyses/reaching_definitions/engine_vex.py,sha256=K486MkRAvTcTFD52pJtmjWbuVw7KURtGCEC0EDhJmRk,45601
 angr/analyses/reaching_definitions/external_codeloc.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 angr/analyses/reaching_definitions/function_handler.py,sha256=ZwtBHoAAocYIIUYVjg51sG7ejdmTnXrQzbYlUgkDKXA,29105
@@ -373,7 +374,7 @@ angr/analyses/unpacker/obfuscation_detector.py,sha256=VWMHOO2UbyiGzRYzAq9yrU3WwZ
 angr/analyses/unpacker/packing_detector.py,sha256=SO6aXR1gZkQ7w17AAv3C1-U2KAc0yL9OIQqjNOtVnuo,5331
 angr/analyses/variable_recovery/__init__.py,sha256=eA1SHzfSx8aPufUdkvgMmBnbI6VDYKKMJklcOoCO7Ao,208
 angr/analyses/variable_recovery/annotations.py,sha256=2va7cXnRHYqVqXeVt00QanxfAo3zanL4BkAcC0-Bk20,1438
-angr/analyses/variable_recovery/engine_ail.py,sha256=sFwIrUmfH1DCV9QMgPPYQdHre_svLhZXGGl7ow4WBvo,33700
+angr/analyses/variable_recovery/engine_ail.py,sha256=7kGaMVV_h4UAholuJYXazSk0a6CXk3p9H2cd8kQJ7wI,33991
 angr/analyses/variable_recovery/engine_base.py,sha256=HFv-grnBD8ubSfDykn3-mLegVwn6T0SgCE3F7sgOxs8,52348
 angr/analyses/variable_recovery/engine_vex.py,sha256=5Q2S1jAr7tALa0m0okqBHBe3cUePmJlnV1Grxos1xbo,21344
 angr/analyses/variable_recovery/irsb_scanner.py,sha256=1dL2IC7fZGuRrhmcpa2Q-G666aMPmbM8zSzmIRpLNSY,5141
@@ -423,7 +424,7 @@ angr/engines/syscall.py,sha256=7wYTriURsDTTi3PEBj4u3ZWDi7RHBV-gRrxTRxwMAVk,2166
 angr/engines/unicorn.py,sha256=fq2akQ4dVFAWqek0Yr4JTaTJWwp5vICiSQ7Sg4wuDJE,24533
 angr/engines/light/__init__.py,sha256=-634kaOlcs8ZAsMNtOML7FXP3svyZIrJb3ikq0isFv0,494
 angr/engines/light/data.py,sha256=3bvC-7e6isb4aGM7IrdpZelJDSWQ0KflC-oNpCDT7tI,21243
-angr/engines/light/engine.py,sha256=MSfHP-VFNbV6MqZTMOzQMMLsO91wesG49tYSOaalZ0E,46210
+angr/engines/light/engine.py,sha256=EQCwbipfZ_FDA-17UX0FwdhgbeWuJUagbSEc672zZjw,46429
 angr/engines/pcode/__init__.py,sha256=KWBnZnLYR3qANzXvxOt3XJq6cR57mQeNvugPBh7gr8s,195
 angr/engines/pcode/behavior.py,sha256=ycNNTNHlCJFG6fPtOwRHbI3c0fkY5pYyPA--k3Kz-WY,29406
 angr/engines/pcode/cc.py,sha256=brVglfSNnpDbRRcG-KO9EZ5NMMlmtDzP1n4kap7gKRY,3236
@@ -571,7 +572,7 @@ angr/knowledge_plugins/xrefs/__init__.py,sha256=5PhqVOtTZ27lCjJ9wp7akUeJydqILbyC
 angr/knowledge_plugins/xrefs/xref.py,sha256=U2H1rfffp5EXoh0awlGxMBxA4K5MIwl3CXjV3Uih3tA,4856
 angr/knowledge_plugins/xrefs/xref_manager.py,sha256=1n373rtV91xicAfSUresRigsZ6qCBhPOaJKrN_SW3QY,4157
 angr/knowledge_plugins/xrefs/xref_types.py,sha256=LcQ9pD4E4XlC51Us49xiqAoGAFGpnCrpYO4mOzILiKI,308
-angr/lib/angr_native.dylib,sha256=0UHQeNhsPHjQooO8mjRzzT5tFb1OLoXTnqriuKlw8bs,264696
+angr/lib/angr_native.dylib,sha256=qWPSzpslmT-miNEkIEMgzZ9RWLR4I-USccXfzaX5VAY,264696
 angr/misc/__init__.py,sha256=FoUwjk1DhqlIsr2sBN0MlR8MnSOGQv9QJhxmq32RYuA,355
 angr/misc/ansi.py,sha256=nPJHC0SKfqasMQZ0LxdmmIYojjmk4nr5jI6FrzoTwS0,811
 angr/misc/autoimport.py,sha256=iZagpuPwZWczUTYIqs-JkDMQjftMqc_cchcm7OBFiEg,3450
@@ -1309,7 +1310,7 @@ angr/storage/memory_mixins/__init__.py,sha256=a4fY0pSAwgFALjPoDRJVHKt_oMCqia_Jqi
 angr/storage/memory_mixins/actions_mixin.py,sha256=L9FlA0oyQ3gvEENfs5nvHhCYBeuKeyk_TyBh5sgiF64,3493
 angr/storage/memory_mixins/address_concretization_mixin.py,sha256=NBIeezemaCSVludIoWzcciQit4C8E_vpK8nepcn-_u0,16535
 angr/storage/memory_mixins/bvv_conversion_mixin.py,sha256=5owT0luMQkYGqAdP-CSOD821Mrg4REFG_9uuo8uaphA,2888
-angr/storage/memory_mixins/clouseau_mixin.py,sha256=Yz-ioAI_CscU6C6L2U8rGGLvPBG0j6a5s1TZH9c0LPk,5579
+angr/storage/memory_mixins/clouseau_mixin.py,sha256=3Jr8L5hS72oxVWc7at2Wd7plOb7EL5_lxHIUpoYYouM,5828
 angr/storage/memory_mixins/conditional_store_mixin.py,sha256=OekCAvHcwnzUbRN5OTzlWL-H_x0gaFr-iB6xUdjDeVc,1025
 angr/storage/memory_mixins/convenient_mappings_mixin.py,sha256=gLmp7bPvXRLGWFEHWuyAHQ1BdI5K9-47JhgdYyX2978,10290
 angr/storage/memory_mixins/default_filler_mixin.py,sha256=9xwaHqJziT07dMtHtIU_ni0b_Wh9azPiTbPSnJ4ZS10,5992
@@ -1370,7 +1371,7 @@ angr/utils/enums_conv.py,sha256=fA6qeoRZ6Cj6gCIS_PZbP4PX7E8IybnYQ90OZGnBVrc,2746
 angr/utils/env.py,sha256=aO4N2h7DUsUQtTgnC5J_oPHvMxJRur20m5UFSkmy4XU,398
 angr/utils/formatting.py,sha256=OWzSfAlKcL09cEtcqxszYWHsRO9tih7hvXD2K9kUZc8,4343
 angr/utils/funcid.py,sha256=Rd4r8juv2IpeMtCpPp4wxJoEZTnZZ1NsxdT42tvrKVA,6353
-angr/utils/graph.py,sha256=yCsmWXU_S-EfOT-I2iAqwZWVi5ASUC3mKCSF8ZGBmzo,31566
+angr/utils/graph.py,sha256=KgmX5yCe2AxqfPgpXbXWwQ7j32AYNIuhMaNoESPt5Hw,31537
 angr/utils/lazy_import.py,sha256=7Mx-y-aZFsXX9jNxvEcXT-rO8tL8rknb6D6RbSFOI1M,343
 angr/utils/library.py,sha256=z3rFYm7ePZTXNZJuKiQrR0SnlbVb-OzkX0t0U44nXDk,7181
 angr/utils/loader.py,sha256=5PtUlonkbqENNg3AMJ4YI3-g5dyyXJ0GP83SwO2dECY,1951
@@ -1380,12 +1381,12 @@ angr/utils/segment_list.py,sha256=DulfCDdNETMehseRey64FkjmORQvoSyVd9eRZ4sQ7tw,21
 angr/utils/tagged_interval_map.py,sha256=rXKBuT14N23AAntpOKhZhmA-qqymnsvjpheFXoTRVRA,4417
 angr/utils/timing.py,sha256=n-YZ86g0ZWmLhsoNvcimRpKzewR5hmquLZe6fagxlBw,2224
 angr/utils/types.py,sha256=5EDtrusFLf1fIcMz8fgJiPPsUhpEm0bf_oqZ_PSRje0,1836
-angr/utils/ssa/__init__.py,sha256=ohP9IJh9ZvdVH8nH-ZrYA8hwIi8L98XQ6NMNL6q_pJ0,13649
+angr/utils/ssa/__init__.py,sha256=ZUPoK7Y1k-7vQkvoYUYPMdjfGh4oC6W3VbWzV_udZHg,14020
 angr/utils/ssa/tmp_uses_collector.py,sha256=rSpvMxBHzg-tmvhsfjn3iLyPEKzaZN-xpQrdslMq3J4,793
 angr/utils/ssa/vvar_uses_collector.py,sha256=O2aNZeM5DL8qatyhYuMhgbYGFp6Onm2yr9pKq1wRjA0,1347
-angr-9.2.150.dist-info/licenses/LICENSE,sha256=PmWf0IlSz6Jjp9n7nyyBQA79Q5C2ma68LRykY1V3GF0,1456
-angr-9.2.150.dist-info/METADATA,sha256=ArmKS_xO7TD2tYLOgol_yy5ANcGpXDh5PQB8wbMzKKg,4910
-angr-9.2.150.dist-info/WHEEL,sha256=YJko8HaqWL7RZj-eYXRM0Eg6Tr2R-DY8R8lYY8AybKM,106
-angr-9.2.150.dist-info/entry_points.txt,sha256=Vjh1C8PMyr5dZFMnik5WkEP01Uwr2T73I3a6N32sgQU,44
-angr-9.2.150.dist-info/top_level.txt,sha256=dKw0KWTbwLXytFvv15oAAG4sUs3ey47tt6DorJG9-hw,5
-angr-9.2.150.dist-info/RECORD,,
+angr-9.2.152.dist-info/licenses/LICENSE,sha256=PmWf0IlSz6Jjp9n7nyyBQA79Q5C2ma68LRykY1V3GF0,1456
+angr-9.2.152.dist-info/METADATA,sha256=gen2o641GCTQ_68STSXm_FqZ_lp6gRZXlxlv4wBABhY,4910
+angr-9.2.152.dist-info/WHEEL,sha256=Nc-chqW4kUTC2rlmGRTJjDt63XYahHFuunBTZ7fPjkM,106
+angr-9.2.152.dist-info/entry_points.txt,sha256=Vjh1C8PMyr5dZFMnik5WkEP01Uwr2T73I3a6N32sgQU,44
+angr-9.2.152.dist-info/top_level.txt,sha256=dKw0KWTbwLXytFvv15oAAG4sUs3ey47tt6DorJG9-hw,5
+angr-9.2.152.dist-info/RECORD,,

{angr-9.2.150.dist-info → angr-9.2.152.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: setuptools (78.1.0)
+Generator: setuptools (79.0.0)
 Root-Is-Purelib: true
 Tag: py3-none-macosx_10_9_x86_64