angr 9.2.138__py3-none-macosx_11_0_arm64.whl → 9.2.139__py3-none-macosx_11_0_arm64.whl

angr/analyses/variable_recovery/engine_base.py

@@ -1,5 +1,5 @@
 from __future__ import annotations
-from typing import Any, TYPE_CHECKING, Generic, TypeVar, cast
+from typing import Any, Generic, TypeVar, cast
 import contextlib
 import logging
 
@@ -16,8 +16,6 @@ from angr.code_location import CodeLocation
 from angr.analyses.typehoon import typevars, typeconsts
 from angr.analyses.typehoon.typevars import TypeVariable, DerivedTypeVariable, AddN, SubN, Load, Store
 
-if TYPE_CHECKING:
-    from angr.knowledge_plugins.variables.variable_manager import VariableManager
 
 #
 # The base engine used in VariableRecoveryFast
@@ -72,8 +70,6 @@ class SimEngineVRBase(
     and storing data.
     """
 
-    variable_manager: VariableManager
-
     def __init__(self, project, kb):
         super().__init__(project)
 
@@ -86,10 +82,6 @@ class SimEngineVRBase(
             return None
         return self.state.function.addr
 
-    def process(self, state, *args, **kwargs):
-        self.variable_manager = state.variable_manager
-        super().process(state, *args, **kwargs)
-
     def _top(self, bits):
         return RichR(self.state.top(bits))
 
@@ -130,9 +122,9 @@ class SimEngineVRBase(
                 if abs_offset.op == "__lshift__" and cast(claripy.ast.BV, abs_offset.args[1]).concrete:
                     offset = cast(claripy.ast.BV, abs_offset.args[0])
                     elem_size = 2 ** cast(claripy.ast.BV, abs_offset.args[1]).concrete_value
-                elif abs_offset.op == "__mul__" and abs_offset.args[1].concrete:
-                    offset = abs_offset.args[0]
-                    elem_size = abs_offset.args[1].concrete_value
+                elif abs_offset.op == "__mul__" and cast(claripy.ast.BV, abs_offset.args[1]).concrete:
+                    offset = cast(claripy.ast.BV, abs_offset.args[0])
+                    elem_size = cast(claripy.ast.BV, abs_offset.args[1]).concrete_value
 
             if base_addr is not None and offset is not None and elem_size is not None:
                 return base_addr, offset, elem_size
@@ -152,7 +144,7 @@ class SimEngineVRBase(
             # extract stack offset
             stack_offset: int | None = self.state.get_stack_offset(data)
 
-            variable_manager = self.variable_manager[self.func_addr]
+            variable_manager = self.state.variable_manager[self.func_addr]
             var_candidates: list[tuple[SimVariable, int]] = variable_manager.find_variables_by_stmt(
                 self.block.addr, self.stmt_idx, "memory"
             )
@@ -190,10 +182,10 @@ class SimEngineVRBase(
                             stack_offset,
                             lea_size,
                             base="bp",
-                            ident=self.variable_manager[self.func_addr].next_variable_ident("stack"),
+                            ident=self.state.variable_manager[self.func_addr].next_variable_ident("stack"),
                             region=self.func_addr,
                         )
-                        self.variable_manager[self.func_addr].add_variable("stack", stack_offset, variable)
+                        self.state.variable_manager[self.func_addr].add_variable("stack", stack_offset, variable)
                         l.debug("Identified a new stack variable %s at %#x.", variable, self.ins_addr)
                         existing_vars.append((variable, 0))
 
@@ -212,7 +204,7 @@ class SimEngineVRBase(
             # this is probably an address for a global variable
             global_var_addr = data.concrete_value
 
-            variable_manager = self.variable_manager["global"]
+            variable_manager = self.state.variable_manager["global"]
 
             # special case for global variables: find existing variable by base address
             existing_vars = [(var, 0) for var in variable_manager.get_global_variables(global_var_addr)]
@@ -249,7 +241,7 @@ class SimEngineVRBase(
             # extract stack offset
             stack_offset: int | None = self.state.get_stack_offset(data)
 
-            variable_manager = self.variable_manager[self.func_addr]
+            variable_manager = self.state.variable_manager[self.func_addr]
             var_candidates: list[tuple[SimVariable, int]] = variable_manager.find_variables_by_stmt(
                 self.block.addr,
                 self.stmt_idx,
@@ -265,7 +257,7 @@ class SimEngineVRBase(
         elif self.state.is_global_variable_address(data):
             # this is probably an address for a global variable
             global_var_addr = data.concrete_value
-            variable_manager = self.variable_manager["global"]
+            variable_manager = self.state.variable_manager["global"]
             # special case for global variables: find existing variable by base address
             existing_vars = [(var, 0) for var in variable_manager.get_global_variables(global_var_addr)]
         else:
@@ -319,9 +311,9 @@ class SimEngineVRBase(
         # handle register writes
 
         # first check if there is an existing variable for the atom at this location already
-        existing_vars: set[tuple[SimVariable, int]] = self.variable_manager[self.func_addr].find_variables_by_atom(
-            self.block.addr, self.stmt_idx, dst
-        )
+        existing_vars: set[tuple[SimVariable, int]] = self.state.variable_manager[
+            self.func_addr
+        ].find_variables_by_atom(self.block.addr, self.stmt_idx, dst)
         if not existing_vars:
             # next check if we are overwriting *part* of an existing variable that is not an input variable
             addr_and_variables = set()
@@ -334,7 +326,7 @@ class SimEngineVRBase(
                         addr_and_variables.update(self.state.extract_variables(value))
             except SimMemoryMissingError:
                 pass
-            input_vars = self.variable_manager[self.func_addr].input_variables()
+            input_vars = self.state.variable_manager[self.func_addr].input_variables()
             existing_vars = {
                 (av[1], av[0]) for av in addr_and_variables if av[1] not in input_vars and av[1].size > size
             }
@@ -343,10 +335,10 @@ class SimEngineVRBase(
             variable = SimRegisterVariable(
                 offset,
                 size,
-                ident=self.variable_manager[self.func_addr].next_variable_ident("register"),
+                ident=self.state.variable_manager[self.func_addr].next_variable_ident("register"),
                 region=self.func_addr,
             )
-            self.variable_manager[self.func_addr].add_variable("register", offset, variable)
+            self.state.variable_manager[self.func_addr].add_variable("register", offset, variable)
         else:
             variable, _ = next(iter(existing_vars))
 
@@ -355,7 +347,7 @@ class SimEngineVRBase(
         v = MultiValues(annotated_data)
         self.state.register_region.store(offset, v)
         # register with the variable manager
-        self.variable_manager[self.func_addr].write_to(variable, None, codeloc, atom=dst, overwrite=False)
+        self.state.variable_manager[self.func_addr].write_to(variable, None, codeloc, atom=dst, overwrite=False)
 
         if richr.typevar is not None:
             if not self.state.typevars.has_type_variable_for(variable, codeloc):
@@ -397,9 +389,9 @@ class SimEngineVRBase(
         self._reference(richr, codeloc)
 
         # first check if there is an existing variable for the atom at this location already
-        existing_vars: set[tuple[SimVariable, int]] = self.variable_manager[self.func_addr].find_variables_by_atom(
-            self.block.addr, self.stmt_idx, dst
-        )
+        existing_vars: set[tuple[SimVariable, int]] = self.state.variable_manager[
+            self.func_addr
+        ].find_variables_by_atom(self.block.addr, self.stmt_idx, dst)
         if not existing_vars:
             # next check if there is already a variable for the vvar ID
             addr_and_variables = set()
@@ -415,33 +407,33 @@ class SimEngineVRBase(
                 variable = SimRegisterVariable(
                     vvar.reg_offset,
                     vvar.size,
-                    ident=self.variable_manager[self.func_addr].next_variable_ident("register"),
+                    ident=self.state.variable_manager[self.func_addr].next_variable_ident("register"),
                     region=self.func_addr,
                 )
-                self.variable_manager[self.func_addr].add_variable("register", vvar.reg_offset, variable)
+                self.state.variable_manager[self.func_addr].add_variable("register", vvar.reg_offset, variable)
             elif vvar.was_stack:
                 variable = SimStackVariable(
                     vvar.stack_offset,
                     vvar.size,
-                    ident=self.variable_manager[self.func_addr].next_variable_ident("stack"),
+                    ident=self.state.variable_manager[self.func_addr].next_variable_ident("stack"),
                     region=self.func_addr,
                 )
-                self.variable_manager[self.func_addr].add_variable("stack", vvar.stack_offset, variable)
+                self.state.variable_manager[self.func_addr].add_variable("stack", vvar.stack_offset, variable)
             elif vvar.was_parameter:
                 # FIXME: we assume all parameter vvars were registers
                 variable = SimRegisterVariable(
                     vvar.reg_offset,
                     vvar.size,
-                    ident=self.variable_manager[self.func_addr].next_variable_ident("register"),
+                    ident=self.state.variable_manager[self.func_addr].next_variable_ident("register"),
                     region=self.func_addr,
                 )
-                self.variable_manager[self.func_addr].add_variable("register", vvar.oident, variable)
+                self.state.variable_manager[self.func_addr].add_variable("register", vvar.oident, variable)
             elif vvar.was_tmp:
                 # FIXME: we treat all tmp vvars as registers
                 variable = SimRegisterVariable(
                     4096 + vvar.tmp_idx,
                     vvar.size,
-                    ident=self.variable_manager[self.func_addr].next_variable_ident("register"),
+                    ident=self.state.variable_manager[self.func_addr].next_variable_ident("register"),
                     region=self.func_addr,
                 )
             else:
@@ -452,7 +444,7 @@ class SimEngineVRBase(
         # FIXME: The offset does not have to be 0
         annotated_data = self.state.annotate_with_variables(data, [(0, variable)])
         self.vvar_region[vvar_id] = annotated_data
-        self.variable_manager[self.func_addr].write_to(variable, None, codeloc, atom=dst, overwrite=False)
+        self.state.variable_manager[self.func_addr].write_to(variable, None, codeloc, atom=dst, overwrite=False)
 
         if richr.typevar is not None:
             if not self.state.typevars.has_type_variable_for(variable, codeloc):
@@ -502,13 +494,13 @@ class SimEngineVRBase(
 
         if not stored:
             # remove existing variables linked to this statement
-            existing_vars = self.variable_manager[self.func_addr].find_variables_by_stmt(
+            existing_vars = self.state.variable_manager[self.func_addr].find_variables_by_stmt(
                 self.block.addr, self.stmt_idx, "memory"
             )
             codeloc = self._codeloc()
             if existing_vars:
                 for existing_var, _ in list(existing_vars):
-                    self.variable_manager[self.func_addr].remove_variable_by_atom(codeloc, existing_var, atom)
+                    self.state.variable_manager[self.func_addr].remove_variable_by_atom(codeloc, existing_var, atom)
 
             # storing to a location specified by a pointer whose value cannot be determined at this point
             self._store_to_variable(richr_addr, size)
@@ -517,11 +509,11 @@ class SimEngineVRBase(
         self, stack_offset, data: RichR[claripy.ast.BV | claripy.ast.FP], size, offset=0, atom=None, endness=None
     ):
         if atom is None:
-            existing_vars = self.variable_manager[self.func_addr].find_variables_by_stmt(
+            existing_vars = self.state.variable_manager[self.func_addr].find_variables_by_stmt(
                 self.block.addr, self.stmt_idx, "memory"
             )
         else:
-            existing_vars = self.variable_manager[self.func_addr].find_variables_by_atom(
+            existing_vars = self.state.variable_manager[self.func_addr].find_variables_by_atom(
                 self.block.addr, self.stmt_idx, atom
             )
         if not existing_vars:
@@ -529,12 +521,12 @@ class SimEngineVRBase(
                 stack_offset,
                 size,
                 base="bp",
-                ident=self.variable_manager[self.func_addr].next_variable_ident("stack"),
+                ident=self.state.variable_manager[self.func_addr].next_variable_ident("stack"),
                 region=self.func_addr,
             )
             variable_offset = offset
             if isinstance(stack_offset, int):
-                self.variable_manager[self.func_addr].set_variable("stack", stack_offset, variable)
+                self.state.variable_manager[self.func_addr].set_variable("stack", stack_offset, variable)
                 l.debug("Identified a new stack variable %s at %#x.", variable, self.ins_addr)
 
         else:
@@ -562,7 +554,7 @@ class SimEngineVRBase(
                 offset_into_var = var_offset
                 if offset_into_var == 0:
                     offset_into_var = None
-                self.variable_manager[self.func_addr].write_to(
+                self.state.variable_manager[self.func_addr].write_to(
                     var,
                     offset_into_var,
                     codeloc,
@@ -589,7 +581,7 @@ class SimEngineVRBase(
         offset: claripy.ast.BV | None = None,
         elem_size: int | None = None,
     ):
-        variable_manager = self.variable_manager["global"]
+        variable_manager = self.state.variable_manager["global"]
         if stmt is None:
             existing_vars = variable_manager.find_variables_by_stmt(self.block.addr, self.stmt_idx, "memory")
         else:
@@ -696,9 +688,6 @@ class SimEngineVRBase(
                 base_typevar = typevar
                 field_offset = 0
 
-            # if addr_variable is not None:
-            #     self.variable_manager[self.func_addr].reference_at(addr_variable, field_offset, codeloc, atom=stmt)
-
             store_typevar = self._create_access_typevar(base_typevar, True, size, field_offset)
             if addr_variable is not None:
                 self.state.typevars.add_type_variable(addr_variable, codeloc, typevar)
@@ -766,16 +755,18 @@ class SimEngineVRBase(
                                     all_vars.add((var_offset, var_))
 
                 if not all_vars and concrete_offset is not None:
-                    variables = self.variable_manager[self.func_addr].find_variables_by_stack_offset(concrete_offset)
+                    variables = self.state.variable_manager[self.func_addr].find_variables_by_stack_offset(
+                        concrete_offset
+                    )
                     if not variables:
                         variable = SimStackVariable(
                             concrete_offset,
                             size,
                             base="bp",
-                            ident=self.variable_manager[self.func_addr].next_variable_ident("stack"),
+                            ident=self.state.variable_manager[self.func_addr].next_variable_ident("stack"),
                             region=self.func_addr,
                         )
-                        self.variable_manager[self.func_addr].add_variable("stack", concrete_offset, variable)
+                        self.state.variable_manager[self.func_addr].add_variable("stack", concrete_offset, variable)
                         variables = {variable}
                         l.debug("Identified a new stack variable %s at %#x.", variable, self.ins_addr)
                     for variable in variables:
@@ -814,7 +805,7 @@ class SimEngineVRBase(
                                 var_offset,
                             ),
                         )
-                self.variable_manager[self.func_addr].read_from(
+                self.state.variable_manager[self.func_addr].read_from(
                     var,
                     offset_into_variable,
                     codeloc,
@@ -864,12 +855,12 @@ class SimEngineVRBase(
         if v is None and expr is not None:
             # failed to map the address to a known variable
             # remove existing variables linked to this variable
-            existing_vars = self.variable_manager[self.func_addr].find_variables_by_atom(
+            existing_vars = self.state.variable_manager[self.func_addr].find_variables_by_atom(
                 self.block.addr, self.stmt_idx, expr
             )
             if existing_vars:
                 for existing_var, _ in list(existing_vars):
-                    self.variable_manager[self.func_addr].remove_variable_by_atom(codeloc, existing_var, expr)
+                    self.state.variable_manager[self.func_addr].remove_variable_by_atom(codeloc, existing_var, expr)
 
         # Loading data from a pointer
         if richr_addr.type_constraints:
@@ -901,7 +892,7 @@ class SimEngineVRBase(
         offset: claripy.ast.BV | None = None,
         elem_size: int | None = None,
     ) -> RichR[claripy.ast.BV]:
-        variable_manager = self.variable_manager["global"]
+        variable_manager = self.state.variable_manager["global"]
         if expr is None:
             existing_vars = variable_manager.find_variables_by_stmt(self.block.addr, self.stmt_idx, "memory")
         else:
@@ -992,11 +983,11 @@ class SimEngineVRBase(
                 variable = SimRegisterVariable(
                     offset,
                     size if force_variable_size is None else force_variable_size,
-                    ident=self.variable_manager[self.func_addr].next_variable_ident("register"),
+                    ident=self.state.variable_manager[self.func_addr].next_variable_ident("register"),
                     region=self.func_addr,
                 )
                 value = self.state.annotate_with_variables(value, [(0, variable)])
-                self.variable_manager[self.func_addr].add_variable("register", offset, variable)
+                self.state.variable_manager[self.func_addr].add_variable("register", offset, variable)
             self.state.register_region.store(offset, value)
             value_list = [{value}]
         else:
@@ -1006,7 +997,9 @@ class SimEngineVRBase(
         for value_set in value_list:
             for value in value_set:
                 for _, var in self.state.extract_variables(value):
-                    self.variable_manager[self.func_addr].read_from(var, None, codeloc, atom=expr, overwrite=False)
+                    self.state.variable_manager[self.func_addr].read_from(
+                        var, None, codeloc, atom=expr, overwrite=False
+                    )
                     variable_set.add(var)
 
         if offset == self.project.arch.sp_offset:
@@ -1078,20 +1071,20 @@ class SimEngineVRBase(
                     variable = SimRegisterVariable(
                         vvar.reg_offset,
                         vvar.size,
-                        ident=self.variable_manager[self.func_addr].next_variable_ident("register"),
+                        ident=self.state.variable_manager[self.func_addr].next_variable_ident("register"),
                         region=self.func_addr,
                     )
                     value = self.state.annotate_with_variables(value, [(0, variable)])
-                    self.variable_manager[self.func_addr].add_variable("register", vvar.reg_offset, variable)
+                    self.state.variable_manager[self.func_addr].add_variable("register", vvar.reg_offset, variable)
                 elif vvar.category == ailment.Expr.VirtualVariableCategory.STACK:
                     variable = SimStackVariable(
                         vvar.stack_offset,
                         vvar.size,
-                        ident=self.variable_manager[self.func_addr].next_variable_ident("stack"),
+                        ident=self.state.variable_manager[self.func_addr].next_variable_ident("stack"),
                         region=self.func_addr,
                     )
                     value = self.state.annotate_with_variables(value, [(0, variable)])
-                    self.variable_manager[self.func_addr].add_variable("stack", vvar.stack_offset, variable)
+                    self.state.variable_manager[self.func_addr].add_variable("stack", vvar.stack_offset, variable)
                 elif vvar.category == ailment.Expr.VirtualVariableCategory.PARAMETER:
                     raise KeyError(f"Missing virtual variable for parameter {vvar}")
                 elif vvar.category == ailment.Expr.VirtualVariableCategory.TMP:
@@ -1104,7 +1097,7 @@ class SimEngineVRBase(
 
         variable_set = set()
         for _, var in self.state.extract_variables(value):
-            self.variable_manager[self.func_addr].read_from(var, None, codeloc, atom=expr, overwrite=False)
+            self.state.variable_manager[self.func_addr].read_from(var, None, codeloc, atom=expr, overwrite=False)
             variable_set.add(var)
 
         if (

angr/analyses/variable_recovery/engine_vex.py

@@ -51,7 +51,7 @@ class SimEngineVRVEX(
 
     def _process_block(self, whitelist=None):
         scanner = VEXIRSBScanner(self.project, logger=self.l)
-        scanner._process(None, block=self.block)
+        scanner.process(None, block=self.block)
         self.stmts_to_lower = scanner.stmts_to_lower
         self.reg_read_stmts_to_ignore = scanner.reg_read_stmts_to_ignore
 

angr/analyses/variable_recovery/irsb_scanner.py

@@ -39,12 +39,12 @@ class VEXIRSBScanner(SimEngineLightVEX[None, None, None, None]):
     def _is_top(self, expr) -> bool:
         return True
 
-    def _process(self, state, *, block=None, whitelist=None, **kwargs):
+    def process(self, state, *, block=None, whitelist=None, **kwargs):
         self.tmps_with_64bit_regs = set()
         self.tmps_assignment_stmtidx = {}
         self.tmps_converted_to_32bit = set()
 
-        super()._process(state, block=block, whitelist=whitelist, **kwargs)
+        super().process(state, block=block, whitelist=whitelist, **kwargs)
 
         self.stmts_to_lower = {self.tmps_assignment_stmtidx[i] for i in self.tmps_converted_to_32bit}
 

angr/calling_conventions.py

@@ -11,6 +11,7 @@ import archinfo
 from archinfo import RegisterName
 from unique_log_filter import UniqueLogFilter
 
+import angr
 from .errors import AngrTypeError
 from .sim_type import (
     SimType,
@@ -33,7 +34,6 @@ from .sim_type import (
     SimTypeReference,
 )
 from .state_plugins.sim_action_object import SimActionObject
-from .engines.soot.engine import SootMixin
 
 l = logging.getLogger(name=__name__)
 l.addFilter(UniqueLogFilter())
@@ -307,7 +307,7 @@ class SimRegArg(SimFunctionArgument):
     def __hash__(self):
         return hash((self.size, self.reg_name, self.reg_offset))
 
-    def check_offset(self, arch):
+    def check_offset(self, arch) -> int:
         return arch.registers[self.reg_name][0] + self.reg_offset
 
     def set_value(self, state, value, **kwargs):  # pylint: disable=unused-argument,arguments-differ
@@ -582,7 +582,12 @@ class SimCC:
     FP_RETURN_VAL: SimFunctionArgument | None = (
         None  # The location where floating-point argument return values are stored
     )
-    ARCH = None  # The archinfo.Arch class that this CC must be used for, if relevant
+    ARCH: type[archinfo.Arch] | None = (
+        None  # The archinfo.Arch class for which this CC is most likely relevant, if related
+    )
+    # archinfo.Arch classes for which this CC is relevant, in addition to self.ARCH.
+    # you should access cls.arches() to get a list of all arches for which this CC is relevant
+    EXTRA_ARCHES: tuple[type[archinfo.Arch], ...] = ()
     CALLEE_CLEANUP = False  # Whether the callee has to deallocate the stack space for the arguments
 
     STACK_ALIGNMENT = 1  # the alignment requirement of the stack pointer at function start BEFORE call
@@ -1082,8 +1087,8 @@ class SimCC:
 
     @classmethod
     def _match(cls, arch, args: list, sp_delta):
-        if cls.ARCH is not None and not isinstance(
-            arch, cls.ARCH
+        if (
+            cls.arches() is not None and ":" not in arch.name and not isinstance(arch, cls.arches())
         ):  # pylint:disable=isinstance-second-argument-not-valid-type
             return False
         if sp_delta != cls.STACKARG_SP_DIFF:
@@ -1149,6 +1154,12 @@ class SimCC:
                 return cc_cls(arch)
         return None
 
+    @classmethod
+    def arches(cls) -> tuple[type[archinfo.Arch], ...]:
+        if cls.ARCH is not None:
+            return (cls.ARCH, *cls.EXTRA_ARCHES)
+        return cls.EXTRA_ARCHES
+
     def get_arg_info(self, state, prototype):
         """
         This is just a simple wrapper that collects the information from various locations
@@ -1444,7 +1455,7 @@ class SimCCSystemVAMD64(SimCC):
 
     @classmethod
     def _match(cls, arch, args, sp_delta):
-        if cls.ARCH is not None and not isinstance(arch, cls.ARCH):
+        if cls.ARCH is not None and ":" not in arch.name and not isinstance(arch, cls.ARCH):
             return False
         # if sp_delta != cls.STACKARG_SP_DIFF:
         #    return False
@@ -1789,8 +1800,54 @@ class SimCCARMHF(SimCCARM):
     FP_RETURN_VAL = SimRegArg("s0", 32)
     CALLER_SAVED_REGS = []
     RETURN_ADDR = SimRegArg("lr", 4)
-    RETURN_VAL = SimRegArg("r0", 4)  # TODO Return val can also include reg r1
+    RETURN_VAL = SimRegArg("r0", 4)
+    OVERFLOW_RETURN_VAL = SimRegArg("r1", 4)
     ARCH = archinfo.ArchARMHF
+    EXTRA_ARCHES = (archinfo.ArchARMCortexM,)
+
+    def next_arg(self, session, arg_type):
+        if isinstance(arg_type, (SimTypeArray, SimTypeFixedSizeArray)):  # hack
+            arg_type = SimTypePointer(arg_type.elem_type).with_arch(self.arch)
+        state = session.getstate()
+        classification = self._classify(arg_type)
+        try:
+            mapped_classes = []
+            for cls in classification:
+                if cls == "DOUBLEP":
+                    if session.getstate()[1] % 2 == 1:  # doubles must start on an even register
+                        next(session.int_iter)
+
+                    if session.getstate()[1] == len(self.ARG_REGS) - 2:
+                        mapped_classes.append(next(session.int_iter))
+                        mapped_classes.append(next(session.both_iter))
+                    else:
+                        try:
+                            mapped_classes.append(next(session.int_iter))
+                            mapped_classes.append(next(session.int_iter))
+                        except StopIteration:
+                            mapped_classes.append(next(session.both_iter))
+                            mapped_classes.append(next(session.both_iter))
+                elif cls == "NO_CLASS":
+                    raise NotImplementedError("Bug. Report to @rhelmot")
+                elif cls == "MEMORY":
+                    mapped_classes.append(next(session.both_iter))
+                elif cls == "INTEGER":
+                    try:
+                        mapped_classes.append(next(session.int_iter))
+                    except StopIteration:
+                        mapped_classes.append(next(session.both_iter))
+                elif cls == "SINGLEP":
+                    try:
+                        mapped_classes.append(next(session.fp_iter))
+                    except StopIteration:
+                        mapped_classes.append(next(session.both_iter))
+                else:
+                    raise NotImplementedError("Bug. Report to @rhelmot")
+        except StopIteration:
+            session.setstate(state)
+            mapped_classes = [next(session.both_iter) for _ in classification]
+
+        return refine_locs_with_struct_type(self.arch, mapped_classes, arg_type)
 
 
 class SimCCARMLinuxSyscall(SimCCSyscall):
@@ -2122,7 +2179,7 @@ class SimCCSoot(SimCC):
     ARG_REGS = []
 
     def setup_callsite(self, state, ret_addr, args, prototype, stack_base=None, alloc_base=None, grow_like_stack=True):
-        SootMixin.setup_callsite(state, args, ret_addr)
+        angr.engines.SootMixin.setup_callsite(state, args, ret_addr)
 
     @staticmethod
     def guess_prototype(args, prototype=None):
@@ -2226,7 +2283,7 @@ DEFAULT_CC: dict[str, dict[str, type[SimCC]]] = {
     "X86": {"Linux": SimCCCdecl, "CGC": SimCCCdecl, "Win32": SimCCMicrosoftCdecl},
     "ARMEL": {"Linux": SimCCARM},
     "ARMHF": {"Linux": SimCCARMHF},
-    "ARMCortexM": {"Linux": SimCCARM},
+    "ARMCortexM": {"Linux": SimCCARMHF},
     "MIPS32": {"Linux": SimCCO32},
     "MIPS64": {"Linux": SimCCN64},
     "PPC32": {"Linux": SimCCPowerPC},

angr/engines/engine.py

@@ -24,10 +24,9 @@ DataType_co = TypeVar("DataType_co", covariant=True)
 HeavyState = SimState[int | SootAddressDescriptor, claripy.ast.BV | SootAddressDescriptor]
 
 
-class SimEngineBase(Generic[StateType]):
+class SimEngine(Generic[StateType, ResultType], metaclass=abc.ABCMeta):
     """
-    Even more basey of a base class for SimEngine. Used as a base by mixins which want access to the project but for
-    which having method `process` (contained in `SimEngine`) doesn't make sense
+    A SimEngine is a type which understands how to perform execution on a state.
     """
 
     state: StateType
@@ -43,21 +42,6 @@ class SimEngineBase(Generic[StateType]):
         self.project = state[0]
 
 
-class SimEngine(Generic[StateType, ResultType], SimEngineBase[StateType], metaclass=abc.ABCMeta):
-    """
-    A SimEngine is a class which understands how to perform execution on a state. This is a base class.
-    """
-
-    @abc.abstractmethod
-    def process(self, state: StateType, **kwargs) -> ResultType:
-        """
-        The main entry point for an engine. Should take a state and return a result.
-
-        :param state:   The state to proceed from
-        :return:        The result. Whatever you want ;)
-        """
-
-
 class SuccessorsMixin(SimEngine[HeavyState, SimSuccessors]):
     """
     A mixin for SimEngine which implements ``process`` to perform common operations related to symbolic execution

angr/engines/light/engine.py

@@ -64,13 +64,8 @@ class SimEngineLight(Generic[StateType, DataType_co, BlockType, ResultType], Sim
         self.l = logger or logging.getLogger(self.__module__ + "." + self.__class__.__name__)
         super().__init__(project)
 
-    # there's two of these to support the mixin pattern - mixins can override process while there must be some base
-    # class that provides _process
-    def process(self, state: StateType, *, block: BlockType | None = None, **kwargs) -> ResultType:
-        return self._process(state, block=block, **kwargs)
-
     @abstractmethod
-    def _process(self, state: StateType, *, block: BlockType | None = None, **kwargs) -> ResultType: ...
+    def process(self, state: StateType, *, block: BlockType | None = None, **kwargs) -> ResultType: ...
 
     def lift(self, state: StateType) -> BlockType:
         raise TypeError(f"{type(self)} requires `block` to be passed to `process`")
@@ -267,7 +262,7 @@ class SimEngineLightVEX(
             if name.startswith("_handle_dirty_")
         }
 
-    def _process(
+    def process(
         self, state: StateType, *, block: Block | None = None, whitelist: set[int] | None = None, **kwargs
     ) -> ResultType:
         # initialize local variables
@@ -640,7 +635,7 @@ class SimEngineLightAIL(
         }
         super().__init__(*args, **kwargs)
 
-    def _process(
+    def process(
         self, state: StateType, *, block: ailment.Block | None = None, whitelist: set[int] | None = None, **kwargs
     ) -> ResultType:
         self.tmps = {}

angr/engines/pcode/emulate.py

@@ -4,7 +4,7 @@ import logging
 import claripy
 from claripy.ast.bv import BV
 
-from angr.engines.engine import SimEngineBase
+from angr.engines.engine import SimEngine
 from angr.utils.constants import DEFAULT_STATEMENT
 from .lifter import IRSB
 from .behavior import OpBehavior
@@ -19,7 +19,7 @@ with contextlib.suppress(ImportError):
 l = logging.getLogger(__name__)
 
 
-class PcodeEmulatorMixin(SimEngineBase):
+class PcodeEmulatorMixin(SimEngine):
     """
     Mixin for p-code execution.
     """

angr/engines/pcode/lifter.py

@@ -20,7 +20,7 @@ from cachetools import LRUCache
 from pyvex.errors import PyVEXError, SkipStatementsError, LiftingException
 
 from .behavior import BehaviorFactory
-from angr.engines.engine import SimEngineBase
+from angr.engines.engine import SimEngine
 from angr.state_plugins.inspect import BP_AFTER, BP_BEFORE
 from angr.sim_state import SimState
 from angr.misc.ux import once
@@ -981,7 +981,7 @@ class PcodeLifter(Lifter):
             raise LiftingException(f"pypcode: could not decode any instructions @ 0x{self.addr:x}")
 
 
-class PcodeLifterEngineMixin(SimEngineBase):
+class PcodeLifterEngineMixin(SimEngine):
     """
     Lifter mixin to lift from machine code to P-Code.
     """