angr 9.2.135__py3-none-manylinux2014_x86_64.whl → 9.2.137__py3-none-manylinux2014_x86_64.whl

angr/analyses/decompiler/optimization_passes/ite_region_converter.py

@@ -263,7 +263,7 @@ class ITERegionConverter(OptimizationPass):
 
             # is this the statement that we are looking for?
             found_true_src_vvar, found_false_src_vvar = False, False
-            for src, vvar in stmt.src.src_and_vvars:
+            for _src, vvar in stmt.src.src_and_vvars:
                 if vvar is not None:
                     if vvar.varid == true_stmt_dst.varid:
                         found_true_src_vvar = True

angr/analyses/decompiler/optimization_passes/lowered_switch_simplifier.py

@@ -557,7 +557,7 @@ class LoweredSwitchSimplifier(StructuringOptimizationPass):
                     varhash_to_caselists[v].append((cases, extra_cmp_nodes))
 
         for v, caselists in list(varhash_to_caselists.items()):
-            for idx, (cases, redundant_nodes) in list(enumerate(caselists)):
+            for idx, (cases, _redundant_nodes) in list(enumerate(caselists)):
                 # filter: each case value should only appear once
                 if len({case.value for case in cases}) != len(cases):
                     caselists[idx] = None

angr/analyses/decompiler/optimization_passes/return_duplicator_base.py

@@ -571,8 +571,7 @@ class ReturnDuplicatorBase:
                 new_name = stmt.name if stmt.name else f"Label_{stmt.ins_addr:x}"
                 if stmt.block_idx is not None:
                     suffix = f"__{stmt.block_idx}"
-                    if new_name.endswith(suffix):
-                        new_name = new_name[: -len(suffix)]
+                    new_name = new_name.removesuffix(suffix)
                 else:
                     new_name = stmt.name
                 new_name += f"__{block.idx}"

angr/analyses/decompiler/optimization_passes/stack_canary_simplifier.py

@@ -144,7 +144,7 @@ class StackCanarySimplifier(OptimizationPass):
                 nodes_to_process.append((pred, canary_check_stmt_idx, stack_chk_fail_caller, ret_node))
 
             # Awesome. Now patch this function.
-            for pred, canary_check_stmt_idx, stack_chk_fail_caller, ret_node in nodes_to_process:
+            for pred, _canary_check_stmt_idx, stack_chk_fail_caller, ret_node in nodes_to_process:
                 # Patch the pred so that it jumps to the one that is not stack_chk_fail_caller
                 pred_copy = pred.copy()
                 pred_copy.statements[-1] = ailment.Stmt.Jump(

angr/analyses/decompiler/sequence_walker.py

@@ -204,13 +204,17 @@ class SequenceWalker:
 
         new_false_node = self._handle(node.false_node, parent=node, index=1) if node.false_node is not None else None
 
-        if new_true_node is None and new_false_node is None:
+        new_condition = (
+            self._handle(node.condition, parent=node, label="condition") if node.condition is not None else None
+        )
+
+        if new_true_node is None and new_false_node is None and new_condition is None:
             return None
 
         return ConditionNode(
             node.addr,
             node.reaching_condition,
-            node.condition,
+            node.condition if new_condition is None else new_condition,
             node.true_node if new_true_node is None else new_true_node,
             false_node=node.false_node if new_false_node is None else new_false_node,
         )

angr/analyses/decompiler/ssailification/rewriting.py

@@ -40,6 +40,7 @@ class RewritingAnalysis(ForwardAnalysis[RewritingState, NodeType, object, object
         stackvar_locs: dict[int, int],
         rewrite_tmps: bool,
         ail_manager,
+        func_args: set[VirtualVariable],
         vvar_id_start: int = 0,
     ):
         self.project = project
@@ -55,6 +56,7 @@ class RewritingAnalysis(ForwardAnalysis[RewritingState, NodeType, object, object
         self._stackvar_locs = stackvar_locs
         self._rewrite_tmps = rewrite_tmps
         self._ail_manager = ail_manager
+        self._func_args = func_args
         self._engine_ail = SimEngineSSARewriting(
             self.project,
             sp_tracker=sp_tracker,
@@ -205,12 +207,20 @@ class RewritingAnalysis(ForwardAnalysis[RewritingState, NodeType, object, object
                 self.insert_phi_statements(node, phi_stmts)
 
     def _initial_abstract_state(self, node) -> RewritingState:
-        return RewritingState(
+        state = RewritingState(
             CodeLocation(node.addr, stmt_idx=0, ins_addr=node.addr, block_idx=node.idx),
             self.project.arch,
             self._function,
             node,
         )
+        # update state with function arguments
+        for func_arg in self._func_args:
+            if func_arg.oident[0] == VirtualVariableCategory.REGISTER:
+                reg_offset, reg_size = func_arg.oident[1], func_arg.size
+                state.registers[reg_offset][reg_size] = func_arg
+            elif func_arg.oident[0] == VirtualVariableCategory.STACK:
+                state.stackvars[func_arg.oident[1]][func_arg.size] = func_arg
+        return state
 
     def _run_on_node(self, node, state: RewritingState):
         """

angr/analyses/decompiler/ssailification/rewriting_engine.py

@@ -462,7 +462,7 @@ class SimEngineSSARewriting(
         base_mask = Const(self.ail_manager.next_atom(), None, base_mask, existing_vvar.bits)
         new_base_expr = BinaryOp(
             self.ail_manager.next_atom(),
-            "Or",
+            "And",
             [existing_vvar, base_mask],
             False,
             bits=existing_vvar.bits,
@@ -618,6 +618,15 @@ class SimEngineSSARewriting(
             ):
                 vvar = self.state.registers[reg_expr.reg_offset][reg_expr.size]
                 assert vvar is not None
+                if vvar.category == VirtualVariableCategory.PARAMETER:
+                    return VirtualVariable(
+                        reg_expr.idx,
+                        vvar.varid,
+                        vvar.bits,
+                        VirtualVariableCategory.PARAMETER,
+                        oident=vvar.oident,
+                        **vvar.tags,
+                    )
                 return VirtualVariable(
                     reg_expr.idx,
                     vvar.varid,
@@ -640,6 +649,20 @@ class SimEngineSSARewriting(
                             vvar,
                             **reg_expr.tags,
                         )
+                elif reg_expr.size > existing_size:
+                    # part of the variable exists... maybe it's a parameter?
+                    vvar = self.state.registers[reg_expr.reg_offset][existing_size]
+                    if vvar.category == VirtualVariableCategory.PARAMETER:
+                        # just zero-extend it
+                        return Convert(
+                            self.ail_manager.next_atom(),
+                            existing_size * self.project.arch.byte_width,
+                            reg_expr.size * self.project.arch.byte_width,
+                            False,
+                            vvar,
+                            **vvar.tags,
+                        )
+                    break
                 else:
                     break
 
@@ -651,24 +674,29 @@ class SimEngineSSARewriting(
             ins_addr=reg_expr.ins_addr,
         )
         # extract
-        shift_amount = Const(
-            self.ail_manager.next_atom(),
-            None,
-            (reg_expr.reg_offset - vvar.oident) * self.arch.byte_width,
-            8,
-            **reg_expr.tags,
-        )
-        shifted = BinaryOp(
-            self.ail_manager.next_atom(),
-            "Shr",
-            [
-                vvar,
-                shift_amount,
-            ],
-            False,
-            bits=vvar.bits,
-            **reg_expr.tags,
-        )
+        if reg_expr.reg_offset == vvar.oident:
+            shifted = vvar
+        else:
+            shift_amount = Const(
+                self.ail_manager.next_atom(),
+                None,
+                (reg_expr.reg_offset - vvar.oident) * self.arch.byte_width,
+                8,
+                **reg_expr.tags,
+            )
+            shifted = BinaryOp(
+                self.ail_manager.next_atom(),
+                "Shr",
+                [
+                    vvar,
+                    shift_amount,
+                ],
+                False,
+                bits=vvar.bits,
+                **reg_expr.tags,
+            )
+        if shifted.bits == reg_expr.bits:
+            return shifted
         return Convert(
             self.ail_manager.next_atom(),
             shifted.bits,
@@ -700,6 +728,15 @@ class SimEngineSSARewriting(
             # TODO: Support truncation
             # TODO: Maybe also support concatenation
             vvar = self.state.stackvars[expr.addr.offset][expr.size]
+            if vvar.category == VirtualVariableCategory.PARAMETER:
+                return VirtualVariable(
+                    expr.idx,
+                    vvar.varid,
+                    vvar.bits,
+                    VirtualVariableCategory.PARAMETER,
+                    oident=vvar.oident,
+                    **vvar.tags,
+                )
             return VirtualVariable(
                 expr.idx,
                 vvar.varid,

angr/analyses/decompiler/ssailification/ssailification.py

@@ -5,7 +5,7 @@ from collections import defaultdict
 from itertools import count
 from bisect import bisect_left
 
-from ailment.expression import Expression, Register, StackBaseOffset, Tmp
+from ailment.expression import Expression, Register, StackBaseOffset, Tmp, VirtualVariable, VirtualVariableCategory
 from ailment.statement import Statement, Store
 
 from angr.knowledge_plugins.functions import Function
@@ -34,6 +34,7 @@ class Ssailification(Analysis):  # pylint:disable=abstract-method
         ail_manager=None,
         ssa_stackvars: bool = False,
         ssa_tmps: bool = False,
+        func_args: set[VirtualVariable] | None = None,
         vvar_id_start: int = 0,
     ):
         """
@@ -53,6 +54,7 @@ class Ssailification(Analysis):  # pylint:disable=abstract-method
         self._ail_manager = ail_manager
         self._ssa_stackvars = ssa_stackvars
         self._ssa_tmps = ssa_tmps
+        self._func_args = func_args if func_args is not None else set()
         self._entry = (
             entry
             if entry is not None
@@ -71,6 +73,7 @@ class Ssailification(Analysis):  # pylint:disable=abstract-method
             bp_as_gpr,
             ssa_stackvars,
             ssa_tmps,
+            self._func_args,
         )
 
         # calculate virtual variables and phi nodes
@@ -91,6 +94,7 @@ class Ssailification(Analysis):  # pylint:disable=abstract-method
             self._stackvar_locs,
             self._ssa_tmps,
             self._ail_manager,
+            self._func_args,
             vvar_id_start=vvar_id_start,
         )
         self.out_graph = rewriter.out_graph
@@ -122,6 +126,11 @@ class Ssailification(Analysis):  # pylint:disable=abstract-method
             # for stack variables, we collect all definitions and identify stack variable locations using heuristics
 
             stackvar_locs = self._synthesize_stackvar_locs([def_ for def_, _ in def_to_loc if isinstance(def_, Store)])
+            # handle function arguments
+            if self._func_args:
+                for func_arg in self._func_args:
+                    if func_arg.oident[0] == VirtualVariableCategory.STACK:
+                        stackvar_locs[func_arg.oident[1]] = func_arg.size
             sorted_stackvar_offs = sorted(stackvar_locs)
         else:
             stackvar_locs = {}
@@ -137,9 +146,10 @@ class Ssailification(Analysis):  # pylint:disable=abstract-method
                 udef_to_defs[("reg", base_off, base_reg_bits)].add(def_)
                 udef_to_blockkeys[("reg", base_off, base_reg_bits)].add((loc.block_addr, loc.block_idx))
                 # add a definition for the partial register
-                if base_off != def_.reg_offset:
+                if base_off != def_.reg_offset or base_size != def_.size:
                     reg_bits = def_.size * self.project.arch.byte_width
-                    udef_to_defs[("reg", def_.reg_offset, reg_bits)].add((loc.block_addr, loc.block_idx))
+                    udef_to_defs[("reg", def_.reg_offset, reg_bits)].add(def_)
+                    udef_to_blockkeys[("reg", def_.reg_offset, reg_bits)].add((loc.block_addr, loc.block_idx))
             elif isinstance(def_, Store):
                 if isinstance(def_.addr, StackBaseOffset) and isinstance(def_.addr.offset, int):
                     idx_begin = bisect_left(sorted_stackvar_offs, def_.addr.offset)

angr/analyses/decompiler/ssailification/traversal.py

@@ -17,13 +17,24 @@ class TraversalAnalysis(ForwardAnalysis[TraversalState, ailment.Block, object, t
     TraversalAnalysis traverses the AIL graph and collects definitions.
     """
 
-    def __init__(self, project, func, ail_graph, sp_tracker, bp_as_gpr: bool, stackvars: bool, tmps: bool):
+    def __init__(
+        self,
+        project,
+        func,
+        ail_graph,
+        sp_tracker,
+        bp_as_gpr: bool,
+        stackvars: bool,
+        tmps: bool,
+        func_args: set[ailment.Expr.VirtualVariable],
+    ):
 
         self.project = project
         self._stackvars = stackvars
         self._tmps = tmps
         self._function = func
         self._graph_visitor = FunctionGraphVisitor(self._function, ail_graph)
+        self._func_args = func_args
 
         ForwardAnalysis.__init__(
             self, order_jobs=True, allow_merging=True, allow_widening=False, graph_visitor=self._graph_visitor
@@ -52,13 +63,28 @@ class TraversalAnalysis(ForwardAnalysis[TraversalState, ailment.Block, object, t
         pass
 
     def _initial_abstract_state(self, node: ailment.Block) -> TraversalState:
-        return TraversalState(self.project.arch, self._function)
+        state = TraversalState(self.project.arch, self._function)
+        # update it with function arguments
+        if self._func_args:
+            for func_arg in self._func_args:
+                if func_arg.oident[0] == ailment.Expr.VirtualVariableCategory.REGISTER:
+                    reg_offset = func_arg.oident[1]
+                    reg_size = func_arg.size
+                    state.live_registers.add(reg_offset)
+                    # get the full register if needed
+                    basereg_offset, basereg_size = self.project.arch.get_base_register(reg_offset, size=reg_size)
+                    if basereg_size != reg_size or basereg_offset != reg_offset:
+                        state.live_registers.add(basereg_offset)
+                elif func_arg.oident[0] == ailment.Expr.VirtualVariableCategory.STACK:
+                    state.live_stackvars.add((func_arg.oident[1], func_arg.size))
+        return state
 
     def _merge_states(self, node: ailment.Block, *states: TraversalState) -> tuple[TraversalState, bool]:
         merged_state = TraversalState(
             self.project.arch,
             self._function,
             live_registers=states[0].live_registers.copy(),
+            live_stackvars=states[0].live_stackvars.copy(),
         )
         merge_occurred = merged_state.merge(*states[1:])
         return merged_state, not merge_occurred

angr/analyses/decompiler/ssailification/traversal_state.py

@@ -37,7 +37,12 @@ class TraversalState:
                 merge_occurred = True
             all_regs |= o.live_registers
 
-        # TODO: merge of live_stackvars
+        all_stackvars: set[tuple[int, int]] = self.live_stackvars.copy()
+        for o in others:
+            if o.live_stackvars.difference(all_stackvars):
+                merge_occurred = True
+            all_stackvars |= o.live_stackvars
 
         self.live_registers = all_regs
+        self.live_stackvars = all_stackvars
         return merge_occurred

angr/analyses/decompiler/structured_codegen/c.py

@@ -679,14 +679,23 @@ class CStatements(CStatement):
     Represents a sequence of statements in C.
     """
 
-    __slots__ = ("statements",)
+    __slots__ = (
+        "addr",
+        "statements",
+    )
 
-    def __init__(self, statements, **kwargs):
+    def __init__(self, statements, addr=None, **kwargs):
         super().__init__(**kwargs)
 
         self.statements = statements
+        self.addr = addr
 
     def c_repr_chunks(self, indent=0, asexpr=False):
+        indent_str = self.indent_str(indent)
+        if self.codegen.display_block_addrs:
+            yield indent_str, None
+            yield f"/* Block {hex(self.addr) if self.addr is not None else 'unknown'} */", None
+            yield "\n", None
         for stmt in self.statements:
             yield from stmt.c_repr_chunks(indent=indent, asexpr=asexpr)
             if asexpr:
@@ -1572,15 +1581,19 @@ class CVariable(CExpression):
         "unified_variable",
         "variable",
         "variable_type",
+        "vvar_id",
     )
 
-    def __init__(self, variable: SimVariable, unified_variable=None, variable_type=None, tags=None, **kwargs):
+    def __init__(
+        self, variable: SimVariable, unified_variable=None, variable_type=None, tags=None, vvar_id=None, **kwargs
+    ):
         super().__init__(**kwargs)
 
         self.variable: SimVariable = variable
         self.unified_variable: SimVariable | None = unified_variable
         self.variable_type: SimType = variable_type.with_arch(self.codegen.project.arch)
         self.tags = tags
+        self.vvar_id = vvar_id
 
     @property
     def type(self):
@@ -1598,6 +1611,8 @@ class CVariable(CExpression):
 
     def c_repr_chunks(self, indent=0, asexpr=False):
         yield self.name, self
+        if self.codegen.display_vvar_ids:
+            yield f"<vvar_{self.vvar_id}>", self
 
 
 class CIndexedVariable(CExpression):
@@ -2141,7 +2156,8 @@ class CConstant(CExpression):
         result = self.fmt.get("neg", None)
         if result is None:
             result = False
-            if isinstance(self.value, int):
+            # guess it
+            if isinstance(self._type, (SimTypeInt, SimTypeChar)) and self._type.signed and isinstance(self.value, int):
                 value_size = self._type.size if self._type is not None else None
                 if (value_size == 32 and 0xF000_0000 <= self.value <= 0xFFFF_FFFF) or (
                     value_size == 64 and 0xF000_0000_0000_0000 <= self.value <= 0xFFFF_FFFF_FFFF_FFFF
@@ -2486,6 +2502,8 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
         simplify_else_scope=True,
         cstyle_ifs=True,
         omit_func_header=False,
+        display_block_addrs=False,
+        display_vvar_ids=False,
     ):
         super().__init__(flavor=flavor)
 
@@ -2558,6 +2576,8 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
         self.simplify_else_scope = simplify_else_scope
         self.cstyle_ifs = cstyle_ifs
         self.omit_func_header = omit_func_header
+        self.display_block_addrs = display_block_addrs
+        self.display_vvar_ids = display_vvar_ids
         self.text = None
         self.map_pos_to_node = None
         self.map_pos_to_addr = None
@@ -2740,7 +2760,7 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
             return _mapping.get(n)(signed=signed).with_arch(self.project.arch)
         return SimTypeNum(n, signed=signed).with_arch(self.project.arch)
 
-    def _variable(self, variable: SimVariable, fallback_type_size: int | None) -> CVariable:
+    def _variable(self, variable: SimVariable, fallback_type_size: int | None, vvar_id: int | None = None) -> CVariable:
         # TODO: we need to fucking make sure that variable recovery and type inference actually generates a size
         # TODO: for each variable it links into the fucking ail. then we can remove fallback_type_size.
         unified = self._variable_kb.variables[self._func.addr].unified_variable(variable)
@@ -2751,7 +2771,7 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
             variable_type = self.default_simtype_from_bits(
                 (fallback_type_size or self.project.arch.bytes) * self.project.arch.byte_width
             )
-        cvar = CVariable(variable, unified_variable=unified, variable_type=variable_type, codegen=self)
+        cvar = CVariable(variable, unified_variable=unified, variable_type=variable_type, codegen=self, vvar_id=vvar_id)
         self._variables_in_use[variable] = cvar
         return cvar
 
@@ -3106,14 +3126,18 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
     # Handlers
     #
 
-    def _handle(self, node, is_expr: bool = True, lvalue: bool = False):
+    def _handle(self, node, is_expr: bool = True, lvalue: bool = False, likely_signed=False):
         if (node, is_expr) in self.ailexpr2cnode:
             return self.ailexpr2cnode[(node, is_expr)]
 
         handler: Callable | None = self._handlers.get(node.__class__, None)
         if handler is not None:
             # special case for Call
-            converted = handler(node, is_expr=is_expr) if isinstance(node, Stmt.Call) else handler(node, lvalue=lvalue)
+            converted = (
+                handler(node, is_expr=is_expr)
+                if isinstance(node, Stmt.Call)
+                else handler(node, lvalue=lvalue, likely_signed=likely_signed)
+            )
             self.ailexpr2cnode[(node, is_expr)] = converted
             return converted
         raise UnsupportedNodeTypeError(f"Node type {type(node)} is not supported yet.")
@@ -3127,10 +3151,7 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
         for node in seq.nodes:
             lines.append(self._handle(node, is_expr=False))
 
-        if not lines:
-            return CStatements([], codegen=None)
-
-        return CStatements(lines, codegen=self) if len(lines) > 1 else lines[0]
+        return lines[0] if len(lines) == 1 else CStatements(lines, codegen=self, addr=seq.addr)
 
     def _handle_Loop(self, loop_node, **kwargs):
         tags = {"ins_addr": loop_node.addr}
@@ -3217,7 +3238,7 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
             r = self._handle(n, is_expr=False)
             lines.append(r)
 
-        return CStatements(lines, codegen=self) if len(lines) > 1 else lines[0]
+        return lines[0] if len(lines) == 1 else CStatements(lines, codegen=self, addr=node.addr)
 
     def _handle_SwitchCase(self, node, **kwargs):
         """
@@ -3260,7 +3281,7 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
                 cstmt = CUnsupportedStatement(stmt, codegen=self)
             cstmts.append(cstmt)
 
-        return CStatements(cstmts, codegen=self)
+        return CStatements(cstmts, codegen=self, addr=node.addr)
 
     #
     # AIL statement handlers
@@ -3315,9 +3336,9 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
             if stmt.dst.variable is not None:
                 if "struct_member_info" in stmt.dst.tags:
                     offset, var, _ = stmt.dst.struct_member_info
-                    cvar = self._variable(var, stmt.dst.size)
+                    cvar = self._variable(var, stmt.dst.size, vvar_id=stmt.dst.varid)
                 else:
-                    cvar = self._variable(stmt.dst.variable, stmt.dst.size)
+                    cvar = self._variable(stmt.dst.variable, stmt.dst.size, vvar_id=stmt.dst.varid)
                     offset = stmt.dst.variable_offset or 0
                 assert type(offset) is int  # I refuse to deal with the alternative
 
@@ -3474,7 +3495,9 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
         l.warning("FIXME: Leftover Tmp expressions are found.")
         return self._variable(SimTemporaryVariable(expr.tmp_idx, expr.bits), expr.size)
 
-    def _handle_Expr_Const(self, expr: Expr.Const, type_=None, reference_values=None, variable=None, **kwargs):
+    def _handle_Expr_Const(
+        self, expr: Expr.Const, type_=None, reference_values=None, variable=None, likely_signed=True, **kwargs
+    ):
         inline_string = False
         function_pointer = False
 
@@ -3550,8 +3573,8 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
                             inline_string = True
 
         if type_ is None:
-            # default to int
-            type_ = self.default_simtype_from_bits(expr.bits)
+            # default to int or unsigned int, determined by likely_signed
+            type_ = self.default_simtype_from_bits(expr.bits, signed=likely_signed)
 
         if variable is None and hasattr(expr, "reference_variable") and expr.reference_variable is not None:
             variable = expr.reference_variable
@@ -3583,7 +3606,7 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
             )
 
         lhs = self._handle(expr.operands[0])
-        rhs = self._handle(expr.operands[1])
+        rhs = self._handle(expr.operands[1], likely_signed=expr.op not in {"And", "Or"})
 
         return CBinaryOp(
             expr.op,
@@ -3679,7 +3702,7 @@ class CStructuredCodeGenerator(BaseStructuredCodeGenerator, Analysis):
 
     def _handle_VirtualVariable(self, expr: Expr.VirtualVariable, **kwargs):
         if expr.variable:
-            cvar = self._variable(expr.variable, None)
+            cvar = self._variable(expr.variable, None, vvar_id=expr.varid)
             if expr.variable.size != expr.size:
                 l.warning(
                     "VirtualVariable size (%d) and variable size (%d) do not match. Force a type cast.",