angr 9.2.135__py3-none-macosx_11_0_arm64.whl → 9.2.137__py3-none-macosx_11_0_arm64.whl

angr/state_plugins/callstack.py

@@ -1,11 +1,13 @@
 from __future__ import annotations
+
 import collections
-from itertools import dropwhile
 import logging
 from collections.abc import Iterator
+from itertools import dropwhile
 
-from .plugin import SimStatePlugin
 from angr.errors import AngrError, SimEmptyCallStackError
+from angr.sim_state import SimState
+from .plugin import SimStatePlugin
 
 l = logging.getLogger(name=__name__)
 
@@ -393,6 +395,4 @@ class CallStackAction:
         return f"<CallStackAction pop, ret site {self.ret_site_addr:#x}>"
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("callstack", CallStack)

angr/state_plugins/cgc.py

@@ -1,5 +1,8 @@
 from __future__ import annotations
+
 import operator
+
+from angr.sim_state import SimState
 from .plugin import SimStatePlugin
 
 
@@ -149,6 +152,4 @@ class SimStateCGC(SimStatePlugin):
         self.sinkholes.add((address, length))
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("cgc", SimStateCGC)

angr/state_plugins/gdb.py

@@ -1,12 +1,15 @@
 from __future__ import annotations
+
+import binascii
+import logging
 import os
 import re
-import logging
+
 import claripy
-import binascii
 
-from .plugin import SimStatePlugin
 from angr.errors import SimStateError
+from angr.sim_state import SimState
+from .plugin import SimStatePlugin
 
 l = logging.getLogger(name=__name__)
 
@@ -142,6 +145,4 @@ class GDB(SimStatePlugin):
         return GDB()
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("gdb", GDB)

angr/state_plugins/globals.py

@@ -1,6 +1,7 @@
 from __future__ import annotations
 import logging
 
+from angr.sim_state import SimState
 from .plugin import SimStatePlugin
 
 l = logging.getLogger(name=__name__)
@@ -61,6 +62,4 @@ class SimStateGlobals(SimStatePlugin):
         return SimStateGlobals(dict(self._backer))
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("globals", SimStateGlobals)

angr/state_plugins/heap/heap_brk.py

@@ -4,6 +4,7 @@ import logging
 import claripy
 
 from angr.errors import SimSolverError
+from angr.sim_state import SimState
 from angr.state_plugins.plugin import SimStatePlugin
 from . import SimHeapBase
 
@@ -132,6 +133,4 @@ class SimHeapBrk(SimHeapBase):
         return self._combine(others)
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("heap", SimHeapBrk)

angr/state_plugins/history.py

@@ -1,16 +1,19 @@
 from __future__ import annotations
-from collections.abc import Reversible
-import operator
-import logging
-import itertools
+
 import contextlib
+import itertools
+import logging
+import operator
+from collections.abc import Reversible
 
 import claripy
-from claripy.ast.bv import BV
 
-from .plugin import SimStatePlugin
 from angr import sim_options
+from angr.sim_state import SimState
 from angr.state_plugins.sim_action import SimActionObject
+from .plugin import SimStatePlugin
+from .sim_action import SimAction, SimActionConstraint
+from .sim_event import SimEvent
 
 l = logging.getLogger(name=__name__)
 
@@ -41,7 +44,7 @@ class SimStateHistory(SimStatePlugin):
         self.jump_target = None if clone is None else clone.jump_target
         self.jump_source = None if clone is None else clone.jump_source
         self.jump_avoidable = None if clone is None else clone.jump_avoidable
-        self.jump_guard: BV | None = None if clone is None else clone.jump_guard
+        self.jump_guard: claripy.ast.BV | None = None if clone is None else clone.jump_guard
         self.jumpkind: str | None = None if clone is None else clone.jumpkind
 
         # the execution log for this history
@@ -542,9 +545,4 @@ class LambdaIterIter(LambdaAttrIter):
             yield from reversed(self._f(hist)) if self._reverse else self._f(hist)
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("history", SimStateHistory)
-
-from .sim_action import SimAction, SimActionConstraint
-from .sim_event import SimEvent

angr/state_plugins/inspect.py

@@ -3,6 +3,9 @@ from __future__ import annotations
 
 import logging
 
+from angr.sim_state import SimState
+from .plugin import SimStatePlugin
+
 l = logging.getLogger(name=__name__)
 
 event_types = {
@@ -224,9 +227,6 @@ class BP:
         )
 
 
-from .plugin import SimStatePlugin
-
-
 class SimInspector(SimStatePlugin):
     """
     The breakpoint interface, used to instrument execution. For usage information, look here:
@@ -372,6 +372,4 @@ class SimInspector(SimStatePlugin):
         state.supports_inspect = True
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("inspect", SimInspector)

angr/state_plugins/libc.py

@@ -1,4 +1,6 @@
 from __future__ import annotations
+
+from angr.sim_state import SimState
 from .plugin import SimStatePlugin
 
 
@@ -1258,6 +1260,4 @@ class SimStateLibc(SimStatePlugin):
         return -1
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("libc", SimStateLibc)

angr/state_plugins/log.py

@@ -1,11 +1,16 @@
 from __future__ import annotations
-import logging
-
-l = logging.getLogger(name=__name__)
 
 import itertools
+import logging
 
+from angr.errors import SimEventError
+from angr.sim_state import SimState
 from .plugin import SimStatePlugin
+from .sim_event import SimEvent
+from .sim_action import SimAction, SimActionConstraint
+
+
+l = logging.getLogger(name=__name__)
 
 
 class SimStateLog(SimStatePlugin):
@@ -76,11 +81,4 @@ class SimStateLog(SimStatePlugin):
         # self.input_variables.clear()
 
 
-from angr.errors import SimEventError
-from .sim_event import SimEvent
-from .sim_action import SimAction, SimActionConstraint
-
-
-from angr.sim_state import SimState
-
 SimState.register_default("log", SimStateLog)

angr/state_plugins/loop_data.py

@@ -3,6 +3,7 @@ import logging
 import copy
 from collections import defaultdict
 
+from angr.sim_state import SimState
 from .plugin import SimStatePlugin
 
 
@@ -88,6 +89,4 @@ class SimStateLoopData(SimStatePlugin):
         )
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("loop_data", SimStateLoopData)

angr/state_plugins/posix.py

@@ -1,12 +1,16 @@
 from __future__ import annotations
+
 import logging
 
 import claripy
 
-from .plugin import SimStatePlugin
-from .filesystem import SimMount, Stat
-from angr.storage.file import SimFile, SimPacketsStream, Flags, SimFileDescriptor, SimFileDescriptorDuplex
 from angr import sim_options as options
+from angr.errors import SimPosixError, SimSolverError, SimMergeError, SimMemoryError
+from angr.sim_state import SimState
+from angr.storage.file import SimFile, SimPacketsStream, Flags, SimFileDescriptor, SimFileDescriptorDuplex
+from .filesystem import SimMount, Stat
+from .plugin import SimStatePlugin
+
 
 l = logging.getLogger(name=__name__)
 
@@ -696,8 +700,4 @@ class SimSystemPosix(SimStatePlugin):
         return self.get_fd(fd).concretize(**kwargs)
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("posix", SimSystemPosix)
-
-from angr.errors import SimPosixError, SimSolverError, SimMergeError, SimMemoryError

angr/state_plugins/preconstrainer.py

@@ -3,9 +3,10 @@ import logging
 
 import claripy
 
-from .plugin import SimStatePlugin
 from angr import sim_options as o
 from angr.errors import AngrError
+from angr.sim_state import SimState
+from .plugin import SimStatePlugin
 
 
 l = logging.getLogger(name=__name__)
@@ -192,6 +193,4 @@ class SimStatePreconstrainer(SimStatePlugin):
                         l.warning("var %s not found in self.variable_map", var)
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("preconstrainer", SimStatePreconstrainer)

angr/state_plugins/scratch.py

@@ -3,7 +3,12 @@ import logging
 
 import claripy
 
+from angr import sim_options as o
+from angr.errors import SimValueError, SimMissingTempError
+from angr.sim_state import SimState
+from .inspect import BP_AFTER, BP_BEFORE
 from .plugin import SimStatePlugin
+from .sim_action import SimActionObject, SimActionData
 
 
 l = logging.getLogger(name=__name__)
@@ -165,12 +170,4 @@ class SimStateScratch(SimStatePlugin):
         self.jumpkind = j  # preserve jumpkind - "what is the previous jumpkind" is an important question sometimes
 
 
-# pylint:disable=wrong-import-position
-from .sim_action import SimActionObject, SimActionData
-from angr.errors import SimValueError, SimMissingTempError
-from angr import sim_options as o
-from .inspect import BP_AFTER, BP_BEFORE
-
-from angr.sim_state import SimState
-
 SimState.register_default("scratch", SimStateScratch)

angr/state_plugins/sim_action.py

@@ -1,15 +1,15 @@
 # This module contains data structures for handling memory, code, and register references.
 from __future__ import annotations
 
+import contextlib
 import logging
 
+from .sim_event import SimEvent
+
 l = logging.getLogger(name=__name__)
 
 _noneset = frozenset()
 
-from .sim_event import SimEvent
-import contextlib
-
 
 class SimAction(SimEvent):
     """

angr/state_plugins/solver.py

@@ -373,7 +373,7 @@ class SimSolver(SimStatePlugin):
         max=None,
         stride=None,
         uninitialized=False,
-        explicit_name=None,
+        explicit_name=False,
         key=None,
         eternal=False,
         inspect=True,
@@ -408,18 +408,23 @@ class SimSolver(SimStatePlugin):
         if key is not None and eternal and key in self.eternal_tracked_variables:
             r = self.eternal_tracked_variables[key]
             # pylint: disable=too-many-boolean-expressions
-            if size != r.length or uninitialized != r.uninitialized or bool(explicit_name) ^ (r.args[0] == name):
+            if (
+                size != r.length
+                or uninitialized != r.has_annotation_type(claripy.annotation.UninitializedAnnotation)
+                or bool(explicit_name) ^ (r.args[0] == name)
+            ):
                 l.warning("Variable %s being retrieved with different settings than it was tracked with", name)
         else:
             r = claripy.BVS(
                 name,
                 size,
-                uninitialized=uninitialized,
                 explicit_name=explicit_name,
                 **kwargs,
             )
             if any(x is not None for x in (min, max, stride)):
                 r = r.annotate(claripy.annotation.StridedIntervalAnnotation(stride, min, max))
+            if uninitialized:
+                r = r.annotate(claripy.annotation.UninitializedAnnotation())
             if key is not None:
                 self.register_variable(r, key, eternal)
 

angr/state_plugins/symbolizer.py

@@ -1,10 +1,13 @@
 from __future__ import annotations
+
 import logging
-import claripy
 import struct
 
-from .plugin import SimStatePlugin
+import claripy
+
+from angr.sim_state import SimState
 from angr.storage.memory_mixins import PagedMemoryMixin
+from .plugin import SimStatePlugin
 
 
 l = logging.getLogger(name=__name__)
@@ -285,6 +288,4 @@ class SimSymbolizer(SimStatePlugin):  # pylint:disable=abstract-method
         return sc
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("symbolizer", SimSymbolizer)

angr/state_plugins/uc_manager.py

@@ -3,8 +3,10 @@ import logging
 
 import claripy
 
-from .plugin import SimStatePlugin
 from angr.errors import SimUCManagerAllocationError
+from angr.sim_state import SimState
+from .plugin import SimStatePlugin
+
 
 l = logging.getLogger(name=__name__)
 
@@ -89,6 +91,4 @@ class SimUCManager(SimStatePlugin):
         self._region_base = 0xD0 << (self.state.arch.bits - 8)
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("uc_manager", SimUCManager)

angr/state_plugins/unicorn_engine.py

@@ -990,7 +990,11 @@ class Unicorn(SimStatePlugin):
         :param from_where: the ID of the memory region it comes from ('mem' or 'reg')
         :returns: the value to be inserted into Unicorn, or None
         """
-        if len(d.annotations):
+        allowed_annotations = (claripy.annotation.UninitializedAnnotation,)
+        filtered_annotations = [
+            a for a in d.annotations if not isinstance(a, allowed_annotations) and not a.eliminatable
+        ]
+        if len(filtered_annotations) > 0:
             l.debug("Blocking annotated AST.")
             return None
         if not d.symbolic:

angr/state_plugins/view.py

@@ -6,6 +6,9 @@ from typing import ClassVar, TYPE_CHECKING
 import claripy
 from archinfo.arch_soot import ArchSoot, SootAddressDescriptor
 from archinfo.arch_arm import is_arm_arch
+
+from angr.sim_state import SimState
+from angr.sim_type import ALL_TYPES, SimTypeFixedSizeArray, SimTypePointer
 from .plugin import SimStatePlugin
 
 if TYPE_CHECKING:
@@ -331,12 +334,7 @@ class StructMode:
             self.__getattr__(k).store(v)
 
 
-from angr.sim_type import ALL_TYPES, SimTypeFixedSizeArray, SimTypePointer
-
 SimMemView.types = ALL_TYPES  # identity purposefully here
 
-
-from angr.sim_state import SimState
-
 SimState.register_default("mem", SimMemView)
 SimState.register_default("regs", SimRegNameView)

angr/storage/file.py

@@ -4,10 +4,11 @@ import itertools
 
 import claripy
 
-from .memory_mixins import DefaultMemory
+from angr import sim_options
+from angr.errors import SimMergeError, SimFileError, SimSolverError
 from angr.state_plugins.plugin import SimStatePlugin
 from angr.state_plugins.sim_action_object import SimActionObject
-from angr import sim_options
+from .memory_mixins import DefaultMemory
 
 l = logging.getLogger(name=__name__)
 
@@ -1207,6 +1208,3 @@ class SimPacketsSlots(SimFileBase):
 
     def widen(self, _):
         raise SimMergeError("Widening the filesystem is unsupported")
-
-
-from angr.errors import SimMergeError, SimFileError, SimSolverError

angr/storage/memory_mixins/address_concretization_mixin.py

@@ -20,9 +20,9 @@ class MultiwriteAnnotation(claripy.Annotation):
         return True
 
 
-def _multiwrite_filter(mem, ast):  # pylint:disable=unused-argument
+def _multiwrite_filter(mem, ast: claripy.ast.Base):  # pylint:disable=unused-argument
     # this is a huge hack, but so is the whole multiwrite crap
-    return any(isinstance(a, MultiwriteAnnotation) for a in ast._uneliminatable_annotations)
+    return ast.has_annotation_type(MultiwriteAnnotation)
 
 
 SimStateOptions.register_option(

angr/storage/memory_mixins/bvv_conversion_mixin.py

@@ -1,7 +1,10 @@
 from __future__ import annotations
+
 import logging
+
 import claripy
 
+from angr.errors import SimMemoryError
 from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
 l = logging.getLogger(__name__)
@@ -68,6 +71,3 @@ class DataNormalizationMixin(MemoryMixin):
             raise TypeError("Bad value passed to memory", thing) from None
         else:
             return raw_to_bv()
-
-
-from angr.errors import SimMemoryError

angr/storage/memory_mixins/clouseau_mixin.py

@@ -1,5 +1,6 @@
 from __future__ import annotations
 
+from angr.state_plugins.inspect import BP_BEFORE, BP_AFTER
 from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
 
@@ -128,6 +129,3 @@ class InspectMixinHigh(MemoryMixin):
             add_constraints = self.state._inspect_getattr("address_concretization_add_constraints", add_constraints)
 
         super()._add_constraints(c, add_constraints=add_constraints, inspect=inspect, **kwargs)
-
-
-from angr.state_plugins.inspect import BP_BEFORE, BP_AFTER

angr/storage/memory_mixins/name_resolution_mixin.py

@@ -3,6 +3,7 @@ from __future__ import annotations
 import claripy
 from archinfo.arch_arm import is_arm_arch
 
+from angr.errors import SimMemoryError
 from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
 stn_map = {f"st{n}": n for n in range(8)}
@@ -64,6 +65,3 @@ class NameResolutionMixin(MemoryMixin):
             named_addr, named_size = self._resolve_location_name(addr, is_write=False)
             return super().load(named_addr, size=named_size if size is None else size, **kwargs)
         return super().load(addr, size=size, **kwargs)
-
-
-from angr.errors import SimMemoryError

angr/storage/memory_mixins/paged_memory/paged_memory_mixin.py

@@ -1,16 +1,17 @@
 from __future__ import annotations
-import cffi
-from typing import Any, Generic, Literal, overload
-from collections.abc import Iterable
+
 import logging
 from collections import defaultdict
+from collections.abc import Iterable
+from typing import Any, Generic, Literal, overload
 
+import cffi
 import claripy
 
+from angr.errors import SimMemoryError
 from angr.state_plugins.sim_action_object import SimActionObject
 from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 from angr.storage.memory_mixins.paged_memory.pages import PageType, ListPage, UltraPage, MVListPage
-from angr.errors import SimMemoryError
 
 # yeet
 ffi = cffi.FFI()
@@ -107,7 +108,12 @@ class PagedMemoryMixin(
                     permissions = perms
                     break
 
-        return dict(memory=self, memory_id=f"{self.id}_{pageno}", permissions=permissions, **self._extra_page_kwargs)
+        return {
+            "memory": self,
+            "memory_id": f"{self.id}_{pageno}",
+            "permissions": permissions,
+            **self._extra_page_kwargs,
+        }
 
     def _divide_addr(self, addr: int) -> tuple[int, int]:
         return divmod(addr, self.page_size)
@@ -498,11 +504,7 @@ class PagedMemoryMixin(
 
         # everything from here on out has exactly one goal: to maximize the amount of concrete data
         # we can return (up to the limit!)
-        for i, byte in enumerate(bitmap):
-            if byte != 0:
-                break
-        else:
-            i = len(bitmap)
+        i = next((i for i, byte in enumerate(bitmap) if byte != 0), len(bitmap))
 
         if i != subsize:
             return data[:i]
@@ -523,11 +525,7 @@ class PagedMemoryMixin(
                 break
             else:
                 newdata, bitmap = concrete_load(offset, subsize, with_bitmap=True, **kwargs)
-                for i, byte in enumerate(bitmap):
-                    if byte != 0:
-                        break
-                else:
-                    i = len(bitmap)
+                i = next((i for i, byte in enumerate(bitmap) if byte != 0), len(bitmap))
 
                 # magic: check if the memory regions are physically adjacent
                 if physically_adjacent and ffi.cast(ffi.BVoidP, ffi.from_buffer(data)) + len(data) == ffi.cast(

angr/storage/memory_mixins/paged_memory/pages/__init__.py

@@ -1,32 +1,11 @@
 from __future__ import annotations
-import typing
 
-from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 from .cooperation import CooperationBase, MemoryObjectMixin
 from .ispo_mixin import ISPOMixin
 from .refcount_mixin import RefcountMixin
 from .permissions_mixin import PermissionsMixin
 from .history_tracking_mixin import HistoryTrackingMixin
-
-
-class PageBase(HistoryTrackingMixin, RefcountMixin, CooperationBase, ISPOMixin, PermissionsMixin, MemoryMixin):
-    """
-    This is a fairly succinct definition of the contract between PagedMemoryMixin and its constituent pages:
-
-    - Pages must implement the MemoryMixin model for loads, stores, copying, merging, etc
-    - However, loading/storing may not necessarily use the same data domain as PagedMemoryMixin. In order to do more
-      efficient loads/stores across pages, we use the CooperationBase interface which allows the page class to
-      determine how to generate and unwrap the objects which are actually stored.
-    - To support COW, we use the RefcountMixin and the ISPOMixin (which adds the contract element that ``memory=self``
-      be passed to every method call)
-    - Pages have permissions associated with them, stored in the PermissionsMixin.
-
-    Read the docstrings for each of the constituent classes to understand the nuances of their functionalities
-    """
-
-
-PageType = typing.TypeVar("PageType", bound=PageBase)
-
+from .base import PageBase, PageType
 from .list_page import ListPage
 from .mv_list_page import MVListPage
 from .ultra_page import UltraPage

angr/storage/memory_mixins/paged_memory/pages/base.py

@@ -0,0 +1,31 @@
+from __future__ import annotations
+
+import typing
+
+from angr.storage.memory_mixins.memory_mixin import MemoryMixin
+from .cooperation import CooperationBase
+from .ispo_mixin import ISPOMixin
+from .refcount_mixin import RefcountMixin
+from .permissions_mixin import PermissionsMixin
+from .history_tracking_mixin import HistoryTrackingMixin
+
+
+class PageBase(HistoryTrackingMixin, RefcountMixin, CooperationBase, ISPOMixin, PermissionsMixin, MemoryMixin):
+    """
+    This is a fairly succinct definition of the contract between PagedMemoryMixin and its constituent pages:
+
+    - Pages must implement the MemoryMixin model for loads, stores, copying, merging, etc
+    - However, loading/storing may not necessarily use the same data domain as PagedMemoryMixin. In order to do more
+      efficient loads/stores across pages, we use the CooperationBase interface which allows the page class to
+      determine how to generate and unwrap the objects which are actually stored.
+    - To support COW, we use the RefcountMixin and the ISPOMixin (which adds the contract element that ``memory=self``
+      be passed to every method call)
+    - Pages have permissions associated with them, stored in the PermissionsMixin.
+
+    Read the docstrings for each of the constituent classes to understand the nuances of their functionalities
+    """
+
+
+PageType = typing.TypeVar("PageType", bound=PageBase)
+
+__all__ = ("PageBase", "PageType")

angr/storage/memory_mixins/paged_memory/pages/list_page.py

@@ -6,7 +6,7 @@ import claripy
 
 from angr.utils.dynamic_dictlist import DynamicDictList
 from angr.storage.memory_object import SimMemoryObject, SimLabeledMemoryObject
-from . import PageBase
+from .base import PageBase
 from .cooperation import MemoryObjectMixin
 
 

angr/storage/memory_mixins/paged_memory/pages/mv_list_page.py

@@ -7,7 +7,7 @@ from collections.abc import Callable
 from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 from angr.utils.dynamic_dictlist import DynamicDictList
 from angr.storage.memory_object import SimMemoryObject, SimLabeledMemoryObject
-from . import PageBase
+from .base import PageBase
 from .cooperation import MemoryObjectSetMixin