angr 9.2.132__py3-none-win_amd64.whl → 9.2.133__py3-none-win_amd64.whl

angr/procedures/definitions/linux_kernel.py

@@ -1,6 +1,5 @@
 from __future__ import annotations
 import logging
-from typing import Dict
 
 from angr.sim_type import SimTypeFunction, SimTypePointer, SimTypeLong, SimStruct, SimTypeInt, SimTypeChar, SimTypeBottom, SimTypeFd, SimTypeLongLong
 from angr.procedures import SIM_PROCEDURES as P

angr/procedures/definitions/parse_syscalls_from_local_system.py

@@ -26,7 +26,7 @@ def parse_unistd_include_header(header_path):
 def dump_mapping(abi, mapping):
     print(f'\nlib.add_number_mapping_from_dict("{abi}", {{')
     for num in sorted(mapping):
-        print('    %d: "%s",' % (num, mapping[num]))
+        print(f'    {num}: "{mapping[num]}",')
     print('})')
 
 def main():

angr/procedures/definitions/parse_win32json.py

@@ -1,7 +1,6 @@
 # Based on https://github.com/dfraze/binja_winmd/blob/main/main.py. Thank you, Dustin Fraze!
 from __future__ import annotations
 
-from typing import Set
 import json
 import codecs
 import sys

angr/procedures/ntdll/exceptions.py

@@ -44,7 +44,7 @@ class KiUserExceptionDispatcher(angr.SimProcedure):
             elif disposition == 3:
                 raise angr.errors.SimUnsupportedError("Exception disposition ExceptionCollidedUnwind is unsupported")
             else:
-                raise angr.errors.SimError("Bad exception disposition %d" % disposition)
+                raise angr.errors.SimError(f"Bad exception disposition {disposition}")
 
         # todo: check cur_ptr against stack bounds
         cur_ptr = self.cur_ptr

angr/procedures/stubs/format_parser.py

@@ -323,11 +323,11 @@ class FormatSpecifier:
     """
 
     __slots__ = (
-        "string",
-        "size",
-        "signed",
         "length_spec",
         "pad_chr",
+        "signed",
+        "size",
+        "string",
     )
 
     def __init__(self, string, length_spec, pad_chr, size, signed):

angr/procedures/win32/dynamic_loading.py

@@ -59,7 +59,7 @@ class GetProcAddress(angr.SimProcedure):
         if claripy.is_true(name_addr < 0x10000):
             # this matches the bogus name specified in the loader...
             ordinal = self.state.solver.eval(name_addr)
-            name = "ordinal.%d.%s" % (ordinal, obj.provides)
+            name = f"ordinal.{ordinal}.{obj.provides}"
         else:
             name = self.state.mem[name_addr].string.concrete.decode("utf-8")
 

angr/protos/__init__.py

@@ -14,9 +14,9 @@ from . import xrefs_pb2
 from . import variables_pb2
 
 __all__ = (
-    "primitives_pb2",
-    "function_pb2",
     "cfg_pb2",
-    "xrefs_pb2",
+    "function_pb2",
+    "primitives_pb2",
     "variables_pb2",
+    "xrefs_pb2",
 )

angr/sim_manager.py

@@ -155,10 +155,10 @@ class SimulationManager:
                 self.use_technique(t)
 
     def __repr__(self):
-        stashes_repr = ", ".join(("%d %s" % (len(v), k)) for k, v in self._stashes.items() if len(v) != 0)
+        stashes_repr = ", ".join((f"{len(v)} {k}") for k, v in self._stashes.items() if len(v) != 0)
         if not stashes_repr:
             stashes_repr = "all stashes empty"
-        errored_repr = " (%d errored)" % len(self.errored) if self.errored else ""
+        errored_repr = f" ({len(self.errored)} errored)" if self.errored else ""
         return f"<SimulationManager with {stashes_repr}{errored_repr}>"
 
     def __getattr__(self, item):

angr/sim_state.py

@@ -598,7 +598,7 @@ class SimState(Generic[IPTypeConc, IPTypeSym], PluginHub[SimStatePlugin]):
 
         if merge_conditions is None:
             # TODO: maybe make the length of this smaller? Maybe: math.ceil(math.log(len(others)+1, 2))
-            merge_flag = claripy.BVS("state_merge_%d" % next(merge_counter), 16)
+            merge_flag = claripy.BVS(f"state_merge_{next(merge_counter)}", 16)
             merge_values = range(len(others) + 1)
             merge_conditions = [merge_flag == b for b in merge_values]
         else:

angr/sim_state_options.py

@@ -11,11 +11,11 @@ class StateOption:
     """
 
     __slots__ = (
-        "name",
-        "types",
+        "_one_type",
         "default",
         "description",
-        "_one_type",
+        "name",
+        "types",
     )
 
     def __init__(self, name, types, default=_NO_DEFAULT_VALUE, description=None):

angr/sim_type.py

@@ -428,7 +428,7 @@ class SimTypeInt(SimTypeReg):
             name = "unsigned " + name
 
         try:
-            return name + " (%d bits)" % self.size
+            return f"{name} ({self.size} bits)"
         except ValueError:
             return name
 
@@ -516,7 +516,7 @@ class SimTypeFixedSizeInt(SimTypeInt):
             name = "u" + name
 
         try:
-            return name + " (%d bits)" % self.size
+            return f"{name} ({self.size} bits)"
         except ValueError:
             return name
 
@@ -778,12 +778,8 @@ class SimTypePointer(SimTypeReg):
         return out
 
     def _init_str(self):
-        return "%s(%s%s, offset=%d)" % (
-            self.__class__.__name__,
-            self.pts_to._init_str(),
-            (f', label="{self.label}"') if self.label is not None else "",
-            self.offset,
-        )
+        label_str = f', label="{self.label}"' if self.label is not None else ""
+        return f"{self.__class__.__name__}({self.pts_to._init_str()}{label_str}, offset={self.offset})"
 
     def copy(self):
         return SimTypePointer(self.pts_to, label=self.label, offset=self.offset)
@@ -1282,7 +1278,7 @@ class SimTypeLength(SimTypeLong):
         return self._arch.bits
 
     def _init_str(self):
-        return "%s(size=%d)" % (self.__class__.__name__, self.size)
+        return f"{self.__class__.__name__}(size={self.size})"
 
     def copy(self):
         return SimTypeLength(signed=self.signed, addr=self.addr, length=self.length, label=self.label)
@@ -1322,7 +1318,7 @@ class SimTypeFloat(SimTypeReg):
         return "float"
 
     def _init_str(self):
-        return "%s(size=%d)" % (self.__class__.__name__, self.size)
+        return f"{self.__class__.__name__}(size={self.size})"
 
     def copy(self):
         return SimTypeFloat(self.size)
@@ -1510,7 +1506,7 @@ class SimStruct(NamedTypeMixin, SimType):
             raise TypeError(f"Can't store struct of type {type(value)}")
 
         if len(value) != len(self.fields):
-            raise ValueError("Passed bad values for %s; expected %d, got %d" % (self, len(self.offsets), len(value)))
+            raise ValueError(f"Passed bad values for {self}; expected {len(self.offsets)}, got {len(value)}")
 
         for field, offset in self.offsets.items():
             ty = self.fields[field]
@@ -1793,7 +1789,7 @@ class SimCppClass(SimStruct):
             raise TypeError(f"Can't store struct of type {type(value)}")
 
         if len(value) != len(self.fields):
-            raise ValueError("Passed bad values for %s; expected %d, got %d" % (self, len(self.offsets), len(value)))
+            raise ValueError(f"Passed bad values for {self}; expected {len(self.offsets)}, got {len(value)}")
 
         for field, offset in self.offsets.items():
             ty = self.fields[field]
@@ -3507,7 +3503,7 @@ def parse_cpp_file(cpp_decl, with_param_names: bool = False):
             idx = s.find(",", last_pos)
             if idx == -1:
                 break
-            arg_name = "a%d" % i
+            arg_name = f"a{i}"
             i += 1
             s = s[:idx] + " " + arg_name + s[idx:]
             last_pos = idx + len(arg_name) + 1 + 1
@@ -3516,7 +3512,7 @@ def parse_cpp_file(cpp_decl, with_param_names: bool = False):
         idx = s.find(")", last_pos)
         # TODO: consider the case where there are one or multiple spaces between ( and )
         if idx != -1 and s[idx - 1] != "(":
-            arg_name = "a%d" % i
+            arg_name = f"a{i}"
             s = s[:idx] + " " + arg_name + s[idx:]
 
     # CppHeaderParser does not like missing function body

angr/sim_variable.py

@@ -13,12 +13,12 @@ if TYPE_CHECKING:
 
 class SimVariable(Serializable):
     __slots__ = [
+        "candidate_names",
+        "category",
         "ident",
         "name",
         "region",
-        "category",
         "renamed",
-        "candidate_names",
         "size",
     ]
 
@@ -87,7 +87,7 @@ class SimVariable(Serializable):
 
 
 class SimConstantVariable(SimVariable):
-    __slots__ = ["value", "_hash"]
+    __slots__ = ["_hash", "value"]
 
     def __init__(self, size: int, ident=None, value=None, region=None):
         super().__init__(ident=ident, region=region, size=size)
@@ -122,7 +122,7 @@ class SimConstantVariable(SimVariable):
 
 
 class SimTemporaryVariable(SimVariable):
-    __slots__ = ["tmp_id", "_hash"]
+    __slots__ = ["_hash", "tmp_id"]
 
     def __init__(self, tmp_id: int, size: int):
         SimVariable.__init__(self, size=size)
@@ -131,14 +131,14 @@ class SimTemporaryVariable(SimVariable):
         self._hash = None
 
     def __repr__(self):
-        return "<tmp %d>" % (self.tmp_id,)
+        return f"<tmp {self.tmp_id}>"
 
     def loc_repr(self, arch):
         return f"tmp #{self.tmp_id}"
 
     def __hash__(self):
         if self._hash is None:
-            self._hash = hash("tmp_%d" % (self.tmp_id))
+            self._hash = hash(f"tmp_{self.tmp_id}")
         return self._hash
 
     def __eq__(self, other):
@@ -170,7 +170,7 @@ class SimTemporaryVariable(SimVariable):
 
 
 class SimRegisterVariable(SimVariable):
-    __slots__ = ["reg", "_hash"]
+    __slots__ = ["_hash", "reg"]
 
     def __init__(self, reg_offset: int, size: int, ident=None, name=None, region=None, category=None):
         SimVariable.__init__(self, ident=ident, name=name, region=region, category=category, size=size)
@@ -236,7 +236,7 @@ class SimRegisterVariable(SimVariable):
 
 
 class SimMemoryVariable(SimVariable):
-    __slots__ = ["addr", "_hash"]
+    __slots__ = ["_hash", "addr"]
 
     def __init__(self, addr, size: int, ident=None, name=None, region=None, category=None):
         SimVariable.__init__(self, ident=ident, name=name, region=region, category=category, size=size)
@@ -251,12 +251,10 @@ class SimMemoryVariable(SimVariable):
         self._hash = None
 
     def __repr__(self):
-        size = "%d" % self.size if type(self.size) is int else f"{self.size}"
-
         if type(self.addr) is int:
-            s = f"<{self.name}: {self.region}-Mem {self.addr:#x} {size}>"
+            s = f"<{self.name}: {self.region}-Mem {self.addr:#x} {self.size}>"
         else:
-            s = f"<{self.name}: {self.region}-Mem {self.addr} {size}>"
+            s = f"<{self.name}: {self.region}-Mem {self.addr} {self.size}>"
 
         return s
 
@@ -311,8 +309,8 @@ class SimMemoryVariable(SimVariable):
 class SimStackVariable(SimMemoryVariable):
     __slots__ = (
         "base",
-        "offset",
         "base_addr",
+        "offset",
     )
 
     def __init__(
@@ -333,8 +331,6 @@ class SimStackVariable(SimMemoryVariable):
         self.base_addr = base_addr
 
     def __repr__(self):
-        size = "%d" % self.size if type(self.size) is int else f"{self.size}"
-
         prefix = f"{self.name}(stack)" if self.name is not None else "Stack"
         ident = f"[{self.ident}]" if self.ident else ""
         region_str = hex(self.region) if isinstance(self.region, int) else self.region
@@ -347,9 +343,9 @@ class SimStackVariable(SimMemoryVariable):
             else:
                 offset = ""
 
-            s = f"<{region_str}{ident}|{prefix} {self.base}{offset}, {size} B>"
+            s = f"<{region_str}{ident}|{prefix} {self.base}{offset}, {self.size} B>"
         else:
-            s = f"<{region_str}{ident}|{prefix} {self.base}{self.addr}, {size} B>"
+            s = f"<{region_str}{ident}|{prefix} {self.base}{self.addr}, {self.size} B>"
 
         return s
 

angr/simos/__init__.py

@@ -34,12 +34,12 @@ register_simos("snimmuc_nxp", SimSnimmucNxp)
 
 
 __all__ = (
-    "SimOS",
-    "SimUserland",
-    "SimLinux",
     "SimCGC",
-    "SimWindows",
     "SimJavaVM",
+    "SimLinux",
+    "SimOS",
     "SimSnimmucNxp",
+    "SimUserland",
+    "SimWindows",
     "os_mapping",
 )

angr/simos/cgc.py

@@ -50,7 +50,7 @@ class SimCGC(SimUserland):
 
         # Set up the flag page
         if flag_page is None:
-            flag_page = [s.solver.BVS("cgc-flag-byte-%d" % i, 8, key=("flag", i), eternal=True) for i in range(0x1000)]
+            flag_page = [s.solver.BVS(f"cgc-flag-byte-{i}", 8, key=("flag", i), eternal=True) for i in range(0x1000)]
         elif type(flag_page) is bytes:
             flag_page = [claripy.BVV(c, 8) for c in flag_page]
         elif type(flag_page) is list:

angr/simos/simos.py

@@ -214,7 +214,7 @@ class SimOS:
                 empty_bools = [((val >> (x * 2)) & 3) == 3 for x in range(8)]
                 tag_chars = [claripy.BVV(0 if x else 1, 8) for x in empty_bools]
                 for i, tag in enumerate(tag_chars):
-                    setattr(state.regs, "fpu_t%d" % i, tag)
+                    setattr(state.regs, f"fpu_t{i}", tag)
             elif reg in ("fiseg", "fioff", "foseg", "fooff", "fop"):
                 pass
             elif reg == "mxcsr":

angr/simos/userland.py

@@ -149,7 +149,7 @@ class SimUserland(SimOS):
                 raise AngrUnsupportedSyscallError(f"{self.name} does not have a library of syscalls implemented")
             proc = P["stubs"]["syscall"]()
         elif not allow_unsupported and not self.syscall_library.has_implementation(number, self.arch, abilist):
-            raise AngrUnsupportedSyscallError("No implementation for syscall %d" % number)
+            raise AngrUnsupportedSyscallError(f"No implementation for syscall {number}")
         else:
             proc = self.syscall_library.get(number, self.arch, abilist)
 

angr/slicer.py

@@ -11,10 +11,10 @@ class SimLightState:
     """
 
     __slots__ = (
-        "temps",
+        "options",
         "regs",
         "stack_offsets",
-        "options",
+        "temps",
     )
 
     def __init__(self, temps=None, regs=None, stack_offsets=None, options=None):
@@ -155,11 +155,8 @@ class SimSlicer:
     def _forward_handler_expr_Get(self, expr, state):
         reg = expr.offset
 
-        if (
-            state.options["mock_sp"]
-            and reg == self._arch.sp_offset
-            or state.options["mock_bp"]
-            and reg == self._arch.bp_offset
+        if (state.options["mock_sp"] and reg == self._arch.sp_offset) or (
+            state.options["mock_bp"] and reg == self._arch.bp_offset
         ):
             return state.regs[reg]
 

angr/state_plugins/__init__.py

@@ -31,56 +31,56 @@ from .debug_variables import SimDebugVariable, SimDebugVariablePlugin
 
 
 __all__ = (
-    "SimStatePlugin",
-    "SimStateLibc",
-    "SimInspector",
-    "NO_OVERRIDE",
-    "BP_BEFORE",
     "BP_AFTER",
+    "BP_BEFORE",
     "BP_BOTH",
     "BP_IPDB",
     "BP_IPYTHON",
+    "GDB",
+    "NO_OVERRIDE",
+    "CallStack",
+    "Concrete",
+    "PTChunk",
+    "PTChunkIterator",
     "PosixDevFS",
     "PosixProcFS",
-    "SimSystemPosix",
-    "SimSolver",
-    "SimLightRegisters",
-    "SimStateLog",
-    "SimStateHistory",
-    "SimStateScratch",
-    "SimStateCGC",
-    "GDB",
-    "SimUCManager",
-    "Unicorn",
     "SimAction",
-    "SimActionExit",
     "SimActionConstraint",
-    "SimActionOperation",
     "SimActionData",
+    "SimActionExit",
     "SimActionObject",
+    "SimActionOperation",
+    "SimDebugVariable",
+    "SimDebugVariablePlugin",
     "SimEvent",
-    "resource_event",
-    "CallStack",
-    "SimStateGlobals",
-    "SimStatePreconstrainer",
-    "SimStateLoopData",
-    "SimRegNameView",
-    "SimMemView",
-    "StructMode",
-    "Stat",
     "SimFilesystem",
-    "SimMount",
-    "SimHostFilesystem",
     "SimHeapBase",
     "SimHeapBrk",
     "SimHeapLibc",
     "SimHeapPTMalloc",
-    "PTChunk",
-    "PTChunkIterator",
-    "Concrete",
-    "SimStateJNIReferences",
+    "SimHostFilesystem",
+    "SimInspector",
     "SimJavaVmClassloader",
+    "SimLightRegisters",
+    "SimMemView",
+    "SimMount",
+    "SimRegNameView",
+    "SimSolver",
+    "SimStateCGC",
+    "SimStateGlobals",
+    "SimStateHistory",
+    "SimStateJNIReferences",
+    "SimStateLibc",
+    "SimStateLog",
+    "SimStateLoopData",
+    "SimStatePlugin",
+    "SimStatePreconstrainer",
+    "SimStateScratch",
     "SimSymbolizer",
-    "SimDebugVariable",
-    "SimDebugVariablePlugin",
+    "SimSystemPosix",
+    "SimUCManager",
+    "Stat",
+    "StructMode",
+    "Unicorn",
+    "resource_event",
 )

angr/state_plugins/callstack.py

@@ -119,14 +119,11 @@ class CallStack(SimStatePlugin):
         :return: A printable representation of the CallStack object
         :rtype: str
         """
-        return "<CallStack (depth %d)>" % len(self)
+        return f"<CallStack (depth {len(self)})>"
 
     def __str__(self):
-        return "Backtrace:\n{}".format(
-            "\n".join(
-                "Frame %d: %#x => %#x, sp = %#x" % (i, f.call_site_addr, f.func_addr, f.stack_ptr)
-                for i, f in enumerate(self)
-            )
+        return "Backtrace:\n" + "\n".join(
+            f"Frame {i}: {f.call_site_addr:#x} => {f.func_addr:#x}, sp = {f.stack_ptr:#x}" for i, f in enumerate(self)
         )
 
     def __eq__(self, other):
@@ -319,13 +316,9 @@ class CallStack(SimStatePlugin):
 
         stack = []
         for i, frame in enumerate(self):
-            s = "%d | %s -> %s, returning to %s" % (
-                i,
-                "None" if frame.call_site_addr is None else f"{frame.call_site_addr:#x}",
-                "None" if frame.func_addr is None else f"{frame.func_addr:#x}",
-                "None" if frame.current_return_target is None else f"{frame.current_return_target:#x}",
+            stack.append(
+                f"{i} | {frame.call_site_addr:#x} -> {frame.func_addr:#x}, returning to {frame.current_return_target:#x}"
             )
-            stack.append(s)
 
         return "\n".join(stack)
 

angr/state_plugins/heap/__init__.py

@@ -6,10 +6,10 @@ from .heap_libc import SimHeapLibc
 from .heap_ptmalloc import SimHeapPTMalloc, PTChunk, PTChunkIterator
 
 __all__ = (
+    "PTChunk",
+    "PTChunkIterator",
     "SimHeapBase",
     "SimHeapBrk",
     "SimHeapLibc",
     "SimHeapPTMalloc",
-    "PTChunk",
-    "PTChunkIterator",
 )

angr/state_plugins/heap/heap_brk.py

@@ -90,10 +90,8 @@ class SimHeapBrk(SimHeapBase):
 
         final_size = size * nmemb
 
-        if (
-            self.state.solver.symbolic(sim_nmemb)
-            or self.state.solver.symbolic(sim_size)
-            and final_size > plugin.max_variable_size
+        if self.state.solver.symbolic(sim_nmemb) or (
+            self.state.solver.symbolic(sim_size) and final_size > plugin.max_variable_size
         ):
             final_size = plugin.max_variable_size
 

angr/state_plugins/heap/heap_ptmalloc.py

@@ -75,7 +75,7 @@ class PTChunk(Chunk):
                 next_chunk.set_prev_freeness(is_free)
             else:
                 self.heap._set_final_freeness(is_free)
-        if (is_free is not None and is_free or self.is_free()) and next_chunk is not None:
+        if ((is_free is not None and is_free) or self.is_free()) and next_chunk is not None:
             self.state.memory.store(next_chunk.base, size, size=self.state.arch.bytes)
 
     def set_prev_freeness(self, is_free):

angr/state_plugins/jni_references.py

@@ -30,8 +30,9 @@ class SimStateJNIReferences(SimStatePlugin):
         if opaque_ref_value in self.global_refs:
             return self.global_refs[opaque_ref_value]
         raise KeyError(
-            "Unknown JNI reference %d. Local references: %s Global references: %s"
-            % (opaque_ref_value, self.local_refs, self.global_refs)
+            f"Unknown JNI reference {opaque_ref_value}. "
+            f"Local references: {self.local_refs} "
+            f"Global references: {self.global_refs}"
         )
 
     def create_new_reference(self, obj, global_ref=False):

angr/state_plugins/scratch.py

@@ -108,7 +108,7 @@ class SimStateScratch(SimStatePlugin):
             v = self.temps[tmp]
             if v is None:
                 raise SimMissingTempError(
-                    "VEX temp variable %d does not exist. This is usually the result of an incorrect slicing." % tmp
+                    f"VEX temp variable {tmp} does not exist. This is usually the result of an incorrect slicing."
                 )
         except IndexError as err:
             raise SimMissingTempError("Accessing a temp that is illegal in this tyenv") from err

angr/state_plugins/sim_action.py

@@ -38,10 +38,7 @@ class SimAction(SimEvent):
         if self.sim_procedure is not None:
             location = f"{self.sim_procedure.display_name}()"
         else:
-            if self.stmt_idx is not None:
-                location = "0x%x:%d" % (self.ins_addr, self.stmt_idx)  # TODO: Revert this!
-            else:
-                location = f"0x{self.bbl_addr:x}"
+            location = f"0x{self.ins_addr:x}:{self.stmt_idx}" if self.stmt_idx is not None else f"0x{self.bbl_addr:x}"
         return f"<{self.__class__.__name__} {location} {self._desc()}>"
 
     def _desc(self):

angr/state_plugins/sim_event.py

@@ -25,7 +25,7 @@ class SimEvent:
         self.arch = state.arch
 
     def __repr__(self):
-        return "<SimEvent %s %d, with fields %s>" % (self.type, self.id, ", ".join(self.objects.keys()))
+        return f"<SimEvent {self.type} {self.id}, with fields {', '.join(self.objects.keys())}>"
 
     def _copy_event(self):
         c = self.__class__.__new__(self.__class__)

angr/state_plugins/solver.py

@@ -112,7 +112,7 @@ def error_converter(f):
 def _concrete_bool(e):
     if isinstance(e, bool):
         return e
-    if isinstance(e, claripy.ast.Base) and e.op == "BoolV" or isinstance(e, SimActionObject) and e.op == "BoolV":
+    if (isinstance(e, claripy.ast.Base) and e.op == "BoolV") or (isinstance(e, SimActionObject) and e.op == "BoolV"):
         return e.args[0]
     return None
 
@@ -302,10 +302,8 @@ class SimSolver(SimStatePlugin):
         elif o.SYMBOLIC in self.state.options and o.COMPOSITE_SOLVER in self.state.options:
             self._stored_solver = claripy.SolverComposite(track=track)
         elif (
-            o.SYMBOLIC in self.state.options
-            and any(opt in self.state.options for opt in o.approximation)
-            or o.HYBRID_SOLVER in self.state.options
-        ):
+            o.SYMBOLIC in self.state.options and any(opt in self.state.options for opt in o.approximation)
+        ) or o.HYBRID_SOLVER in self.state.options:
             self._stored_solver = claripy.SolverHybrid(track=track, approximate_first=approximate_first)
         elif o.SYMBOLIC in self.state.options:
             self._stored_solver = claripy.Solver(track=track)
@@ -856,7 +854,7 @@ class SimSolver(SimStatePlugin):
 
         cast_vals = [self._cast_to(e, v, cast_to) for v in self._eval(e, n, **kwargs)]
         if len(cast_vals) == 0:
-            raise SimUnsatError("Not satisfiable: %s, expected up to %d solutions" % (e.shallow_repr(), n))
+            raise SimUnsatError(f"Not satisfiable: {e.shallow_repr()}, expected up to {n} solutions")
         return cast_vals
 
     @overload
@@ -967,7 +965,7 @@ class SimSolver(SimStatePlugin):
         """
         r = self.eval_upto(e, n + 1, cast_to, **kwargs)
         if len(r) > n:
-            raise SimValueError("Concretized %d values (must be at most %d) in eval_atmost" % (len(r), n))
+            raise SimValueError(f"Concretized {len(r)} values (must be at most {n}) in eval_atmost")
         return r
 
     @overload
@@ -1002,7 +1000,7 @@ class SimSolver(SimStatePlugin):
         """
         r = self.eval_upto(e, n, cast_to, **kwargs)
         if len(r) != n:
-            raise SimValueError("Concretized %d values (must be at least %d) in eval_atleast" % (len(r), n))
+            raise SimValueError(f"Concretized {len(r)} values (must be at least {n}) in eval_atleast")
         return r
 
     @overload
@@ -1038,7 +1036,7 @@ class SimSolver(SimStatePlugin):
         """
         r = self.eval_upto(e, n + 1, cast_to, **kwargs)
         if len(r) != n:
-            raise SimValueError("Concretized %d values (must be exactly %d) in eval_exact" % (len(r), n))
+            raise SimValueError(f"Concretized {len(r)} values (must be exactly {n}) in eval_exact")
         return r
 
     min_int = min