angr 9.2.132__py3-none-manylinux2014_aarch64.whl → 9.2.133__py3-none-manylinux2014_aarch64.whl

angr/state_plugins/uc_manager.py

@@ -48,7 +48,7 @@ class SimUCManager(SimStatePlugin):
         dst_uc_alloc_depth = self._uc_alloc_depth[dst_addr_ast]
         if dst_uc_alloc_depth > self._max_alloc_depth:
             raise SimUCManagerAllocationError(
-                "Current allocation depth %d is greater than the cap (%d)" % (dst_uc_alloc_depth, self._max_alloc_depth)
+                f"Current allocation depth {dst_uc_alloc_depth} is greater than the cap ({self._max_alloc_depth})"
             )
 
         abs_addr = self._region_base + self._pos

angr/state_plugins/view.py

@@ -90,8 +90,8 @@ class SimRegNameView(SimStatePlugin):
         if self.state.arch.name in ("X86", "AMD64"):
             return (
                 list(self.state.arch.registers.keys())
-                + ["st%d" % n for n in range(8)]
-                + ["tag%d" % n for n in range(8)]
+                + [f"st{n}" for n in range(8)]
+                + [f"tag{n}" for n in range(8)]
                 + ["flags", "eflags", "rflags"]
             )
         if is_arm_arch(self.state.arch):

angr/storage/__init__.py

@@ -9,7 +9,7 @@ from .memory_mixins import DefaultMemory
 
 __all__ = (
     "DUMMY_SYMBOLIC_READ_VALUE",
+    "DefaultMemory",
     "SimFile",
     "SimMemoryObject",
-    "DefaultMemory",
 )

angr/storage/file.py

@@ -109,7 +109,7 @@ class SimFileBase(SimStatePlugin):
                     yield "?"
 
         nice_name = "".join(generate())
-        return "file_%d_%s" % (next(file_counter), nice_name)
+        return f"file_{next(file_counter)}_{nice_name}"
 
     def concretize(self, **kwargs):
         """
@@ -250,7 +250,7 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
         if type(self._size) is int:
             self._size = claripy.BVV(self._size, state.arch.bits)
         elif len(self._size) != state.arch.bits:
-            raise TypeError("SimFile size must be a bitvector of size %d (arch.bits)" % state.arch.bits)
+            raise TypeError(f"SimFile size must be a bitvector of size {state.arch.bits} (arch.bits)")
 
     @property
     def size(self):
@@ -379,7 +379,7 @@ class SimFileStream(SimFile):
         if type(self.pos) is int:
             self.pos = claripy.BVV(self.pos, state.arch.bits)
         elif len(self.pos) != state.arch.bits:
-            raise TypeError("SimFileStream position must be a bitvector of size %d (arch.bits)" % state.arch.bits)
+            raise TypeError(f"SimFileStream position must be a bitvector of size {state.arch.bits} (arch.bits)")
 
     def read(self, pos, size, **kwargs):
         no_stream = kwargs.pop("no_stream", False)
@@ -509,9 +509,9 @@ class SimPackets(SimFileBase):
         if pos is None:
             pos = len(self.content)
         if pos < 0:
-            raise SimFileError("SimPacket.read(%d): Negative packet number?" % pos)
+            raise SimFileError(f"SimPacket.read({pos}): Negative packet number?")
         if pos > len(self.content):
-            raise SimFileError("SimPacket.read(%d): Packet number is past frontier of %d?" % (pos, len(self.content)))
+            raise SimFileError(f"SimPacket.read({pos}): Packet number is past frontier of {len(self.content)}?")
         if pos != len(self.content):
             _, realsize = self.content[pos]
             self.state.add_constraints(realsize <= size)  # assert that the packet fits within the read request
@@ -533,7 +533,7 @@ class SimPackets(SimFileBase):
         # if short reads are enabled, replace size with a symbol
         if short_reads is True or (short_reads is None and sim_options.SHORT_READS in self.state.options):
             size = self.state.solver.BVS(
-                "packetsize_%d_%s" % (len(self.content), self.ident),
+                f"packetsize_{len(self.content)}_{self.ident}",
                 self.state.arch.bits,
                 key=("file", self.ident, "packetsize", len(self.content)),
             )
@@ -561,7 +561,7 @@ class SimPackets(SimFileBase):
 
         # generate the packet data and return it
         data = self.state.solver.BVS(
-            "packet_%d_%s" % (len(self.content), self.ident),
+            f"packet_{len(self.content)}_{self.ident}",
             max_size * self.state.arch.byte_width,
             key=("file", self.ident, "packet", len(self.content)),
         )
@@ -601,9 +601,9 @@ class SimPackets(SimFileBase):
         if pos is None:
             pos = len(self.content)
         if pos < 0:
-            raise SimFileError("SimPacket.write(%d): Negative packet number?" % pos)
+            raise SimFileError(f"SimPacket.write({pos}): Negative packet number?")
         if pos > len(self.content):
-            raise SimFileError("SimPacket.write(%d): Packet number is past frontier of %d?" % (pos, len(self.content)))
+            raise SimFileError(f"SimPacket.write({pos}): Packet number is past frontier of {len(self.content)}?")
         if pos != len(self.content):
             realdata, realsize = self.content[pos]
             maxlen = max(len(realdata), len(data))
@@ -1171,7 +1171,7 @@ class SimPacketsSlots(SimFileBase):
             self.read_sizes.pop(0)
 
         data = self.state.solver.BVS(
-            "packet_%d_%s" % (len(self.read_data), self.ident),
+            f"packet_{len(self.read_data)}_{self.ident}",
             real_size * self.state.arch.byte_width,
             key=("file", self.ident, "packet", len(self.read_data)),
         )

angr/storage/memory_mixins/__init__.py

@@ -249,69 +249,69 @@ SimState.register_default("javavm_memory", JavaVmMemory)
 
 
 __all__ = (
+    "AbstractMemory",
+    "AbstractMergerMixin",
     "ActionsMixinHigh",
     "ActionsMixinLow",
     "AddressConcretizationMixin",
-    "DataNormalizationMixin",
-    "InspectMixinHigh",
+    "ClemoryBackerMixin",
+    "ConcreteBackerMixin",
     "ConditionalMixin",
     "ConvenientMappingsMixin",
+    "CooperationBase",
+    "DataNormalizationMixin",
     "DefaultFillerMixin",
-    "SpecialFillerMixin",
-    "ExplicitFillerMixin",
+    "DefaultListPagesMemory",
+    "DefaultMemory",
+    "DictBackerMixin",
     "DirtyAddrsMixin",
+    "ExplicitFillerMixin",
+    "FastMemory",
     "HexDumperMixin",
+    "HistoryTrackingMixin",
+    "ISPOMixin",
+    "InspectMixinHigh",
+    "JavaVmMemory",
+    "JavaVmMemoryMixin",
+    "KeyValueMemory",
+    "KeyValueMemoryMixin",
     "LabelMergerMixin",
-    "MultiValueMergerMixin",
-    "NameResolutionMixin",
-    "SimplificationMixin",
-    "SimpleInterfaceMixin",
-    "SizeNormalizationMixin",
-    "SizeConcretizationMixin",
-    "SmartFindMixin",
-    "SymbolicMergerMixin",
-    "TopMergerMixin",
-    "UnderconstrainedMixin",
-    "UnwrapperMixin",
-    "ClemoryBackerMixin",
-    "ConcreteBackerMixin",
-    "DictBackerMixin",
-    "PagedMemoryMixin",
+    "LabeledMemory",
+    "ListPage",
     "ListPagesMixin",
-    "UltraPagesMixin",
     "ListPagesWithLabelsMixin",
+    "MVListPage",
     "MVListPagesMixin",
     "MVListPagesWithLabelsMixin",
-    "PrivilegedPagingMixin",
-    "StackAllocationMixin",
-    "PagedMemoryMultiValueMixin",
-    "CooperationBase",
     "MemoryObjectMixin",
-    "ISPOMixin",
-    "RefcountMixin",
-    "PermissionsMixin",
-    "HistoryTrackingMixin",
+    "MemoryRegionMetaMixin",
+    "MultiValueMergerMixin",
+    "MultiValuedMemory",
+    "NameResolutionMixin",
     "PageBase",
     "PageType",
-    "ListPage",
-    "MVListPage",
-    "UltraPage",
-    "SlottedMemoryMixin",
-    "RegionedMemoryMixin",
+    "PagedMemoryMixin",
+    "PagedMemoryMultiValueMixin",
+    "PermissionsMixin",
+    "PrivilegedPagingMixin",
+    "RefcountMixin",
     "RegionCategoryMixin",
-    "StaticFindMixin",
-    "AbstractMergerMixin",
-    "MemoryRegionMetaMixin",
     "RegionedAddressConcretizationMixin",
-    "KeyValueMemoryMixin",
-    "JavaVmMemoryMixin",
-    "DefaultMemory",
-    "DefaultListPagesMemory",
-    "FastMemory",
-    "AbstractMemory",
     "RegionedMemory",
-    "LabeledMemory",
-    "MultiValuedMemory",
-    "KeyValueMemory",
-    "JavaVmMemory",
+    "RegionedMemoryMixin",
+    "SimpleInterfaceMixin",
+    "SimplificationMixin",
+    "SizeConcretizationMixin",
+    "SizeNormalizationMixin",
+    "SlottedMemoryMixin",
+    "SmartFindMixin",
+    "SpecialFillerMixin",
+    "StackAllocationMixin",
+    "StaticFindMixin",
+    "SymbolicMergerMixin",
+    "TopMergerMixin",
+    "UltraPage",
+    "UltraPagesMixin",
+    "UnderconstrainedMixin",
+    "UnwrapperMixin",
 )

angr/storage/memory_mixins/default_filler_mixin.py

@@ -30,9 +30,7 @@ class DefaultFillerMixin(MemoryMixin):
             type(addr) is int
             and self.category == "mem"
             and options.ZERO_FILL_UNCONSTRAINED_MEMORY in self.state.options
-            or self.category == "reg"
-            and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options
-        ):
+        ) or (self.category == "reg" and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options):
             return claripy.BVV(0, bits)
 
         if self.category == "reg" and type(addr) is int and addr == self.state.arch.ip_offset:

angr/storage/memory_mixins/javavm_memory_mixin.py

@@ -192,7 +192,7 @@ class JavaVmMemoryMixin(MemoryMixin):
             self.state.add_constraints(constraint_on_start_idx)
 
     def _store_array_element_on_heap(self, array, idx, value, value_type, store_condition=None):
-        heap_elem_id = "%s[%d]" % (array.id, idx)
+        heap_elem_id = f"{array.id}[{idx}]"
         l.debug("Set %s to %s with condition %s", heap_elem_id, value, store_condition)
         if store_condition is not None:
             current_value = self._load_array_element_from_heap(array, idx)
@@ -267,7 +267,7 @@ class JavaVmMemoryMixin(MemoryMixin):
 
     def _load_array_element_from_heap(self, array: SimSootValue_ArrayBaseRef, idx):
         # try to load the element
-        heap_elem_id = "%s[%d]" % (array.id, idx)
+        heap_elem_id = f"{array.id}[{idx}]"
         value = self.heap.load(heap_elem_id, none_if_missing=True)
         # if it's not available, initialize it
         if value is None:

angr/storage/memory_mixins/name_resolution_mixin.py

@@ -5,8 +5,8 @@ from archinfo.arch_arm import is_arm_arch
 
 from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
-stn_map = {"st%d" % n: n for n in range(8)}
-tag_map = {"tag%d" % n: n for n in range(8)}
+stn_map = {f"st{n}": n for n in range(8)}
+tag_map = {f"tag{n}": n for n in range(8)}
 
 
 class NameResolutionMixin(MemoryMixin):

angr/storage/memory_mixins/paged_memory/paged_memory_mixin.py

@@ -107,9 +107,7 @@ class PagedMemoryMixin(
                     permissions = perms
                     break
 
-        return dict(
-            memory=self, memory_id="%s_%d" % (self.id, pageno), permissions=permissions, **self._extra_page_kwargs
-        )
+        return dict(memory=self, memory_id=f"{self.id}_{pageno}", permissions=permissions, **self._extra_page_kwargs)
 
     def _divide_addr(self, addr: int) -> tuple[int, int]:
         return divmod(addr, self.page_size)

angr/storage/memory_mixins/paged_memory/pages/__init__.py

@@ -34,14 +34,14 @@ from .ultra_page import UltraPage
 
 __all__ = (
     "CooperationBase",
-    "MemoryObjectMixin",
-    "ISPOMixin",
-    "RefcountMixin",
-    "PermissionsMixin",
     "HistoryTrackingMixin",
-    "PageBase",
-    "PageType",
+    "ISPOMixin",
     "ListPage",
     "MVListPage",
+    "MemoryObjectMixin",
+    "PageBase",
+    "PageType",
+    "PermissionsMixin",
+    "RefcountMixin",
     "UltraPage",
 )

angr/storage/memory_mixins/paged_memory/pages/list_page.py

@@ -263,7 +263,7 @@ class ListPage(MemoryObjectMixin, PageBase):
         for c in candidates:
             s_contains = self._contains(c, page_addr)
             o_contains = other._contains(c, page_addr)
-            if not s_contains and o_contains or s_contains and not o_contains:
+            if (not s_contains and o_contains) or (s_contains and not o_contains):
                 differences.add(c)
             else:
                 if self.content[c] is None:

angr/storage/memory_mixins/paged_memory/pages/multi_values.py

@@ -20,8 +20,8 @@ class MultiValues(Generic[MVType]):
     """
 
     __slots__ = (
-        "_values",
         "_single_value",
+        "_values",
     )
 
     _single_value: MVType | None

angr/storage/memory_mixins/paged_memory/pages/mv_list_page.py

@@ -330,7 +330,7 @@ class MVListPage(
         for c in candidates:
             s_contains = self._contains(c, page_addr)
             o_contains = other._contains(c, page_addr)
-            if not s_contains and o_contains or s_contains and not o_contains:
+            if (not s_contains and o_contains) or (s_contains and not o_contains):
                 differences.add(c)
             else:
                 if self.content[c] is None and self.sinkhole is not None:

angr/storage/memory_mixins/paged_memory/pages/ultra_page.py

@@ -430,10 +430,8 @@ class UltraPage(MemoryObjectMixin, PageBase):
             return None
         else:
             obj = self.symbolic_data[place]
-            if (
-                obj.includes(start + page_addr)
-                or memory is not None
-                and obj.includes(start + page_addr + (1 << memory.state.arch.bits))
+            if obj.includes(start + page_addr) or (
+                memory is not None and obj.includes(start + page_addr + (1 << memory.state.arch.bits))
             ):
                 return obj
             return None

angr/storage/memory_mixins/regioned_memory/__init__.py

@@ -8,10 +8,10 @@ from .region_meta_mixin import MemoryRegionMetaMixin
 from .regioned_address_concretization_mixin import RegionedAddressConcretizationMixin
 
 __all__ = (
-    "RegionedMemoryMixin",
-    "RegionCategoryMixin",
-    "StaticFindMixin",
     "AbstractMergerMixin",
     "MemoryRegionMetaMixin",
+    "RegionCategoryMixin",
     "RegionedAddressConcretizationMixin",
+    "RegionedMemoryMixin",
+    "StaticFindMixin",
 )

angr/storage/memory_mixins/regioned_memory/region_data.py

@@ -14,11 +14,11 @@ class AddressWrapper:
     """
 
     __slots__ = (
-        "region",
-        "region_base_addr",
         "address",
-        "is_on_stack",
         "function_address",
+        "is_on_stack",
+        "region",
+        "region_base_addr",
     )
 
     def __init__(self, region: str, region_base_addr: int, address, is_on_stack: bool, function_address: int | None):
@@ -62,8 +62,8 @@ class RegionDescriptor:
     """
 
     __slots__ = (
-        "region_id",
         "base_address",
+        "region_id",
         "related_function_address",
     )
 
@@ -145,7 +145,7 @@ class RegionMap:
         if self.is_stack:
             # Sanity check
             if not region_id.startswith("stack_"):
-                raise SimRegionMapError('Received a non-stack memory ID "%d" in a stack region map' % region_id)
+                raise SimRegionMapError(f'Received a non-stack memory ID "{region_id}" in a stack region map')
 
             # Remove all stack regions that are lower than the one to add
             while True:

angr/storage/memory_mixins/regioned_memory/region_meta_mixin.py

@@ -13,7 +13,7 @@ class Segment:
         self.size = size
 
     def __repr__(self):
-        return "Seg (%s [ %d ])" % (hex(self.offset), self.size)
+        return f"Seg ({hex(self.offset)} [ {self.size} ])"
 
 
 class AbstractLocation:
@@ -120,22 +120,20 @@ class AbstractLocation:
         return False
 
     def __repr__(self):
-        return "(%xh, %d) %s" % (
-            (self.basicblock_key if self.basicblock_key is not None else -1),
-            (self.statement_id if self.statement_id is not None else -1),
-            self._segment_list,
-        )
+        bbl_key = self.basicblock_key if self.basicblock_key is not None else -1
+        stmt_id = self.statement_id if self.statement_id is not None else -1
+        return f"({bbl_key:x}h, {stmt_id}) {self._segment_list}"
 
 
 class MemoryRegionMetaMixin(MemoryMixin):
     __slots__ = (
+        "_alocs",
         "_endness",
         "_id",
-        "_state",
         "_is_stack",
-        "_related_function_addr",
-        "_alocs",
         "_memory",
+        "_related_function_addr",
+        "_state",
     )
 
     def __init__(self, related_function_addr=None, **kwargs):

angr/storage/memory_mixins/regioned_memory/regioned_memory_mixin.py

@@ -95,9 +95,9 @@ class RegionedMemoryMixin(MemoryMixin):
         if isinstance(size, BV) and size.has_annotation_type(RegionAnnotation):
             _l.critical("load(): size %s is a ValueSet. Something is wrong.", size)
             if self.state.scratch.ins_addr is not None:
-                var_name = "invalid_read_%d_%#x" % (next(invalid_read_ctr), self.state.scratch.ins_addr)
+                var_name = f"invalid_read_{next(invalid_read_ctr)}_{self.state.scratch.ins_addr:#x}"
             else:
-                var_name = "invalid_read_%d_None" % next(invalid_read_ctr)
+                var_name = f"invalid_read_{next(invalid_read_ctr)}_None"
 
             return self.state.solver.Unconstrained(var_name, self.state.arch.bits)
 
@@ -127,7 +127,7 @@ class RegionedMemoryMixin(MemoryMixin):
             # address_wrappers is empty - we cannot concretize the address in static mode.
             # ensure val is not None
             val = self.state.solver.Unconstrained(
-                "invalid_read_%d_%d" % (next(invalid_read_ctr), size), size * self.state.arch.byte_width
+                f"invalid_read_{next(invalid_read_ctr)}_{size}", size * self.state.arch.byte_width
             )
 
         return val
@@ -225,7 +225,7 @@ class RegionedMemoryMixin(MemoryMixin):
         if region_id not in region_ids:
             return region_id
         for i in range(2000):
-            new_region_id = region_id + "_%d" % i
+            new_region_id = f"{region_id}_{i}"
             if new_region_id not in region_ids:
                 return new_region_id
         raise SimMemoryError(f"Cannot allocate region ID for function {function_address:#08x} - recursion too deep")

angr/storage/memory_object.py

@@ -21,13 +21,13 @@ class SimMemoryObject:
     """
 
     __slots__ = (
-        "is_bytes",
         "_byte_width",
+        "_concrete_bytes",
         "base",
-        "object",
-        "length",
         "endness",
-        "_concrete_bytes",
+        "is_bytes",
+        "length",
+        "object",
     )
 
     def __init__(self, obj, base, endness, length=None, byte_width=8):

angr/utils/__init__.py

@@ -36,11 +36,11 @@ def looks_like_sql(s: str) -> bool:
 
 
 __all__ = (
-    "timethis",
-    "graph",
     "constants",
     "enums_conv",
-    "lazy_import",
+    "graph",
     "is_pyinstaller",
+    "lazy_import",
     "looks_like_sql",
+    "timethis",
 )

angr/utils/dynamic_dictlist.py

@@ -19,7 +19,7 @@ class DynamicDictList(Generic[VT]):
     https://github.com/angr/angr/pull/3471#issuecomment-1236515950.
     """
 
-    __slots__ = ("list_content", "dict_content", "max_size")
+    __slots__ = ("dict_content", "list_content", "max_size")
 
     def __init__(
         self,

angr/utils/graph.py

@@ -572,7 +572,7 @@ class SCCPlaceholder:
         return isinstance(other, SCCPlaceholder) and other.scc_id == self.scc_id
 
     def __hash__(self):
-        return hash("scc_placeholder_%d" % self.scc_id)
+        return hash(f"scc_placeholder_{self.scc_id}")
 
 
 class GraphUtils:

angr/utils/segment_list.py

@@ -13,7 +13,7 @@ class Segment:
     Representing a memory block. This is not the "Segment" in ELF memory model
     """
 
-    __slots__ = ["start", "end", "sort"]
+    __slots__ = ["end", "sort", "start"]
 
     def __init__(self, start, end, sort):
         """
@@ -56,7 +56,7 @@ class SegmentList:
     blocks or not, and obtain the exact block(segment) that the address belongs to.
     """
 
-    __slots__ = ["_list", "_bytes_occupied"]
+    __slots__ = ["_bytes_occupied", "_list"]
 
     def __init__(self):
         self._list: list[Segment] = []

angr/utils/ssa/__init__.py

@@ -14,6 +14,9 @@ from .vvar_uses_collector import VVarUsesCollector
 from .tmp_uses_collector import TmpUsesCollector
 
 
+DEPHI_VVAR_REG_OFFSET = 4096
+
+
 @overload
 def get_reg_offset_base_and_size(
     reg_offset: int, arch: archinfo.Arch, size: int | None = None, resilient: Literal[True] = True
@@ -206,16 +209,20 @@ def phi_assignment_get_src(stmt: Statement) -> Phi | None:
     return None
 
 
+def is_dephi_vvar(vvar: VirtualVariable) -> bool:
+    return vvar.varid == DEPHI_VVAR_REG_OFFSET
+
+
 __all__ = (
     "VVarUsesCollector",
+    "get_tmp_deflocs",
+    "get_tmp_uselocs",
     "get_vvar_deflocs",
     "get_vvar_uselocs",
-    "is_const_assignment",
-    "is_phi_assignment",
-    "phi_assignment_get_src",
     "is_const_and_vvar_assignment",
+    "is_const_assignment",
     "is_const_vvar_load_assignment",
     "is_const_vvar_load_dirty_assignment",
-    "get_tmp_uselocs",
-    "get_tmp_deflocs",
+    "is_phi_assignment",
+    "phi_assignment_get_src",
 )

{angr-9.2.132.dist-info → angr-9.2.133.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: angr
-Version: 9.2.132
+Version: 9.2.133
 Summary: A multi-architecture binary analysis toolkit, with the ability to perform dynamic symbolic execution and various static analyses on binaries
 Home-page: https://github.com/angr/angr
 License: BSD-2-Clause
@@ -16,13 +16,13 @@ Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: CppHeaderParser
 Requires-Dist: GitPython
-Requires-Dist: ailment==9.2.132
-Requires-Dist: archinfo==9.2.132
+Requires-Dist: ailment==9.2.133
+Requires-Dist: archinfo==9.2.133
 Requires-Dist: cachetools
 Requires-Dist: capstone==5.0.3
 Requires-Dist: cffi>=1.14.0
-Requires-Dist: claripy==9.2.132
-Requires-Dist: cle==9.2.132
+Requires-Dist: claripy==9.2.133
+Requires-Dist: cle==9.2.133
 Requires-Dist: itanium-demangler
 Requires-Dist: mulpyplexer
 Requires-Dist: nampa
@@ -31,7 +31,7 @@ Requires-Dist: protobuf>=5.28.2
 Requires-Dist: psutil
 Requires-Dist: pycparser>=2.18
 Requires-Dist: pyformlang
-Requires-Dist: pyvex==9.2.132
+Requires-Dist: pyvex==9.2.133
 Requires-Dist: rich>=13.1.0
 Requires-Dist: sortedcontainers
 Requires-Dist: sympy