angr 9.2.131__py3-none-manylinux2014_x86_64.whl → 9.2.132__py3-none-manylinux2014_x86_64.whl

angr/exploration_techniques/unique.py

@@ -1,8 +1,9 @@
 from __future__ import annotations
-from difflib import SequenceMatcher
+
 from collections import Counter
+from difflib import SequenceMatcher
 
-from . import ExplorationTechnique
+from .base import ExplorationTechnique
 
 
 class UniqueSearch(ExplorationTechnique):

angr/exploration_techniques/veritesting.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
-from . import ExplorationTechnique
 
 from angr.sim_options import EFFICIENT_STATE_MERGING
+from .base import ExplorationTechnique
 
 
 class Veritesting(ExplorationTechnique):

angr/knowledge_plugins/key_definitions/atoms.py

@@ -220,10 +220,10 @@ class Register(Atom):
         "arch",
     )
 
-    def __init__(self, reg_offset: RegisterOffset, size: int, arch: Arch | None = None):
+    def __init__(self, reg_offset: RegisterOffset | int, size: int, arch: Arch | None = None):
         super().__init__(size)
 
-        self.reg_offset = reg_offset
+        self.reg_offset = RegisterOffset(reg_offset)
         self.arch = arch
 
     def __repr__(self):

angr/knowledge_plugins/key_definitions/live_definitions.py

@@ -1,5 +1,5 @@
 from __future__ import annotations
-from typing import Any, TYPE_CHECKING, overload
+from typing import Any, TYPE_CHECKING, cast, overload
 from collections.abc import Iterable, Generator
 import weakref
 import logging
@@ -14,7 +14,7 @@ import archinfo
 from angr.misc.ux import deprecated
 from angr.errors import SimMemoryMissingError, SimMemoryError
 from angr.storage.memory_mixins import MultiValuedMemory
-from angr.storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
+from angr.storage.memory_mixins.paged_memory.pages.multi_values import MVType, MultiValues
 from angr.knowledge_plugins.key_definitions.definition import A
 from angr.engines.light import SpOffset
 from angr.code_location import CodeLocation, ExternalCodeLocation
@@ -324,7 +324,7 @@ class LiveDefinitions:
                 return True
         return False
 
-    def stack_address(self, offset: int) -> claripy.ast.bv.BV | None:
+    def stack_address(self, offset: int) -> claripy.ast.bv.BV:
         base = claripy.BVS("stack_base", self.arch.bits, explicit_name=True)
         if offset:
             return base + offset
@@ -346,21 +346,21 @@ class LiveDefinitions:
                 return 0
             if addr.op == "__add__":
                 if len(addr.args) == 2:
-                    off0 = LiveDefinitions.get_stack_offset(addr.args[0], had_stack_base=True)
-                    off1 = LiveDefinitions.get_stack_offset(addr.args[1], had_stack_base=True)
+                    off0 = LiveDefinitions.get_stack_offset(cast(claripy.ast.BV, addr.args[0]), had_stack_base=True)
+                    off1 = LiveDefinitions.get_stack_offset(cast(claripy.ast.BV, addr.args[1]), had_stack_base=True)
                     if off0 is not None and off1 is not None:
                         return off0 + off1
                 elif len(addr.args) == 1:
                     return 0
             elif addr.op == "__sub__" and len(addr.args) == 2:
-                off0 = LiveDefinitions.get_stack_offset(addr.args[0], had_stack_base=True)
-                off1 = LiveDefinitions.get_stack_offset(addr.args[1], had_stack_base=True)
+                off0 = LiveDefinitions.get_stack_offset(cast(claripy.ast.BV, addr.args[0]), had_stack_base=True)
+                off1 = LiveDefinitions.get_stack_offset(cast(claripy.ast.BV, addr.args[1]), had_stack_base=True)
                 if off0 is not None and off1 is not None:
                     return off0 - off1
         return None
 
     @staticmethod
-    def annotate_with_def(symvar: claripy.ast.BV, definition: Definition) -> claripy.ast.BV:
+    def annotate_with_def(symvar: MVType, definition: Definition) -> MVType:
         """
 
         :param symvar:
@@ -562,9 +562,12 @@ class LiveDefinitions:
         else:
             definition: Definition = Definition(atom, code_loc, dummy=dummy, tags=tags)
             d = MultiValues()
+            count = 0
             for offset, vs in data.items():
                 for v in vs:
+                    count += 1
                     d.add_value(offset, self.annotate_with_def(v, definition))
+            assert count != 0, "MV may not be empty, use TOP instead"
 
         # set_object() replaces kill (not implemented) and add (add) in one step
         if isinstance(atom, Register):
@@ -659,7 +662,7 @@ class LiveDefinitions:
             self.other_uses.add_use(definition, code_loc, expr)
 
     def get_definitions(
-        self, thing: A | Definition[A] | Iterable[A] | Iterable[Definition[A]] | MultiValues
+        self, thing: Atom | Definition[Atom] | Iterable[Atom] | Iterable[Definition[Atom]] | MultiValues
     ) -> set[Definition[Atom]]:
         if isinstance(thing, MultiValues):
             defs = set()
@@ -973,7 +976,7 @@ class LiveDefinitions:
     @overload
     def deref(
         self,
-        pointer: MultiValues | A | Definition[A] | Iterable[A] | Iterable[Definition[A]],
+        pointer: MultiValues[claripy.ast.BV] | Atom | Definition[Atom] | Iterable[Atom] | Iterable[Definition[Atom]],
         size: int | DerefSize,
         endness: archinfo.Endness = ...,
     ) -> set[MemoryLocation]: ...
@@ -1023,7 +1026,7 @@ class LiveDefinitions:
                 if heap_offset is not None:
                     addr = HeapAddress(heap_offset)
                 elif pointer.op == "BVV":
-                    addr = pointer.args[0]
+                    addr = cast(int, pointer.args[0])
                 else:
                     # cannot resolve
                     return None
@@ -1054,8 +1057,8 @@ class LiveDefinitions:
         if "heap_base" in addr.variables:
             if addr.op == "BVS":
                 return 0
-            if addr.op == "__add__" and len(addr.args) == 2 and addr.args[1].op == "BVV":
-                return addr.args[1].concrete_value
+            if addr.op == "__add__" and len(addr.args) == 2 and cast(claripy.ast.BV, addr.args[1]).op == "BVV":
+                return cast(claripy.ast.BV, addr.args[1]).concrete_value
         return None
 
     def heap_address(self, offset: int | HeapAddress) -> claripy.ast.BV:

angr/knowledge_plugins/propagations/states.py

@@ -1,9 +1,12 @@
 # pylint:disable=too-many-boolean-expressions
 from __future__ import annotations
+from abc import abstractmethod
 from typing import Any, TYPE_CHECKING
 from collections import defaultdict
 import weakref
 
+from typing_extensions import Self
+
 import ailment
 import claripy
 import archinfo
@@ -114,7 +117,7 @@ class PropagatorState:
         self.model = model
         self.rda = rda
 
-    def __repr__(self):
+    def __repr__(self) -> str:
         return "<PropagatorState>"
 
     @classmethod
@@ -155,6 +158,7 @@ class PropagatorState:
         # comparing bytes from two sets of memory objects
         # we don't need to resort to byte-level comparison. object-level is good enough.
 
+        # TODO what if object is bytes?
         if mo_self.object.symbolic or mo_other.object.symbolic:
             if type(mo_self) is SimLabeledMemoryObject and type(mo_other) is SimLabeledMemoryObject:
                 return mo_self.label == mo_other.label and mo_self.object is mo_other.object
@@ -165,7 +169,7 @@ class PropagatorState:
         return None
 
     @staticmethod
-    def top(bits: int) -> claripy.ast.Bits:
+    def top(bits: int) -> claripy.ast.BV:
         """
         Get a TOP value.
 
@@ -243,10 +247,11 @@ class PropagatorState:
                             merge_occurred = True
         return merge_occurred
 
-    def copy(self) -> PropagatorState:
+    @abstractmethod
+    def copy(self) -> Self:
         raise NotImplementedError
 
-    def merge(self, *others):
+    def merge(self, *others: Self) -> tuple[Self, bool]:
         state = self.copy()
         merge_occurred = False
 
@@ -263,8 +268,8 @@ class PropagatorState:
         self._replacements = defaultdict(dict)
 
     def add_replacement(
-        self, codeloc: CodeLocation, old, new, force_replace: bool = False
-    ) -> bool:  # pylint:disable=unused-argument
+        self, codeloc: CodeLocation, old, new, force_replace: bool = False  # pylint:disable=unused-argument
+    ) -> bool:
         """
         Add a replacement record: Replacing expression `old` with `new` at program location `codeloc`.
         If the self._only_consts flag is set to true, only constant values will be set.
@@ -331,7 +336,7 @@ class RegisterComparisonAnnotation(claripy.Annotation):
     Annotate TOP values that are the result of register values comparing against constant values.
     """
 
-    def __init__(self, offset, size, cmp_op, value):
+    def __init__(self, offset: int, size: int, cmp_op: str, value: int):
         self.offset = offset
         self.size = size
         self.cmp_op = cmp_op
@@ -504,7 +509,7 @@ class PropagatorVEXState(PropagatorState):
         # TODO: Handle size
         self._stack_variables.store(offset, value, size=size, endness=endness)
 
-    def load_local_variable(self, offset, size, endness):  # pylint:disable=unused-argument
+    def load_local_variable(self, offset, size, endness) -> claripy.ast.BV:  # pylint:disable=unused-argument
         # TODO: Handle size
         try:
             return self._stack_variables.load(offset, size=size, endness=endness)

angr/knowledge_plugins/variables/variable_manager.py

@@ -1,5 +1,5 @@
 from __future__ import annotations
-from typing import Literal, TYPE_CHECKING
+from typing import Literal, TYPE_CHECKING, overload
 import logging
 from collections import defaultdict
 from itertools import count, chain
@@ -77,14 +77,14 @@ class VariableManagerInternal(Serializable):
 
         self.func_addr = func_addr
 
-        self._variables: set[SimVariable] = OrderedSet()  # all variables that are added to any region
+        self._variables: OrderedSet[SimVariable] = OrderedSet()  # all variables that are added to any region
         self._global_region = KeyedRegion()
         self._stack_region = KeyedRegion()
         self._register_region = KeyedRegion()
         self._live_variables = {}  # a mapping between addresses of program points and live variable collections
 
         self._variable_accesses: dict[SimVariable, set[VariableAccess]] = defaultdict(set)
-        self._insn_to_variable: dict[int, set[tuple[SimVariable, int]]] = defaultdict(set)
+        self._insn_to_variable: dict[int, set[tuple[SimVariable, int | None]]] = defaultdict(set)
         self._stmt_to_variable: dict[tuple[int, int] | tuple[int, int, int], set[tuple[SimVariable, int]]] = (
             defaultdict(set)
         )
@@ -115,7 +115,7 @@ class VariableManagerInternal(Serializable):
         # optimization
         self._variables_without_writes = set()
 
-        self.stack_offset_to_struct_member_info: dict[SimStackVariable, (int, SimStackVariable, SimStruct)] = {}
+        self.stack_offset_to_struct_member_info: dict[SimStackVariable, tuple[int, SimStackVariable, SimStruct]] = {}
 
         self.ret_val_size = None
 
@@ -291,9 +291,11 @@ class VariableManagerInternal(Serializable):
             variable_access = VariableAccess.parse_from_cmessage(varaccess_pb2, variable_by_ident=variable_by_ident)
             variable = variable_access.variable
             offset = variable_access.offset
+            assert variable is not None
             tpl = (variable, offset)
 
             model._variable_accesses[variable_access.variable].add(variable_access)
+            assert variable_access.location.ins_addr is not None
             model._insn_to_variable[variable_access.location.ins_addr].add(tpl)
             loc = (
                 (variable_access.location.block_addr, variable_access.location.stmt_idx)
@@ -670,9 +672,16 @@ class VariableManagerInternal(Serializable):
 
         return accesses
 
+    @overload
+    def get_variables(self, sort: Literal["stack"], collapse_same_ident: bool = False) -> list[SimStackVariable]: ...
+    @overload
+    def get_variables(self, sort: Literal["reg"], collapse_same_ident: bool = False) -> list[SimRegisterVariable]: ...
+    @overload
     def get_variables(
-        self, sort: Literal["stack", "reg"] | None = None, collapse_same_ident=False
-    ) -> list[SimStackVariable | SimRegisterVariable]:
+        self, sort: None, collapse_same_ident: bool = False
+    ) -> list[SimRegisterVariable | SimRegisterVariable]: ...
+
+    def get_variables(self, sort=None, collapse_same_ident=False):
         """
         Get a list of variables.
 
@@ -695,9 +704,14 @@ class VariableManagerInternal(Serializable):
 
         return variables
 
-    def get_unified_variables(
-        self, sort: Literal["stack", "reg"] | None = None
-    ) -> list[SimStackVariable | SimRegisterVariable]:
+    @overload
+    def get_unified_variables(self, sort: Literal["stack"]) -> list[SimStackVariable]: ...
+    @overload
+    def get_unified_variables(self, sort: Literal["reg"]) -> list[SimRegisterVariable]: ...
+    @overload
+    def get_unified_variables(self, sort: None) -> list[SimRegisterVariable | SimRegisterVariable]: ...
+
+    def get_unified_variables(self, sort=None):
         """
         Get a list of unified variables.
 

angr/sim_manager.py

@@ -10,6 +10,7 @@ from types import TracebackType
 import claripy
 import mulpyplexer
 
+from .exploration_techniques import ExplorationTechnique, Veritesting, Threading, Explorer, Suggestions
 from .misc.hookset import HookSet
 from .misc.ux import once
 from .misc.picklable_lock import PicklableLock
@@ -968,6 +969,3 @@ class ErrorRecord:
 
     def __eq__(self, other):
         return self is other or self.state is other
-
-
-from .exploration_techniques import ExplorationTechnique, Veritesting, Threading, Explorer, Suggestions

angr/sim_state.py

@@ -5,12 +5,14 @@ import functools
 import itertools
 import logging
 import weakref
-from typing import TypeVar, TYPE_CHECKING
+from typing import Any, TypeVar, TYPE_CHECKING, Generic
+from collections.abc import Callable
 
 import archinfo
-import claripy
 from archinfo import Arch
 from archinfo.arch_soot import SootAddressDescriptor
+import claripy
+from cle import Clemory
 
 from . import sim_options as o
 from .errors import SimMergeError, SimValueError, SimStateError, SimSolverModeError
@@ -27,6 +29,8 @@ if TYPE_CHECKING:
     from .state_plugins.inspect import SimInspector
     from .state_plugins.jni_references import SimStateJNIReferences
     from .state_plugins.scratch import SimStateScratch
+    from angr.project import Project
+    from angr.simos.javavm import SimJavaVM
 
 
 l = logging.getLogger(name=__name__)
@@ -48,9 +52,12 @@ merge_counter = itertools.count()
 
 _complained_se = False
 
+IPTypeConc = TypeVar("IPTypeConc")
+IPTypeSym = TypeVar("IPTypeSym")
+
 
 # pylint: disable=not-callable
-class SimState(PluginHub):
+class SimState(Generic[IPTypeConc, IPTypeSym], PluginHub[SimStatePlugin]):
     """
     The SimState represents the state of a program, including its memory, registers, and so forth.
 
@@ -88,23 +95,23 @@ class SimState(PluginHub):
 
     def __init__(
         self,
-        project=None,
-        arch=None,
-        plugins=None,
-        mode=None,
-        options=None,
-        add_options=None,
-        remove_options=None,
-        special_memory_filler=None,
-        os_name=None,
-        plugin_preset="default",
-        cle_memory_backer=None,
-        dict_memory_backer=None,
-        permissions_map=None,
-        default_permissions=3,
-        stack_perms=None,
-        stack_end=None,
-        stack_size=None,
+        project: Project | None = None,
+        arch: Arch | None = None,
+        plugins: dict[str, SimStatePlugin] | None = None,
+        mode: str | None = None,
+        options: set[str] | list[str] | SimStateOptions | None = None,
+        add_options: set[str] | None = None,
+        remove_options: set[str] | None = None,
+        special_memory_filler: Callable[[str, int, int, SimState], Any] | None = None,
+        os_name: str | None = None,
+        plugin_preset: str = "default",
+        cle_memory_backer: Clemory | None = None,
+        dict_memory_backer: dict[int, bytes] | None = None,
+        permissions_map: dict[tuple[int, int], int] | None = None,
+        default_permissions: int = 3,
+        stack_perms: int | None = None,
+        stack_end: int | None = None,
+        stack_size: int | None = None,
         regioned_memory_cls=None,
         **kwargs,
     ):
@@ -118,7 +125,9 @@ class SimState(PluginHub):
         self._is_java_jni_project = self.project and self.project.is_java_jni_project
 
         # Arch
-        if self._is_java_jni_project:
+        if self._is_java_jni_project and project is not None:
+            if TYPE_CHECKING:
+                assert isinstance(project.simos, SimJavaVM)
             self._arch = {"soot": project.arch, "vex": project.simos.native_simos.arch}
             # This flag indicates whether the current ip is a native address or
             # a soot address descriptor.
@@ -177,6 +186,7 @@ class SimState(PluginHub):
             # we have no choice but to use the 'default' plugin preset.
             if self.plugin_preset is None:
                 self.use_plugin_preset("default")
+            assert self.plugin_preset is not None
 
             # Determine memory backend
             if self._is_java_project and not self._is_java_jni_project:
@@ -186,16 +196,14 @@ class SimState(PluginHub):
             elif o.ABSTRACT_MEMORY in self.options:
                 # We use SimAbstractMemory in static mode.
                 # Convert memory_backer into 'global' region.
-                if cle_memory_backer is not None:
-                    cle_memory_backer = {"global": cle_memory_backer}
-                if dict_memory_backer is not None:
-                    dict_memory_backer = {"global": dict_memory_backer}
+                cle_memory_backer_map = {"global": cle_memory_backer} if cle_memory_backer is not None else None
+                dict_memory_backer_map = {"global": dict_memory_backer} if dict_memory_backer is not None else None
 
                 # TODO: support permissions backer in SimAbstractMemory
                 sim_memory_cls = self.plugin_preset.request_plugin("abs_memory")
                 sim_memory = sim_memory_cls(
-                    cle_memory_backer=cle_memory_backer,
-                    dict_memory_backer=dict_memory_backer,
+                    cle_memory_backer=cle_memory_backer_map,
+                    dict_memory_backer=dict_memory_backer_map,
                     memory_id="mem",
                     regioned_memory_cls=regioned_memory_cls,
                 )
@@ -234,6 +242,7 @@ class SimState(PluginHub):
             # Same as for 'memory' plugin.
             if self.plugin_preset is None:
                 self.use_plugin_preset("default")
+            assert self.plugin_preset is not None
 
             # Get register endness
             if self._is_java_jni_project:
@@ -322,17 +331,6 @@ class SimState(PluginHub):
         # TODO: This shouldn't be access directly.
         return self._active_plugins
 
-    @property
-    def se(self):
-        """
-        Deprecated alias for `solver`
-        """
-        global _complained_se
-        if not _complained_se:
-            _complained_se = True
-            l.critical("The name state.se is deprecated; please use state.solver.")
-        return self.get_plugin("solver")
-
     @property
     def ip(self):
         """
@@ -348,7 +346,7 @@ class SimState(PluginHub):
         self.regs.ip = val
 
     @property
-    def _ip(self):
+    def _ip(self) -> IPTypeSym:
         """
         Get the instruction pointer expression without triggering SimInspect breakpoints or generating SimActions.
 
@@ -360,7 +358,7 @@ class SimState(PluginHub):
             raise TypeError(str(e)) from e
 
     @_ip.setter
-    def _ip(self, val):
+    def _ip(self, val: IPTypeSym | IPTypeConc):
         """
         Set the instruction pointer without triggering SimInspect breakpoints or generating SimActions.
 
@@ -373,7 +371,7 @@ class SimState(PluginHub):
             raise TypeError(str(e)) from e
 
     @property
-    def addr(self):
+    def addr(self) -> IPTypeConc:
         """
         Get the concrete address of the instruction pointer, without triggering SimInspect breakpoints or generating
         SimActions. An integer is returned, or an exception is raised if the instruction pointer is symbolic.

angr/sim_type.py

@@ -535,6 +535,11 @@ class SimTypeInt256(SimTypeFixedSizeInt):
     _fixed_size = 256
 
 
+class SimTypeInt512(SimTypeFixedSizeInt):
+    _base_name = "int512_t"
+    _fixed_size = 512
+
+
 class SimTypeChar(SimTypeReg):
     """
     SimTypeChar is a type that specifies a character;

angr/sim_variable.py

@@ -22,7 +22,9 @@ class SimVariable(Serializable):
         "size",
     ]
 
-    def __init__(self, ident=None, name=None, region: int | None = None, category=None, size: int | None = None):
+    def __init__(
+        self, size: int, ident: str | None = None, name: str | None = None, region: int | None = None, category=None
+    ):
         """
         :param ident: A unique identifier provided by user or the program. Usually a string.
         :param str name: Name of this variable.
@@ -87,7 +89,7 @@ class SimVariable(Serializable):
 class SimConstantVariable(SimVariable):
     __slots__ = ["value", "_hash"]
 
-    def __init__(self, ident=None, value=None, region=None, size=None):
+    def __init__(self, size: int, ident=None, value=None, region=None):
         super().__init__(ident=ident, region=region, size=size)
         self.value = value
         self._hash = None
@@ -122,7 +124,7 @@ class SimConstantVariable(SimVariable):
 class SimTemporaryVariable(SimVariable):
     __slots__ = ["tmp_id", "_hash"]
 
-    def __init__(self, tmp_id, size=None):
+    def __init__(self, tmp_id: int, size: int):
         SimVariable.__init__(self, size=size)
 
         self.tmp_id = tmp_id
@@ -162,7 +164,7 @@ class SimTemporaryVariable(SimVariable):
 
     @classmethod
     def parse_from_cmessage(cls, cmsg, **kwargs):
-        obj = cls(cmsg.tmp_id)
+        obj = cls(cmsg.tmp_id, cmsg.base.size)
         obj._from_base(cmsg)
         return obj
 
@@ -170,10 +172,10 @@ class SimTemporaryVariable(SimVariable):
 class SimRegisterVariable(SimVariable):
     __slots__ = ["reg", "_hash"]
 
-    def __init__(self, reg_offset, size, ident=None, name=None, region=None, category=None):
+    def __init__(self, reg_offset: int, size: int, ident=None, name=None, region=None, category=None):
         SimVariable.__init__(self, ident=ident, name=name, region=region, category=category, size=size)
 
-        self.reg: int = reg_offset
+        self.reg = reg_offset
         self._hash: int | None = None
 
     @property
@@ -236,7 +238,7 @@ class SimRegisterVariable(SimVariable):
 class SimMemoryVariable(SimVariable):
     __slots__ = ["addr", "_hash"]
 
-    def __init__(self, addr, size, ident=None, name=None, region=None, category=None):
+    def __init__(self, addr, size: int, ident=None, name=None, region=None, category=None):
         SimVariable.__init__(self, ident=ident, name=name, region=region, category=category, size=size)
 
         self.addr = addr
@@ -313,7 +315,9 @@ class SimStackVariable(SimMemoryVariable):
         "base_addr",
     )
 
-    def __init__(self, offset, size, base="sp", base_addr=None, ident=None, name=None, region=None, category=None):
+    def __init__(
+        self, offset: int, size: int, base="sp", base_addr=None, ident=None, name=None, region=None, category=None
+    ):
         if isinstance(offset, int) and offset > 0x1000000:
             # I don't think any positive stack offset will be greater than that...
             # convert it to a negative number
@@ -422,16 +426,15 @@ class SimVariableSet(collections.abc.MutableSet):
         # For the sake of performance, we have another set that stores memory addresses of memory_variables
         self.memory_variable_addresses = set()
 
-    def add(self, item):  # pylint:disable=arguments-differ
-        if type(item) is SimRegisterVariable:
-            if not self.contains_register_variable(item):
-                self.add_register_variable(item)
-        elif type(item) is SimMemoryVariable:
-            if not self.contains_memory_variable(item):
-                self.add_memory_variable(item)
+    def add(self, value):
+        if type(value) is SimRegisterVariable:
+            if not self.contains_register_variable(value):
+                self.add_register_variable(value)
+        elif type(value) is SimMemoryVariable:
+            if not self.contains_memory_variable(value):
+                self.add_memory_variable(value)
         else:
-            # TODO:
-            raise Exception("WTF")
+            assert False, "Unknown type"
 
     def add_register_variable(self, reg_var):
         self.register_variables.add(reg_var)
@@ -443,16 +446,15 @@ class SimVariableSet(collections.abc.MutableSet):
         for i in range(mem_var.size):
             self.memory_variable_addresses.add(base_address + i)
 
-    def discard(self, item):  # pylint:disable=arguments-differ
-        if type(item) is SimRegisterVariable:
-            if self.contains_register_variable(item):
-                self.discard_register_variable(item)
-        elif isinstance(item, SimMemoryVariable):
-            if self.contains_memory_variable(item):
-                self.discard_memory_variable(item)
+    def discard(self, value):
+        if type(value) is SimRegisterVariable:
+            if self.contains_register_variable(value):
+                self.discard_register_variable(value)
+        elif isinstance(value, SimMemoryVariable):
+            if self.contains_memory_variable(value):
+                self.discard_memory_variable(value)
         else:
-            # TODO:
-            raise Exception("")
+            assert False, "Unknown type"
 
     def discard_register_variable(self, reg_var):
         self.register_variables.remove(reg_var)
@@ -528,5 +530,4 @@ class SimVariableSet(collections.abc.MutableSet):
             # TODO: Make it better!
             return self.contains_memory_variable(item)
 
-        __import__("ipdb").set_trace()
-        raise Exception("WTF is this variable?")
+        assert False, "WTF is this variable?"

angr/utils/bits.py

@@ -1,5 +1,7 @@
 from __future__ import annotations
 
+import claripy
+
 
 def truncate_bits(value: int, nbits: int) -> int:
     """
@@ -19,3 +21,13 @@ def ffs(x: int) -> int:
 def sign_extend(value: int, bits: int) -> int:
     sign_bit = 1 << (bits - 1)
     return (value & (sign_bit - 1)) - (value & sign_bit)
+
+
+def zeroextend_on_demand(op0: claripy.ast.BV, op1: claripy.ast.BV) -> claripy.ast.BV:
+    """
+    ZeroExtend op1 if the size of op1 is smaller than the size of op0. Otherwise, return op1.
+    """
+
+    if op0.size() > op1.size():
+        return claripy.ZeroExt(op0.size() - op1.size(), op1)
+    return op1

angr/utils/orderedset.py

@@ -1,8 +1,11 @@
 from __future__ import annotations
+from typing import Generic, TypeVar
 import collections.abc
 
+T = TypeVar("T")
 
-class OrderedSet(collections.abc.MutableSet):
+
+class OrderedSet(Generic[T], collections.abc.MutableSet[T]):
     """
     Adapted from http://code.activestate.com/recipes/576694/
     Originally created by Raymond Hettinger and licensed under MIT.