angr 9.2.119__py3-none-win_amd64.whl → 9.2.121__py3-none-win_amd64.whl

angr/state_plugins/preconstrainer.py

@@ -4,8 +4,8 @@ import logging
 import claripy
 
 from .plugin import SimStatePlugin
-from .. import sim_options as o
-from ..errors import AngrError
+from angr import sim_options as o
+from angr.errors import AngrError
 
 
 l = logging.getLogger(name=__name__)
@@ -55,8 +55,8 @@ class SimStatePreconstrainer(SimStatePlugin):
         """
         if not isinstance(value, claripy.ast.Base):
             value = claripy.BVV(value, len(variable))
-        elif value.op != "BVV":
-            raise ValueError("Passed a value to preconstrain that was not a BVV or a string")
+        elif value.op not in ["BVV", "FPV"]:
+            raise ValueError("Passed a value to preconstrain that was not a BVV or FPV or a string")
 
         if not variable.is_leaf():
             l.warning(

angr/state_plugins/scratch.py

@@ -167,10 +167,10 @@ class SimStateScratch(SimStatePlugin):
 
 # pylint:disable=wrong-import-position
 from .sim_action import SimActionObject, SimActionData
-from ..errors import SimValueError, SimMissingTempError
-from .. import sim_options as o
+from angr.errors import SimValueError, SimMissingTempError
+from angr import sim_options as o
 from .inspect import BP_AFTER, BP_BEFORE
 
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 SimState.register_default("scratch", SimStateScratch)

angr/state_plugins/sim_action_object.py

@@ -9,7 +9,7 @@ import claripy
 from angr import sim_options as o
 from angr.errors import SimActionError
 from .sim_action import SimActionData, SimActionOperation
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 if typing.TYPE_CHECKING:
     from claripy.annotation import Annotation

angr/state_plugins/solver.py

@@ -1,4 +1,5 @@
 from __future__ import annotations
+
 import functools
 import time
 import logging
@@ -10,8 +11,10 @@ import claripy
 from angr import sim_options as o
 from angr.errors import SimValueError, SimUnsatError, SimSolverModeError, SimSolverOptionError
 from angr.sim_state import SimState
+from .inspect import BP_AFTER, BP_BEFORE
 from .plugin import SimStatePlugin
 from .sim_action_object import ast_stripping_decorator, SimActionObject
+from .sim_action import SimActionConstraint
 
 l = logging.getLogger(name=__name__)
 
@@ -346,23 +349,19 @@ class SimSolver(SimStatePlugin):
         """
         if o.SYMBOLIC_INITIAL_VALUES in self.state.options:
             # Return a symbolic value
-            if o.ABSTRACT_MEMORY in self.state.options:
-                l.debug("Creating new top StridedInterval")
-                r = claripy.TSI(bits=bits, name=name, uninitialized=uninitialized, **kwargs)
-            else:
-                l.debug("Creating new unconstrained BV named %s", name)
-                r = self.BVS(
-                    name,
-                    bits,
-                    uninitialized=uninitialized,
-                    key=key,
-                    eternal=eternal,
-                    inspect=inspect,
-                    events=events,
-                    **kwargs,
-                )
-                if uc_alloc_depth is not None:
-                    self.state.uc_manager.set_alloc_depth(r, uc_alloc_depth)
+            l.debug("Creating new unconstrained BV named %s", name)
+            r = self.BVS(
+                name,
+                bits,
+                uninitialized=uninitialized,
+                key=key,
+                eternal=eternal,
+                inspect=inspect,
+                events=events,
+                **kwargs,
+            )
+            if uc_alloc_depth is not None:
+                self.state.uc_manager.set_alloc_depth(r, uc_alloc_depth)
 
             return r
         # Return a default value, aka. 0
@@ -411,26 +410,18 @@ class SimSolver(SimStatePlugin):
         if key is not None and eternal and key in self.eternal_tracked_variables:
             r = self.eternal_tracked_variables[key]
             # pylint: disable=too-many-boolean-expressions
-            if (
-                size != r.length
-                or min != r.args[1]
-                or max != r.args[2]
-                or stride != r.args[3]
-                or uninitialized != r.args[4]
-                or bool(explicit_name) ^ (r.args[0] == name)
-            ):
+            if size != r.length or uninitialized != r.uninitialized or bool(explicit_name) ^ (r.args[0] == name):
                 l.warning("Variable %s being retrieved with different settings than it was tracked with", name)
         else:
             r = claripy.BVS(
                 name,
                 size,
-                min=min,
-                max=max,
-                stride=stride,
                 uninitialized=uninitialized,
                 explicit_name=explicit_name,
                 **kwargs,
             )
+            if any(x is not None for x in (min, max, stride)):
+                r = r.annotate(claripy.annotation.StridedIntervalAnnotation(stride, min, max))
             if key is not None:
                 self.register_variable(r, key, eternal)
 
@@ -696,6 +687,9 @@ class SimSolver(SimStatePlugin):
 
         :return:                    True if sat, otherwise false
         """
+        if o.ABSTRACT_SOLVER in self.state.options or o.SYMBOLIC not in self.state.options:
+            return all(not self.is_false(e) for e in extra_constraints)
+
         if exact is False and o.VALIDATE_APPROXIMATIONS in self.state.options:
             er = self._solver.satisfiable(extra_constraints=self._adjust_constraint_list(extra_constraints))
             ar = self._solver.satisfiable(
@@ -715,8 +709,69 @@ class SimSolver(SimStatePlugin):
 
         :param constraints:     Pass any constraints that you want to add (ASTs) as varargs.
         """
-        cc = self._adjust_constraint_list(constraints)
-        return self._solver.add(cc)
+        if len(constraints) > 0 and isinstance(constraints[0], (list, tuple)):
+            raise Exception("Tuple or list passed to add!")
+
+        if o.TRACK_CONSTRAINTS in self.state.options and len(constraints) > 0:
+            constraints = (
+                [self.simplify(a) for a in constraints] if o.SIMPLIFY_CONSTRAINTS in self.state.options else constraints
+            )
+
+            self.state._inspect("constraints", BP_BEFORE, added_constraints=constraints)
+            constraints = self.state._inspect_getattr("added_constraints", constraints)
+            cc = self._adjust_constraint_list(constraints)
+            added = self._solver.add(cc)
+            self.state._inspect("constraints", BP_AFTER)
+
+            # add actions for the added constraints
+            if o.TRACK_CONSTRAINT_ACTIONS in self.state.options:
+                for c in added:
+                    sac = SimActionConstraint(self.state, c)
+                    self.state.history.add_action(sac)
+
+        if o.ABSTRACT_SOLVER in self.state.options and len(constraints) > 0:
+            for arg in constraints:
+                if self.is_false(arg):
+                    return
+
+                if self.is_true(arg):
+                    continue
+
+                # It's neither True or False. Let's try to apply the condition
+
+                # We take the argument, extract a list of constrained SIs out of
+                # it (if we could, of course), and then replace each original SI
+                # the intersection of original SI and the constrained one.
+
+                _, converted = claripy.constraint_to_si(arg)
+
+                for original_expr, constrained_si in converted:
+                    if not original_expr.variables:
+                        l.error(
+                            "Incorrect original_expression to replace in add(). "
+                            "This is due to defects in VSA logics inside claripy. "
+                            "Please report to Fish and he will fix it if he's free."
+                        )
+                        continue
+
+                    new_expr = constrained_si
+                    self.state.registers.replace_all(original_expr, new_expr)
+                    self.state.memory.replace_all(original_expr, new_expr)
+                    # tmps
+                    temps = self.state.scratch.temps
+                    for idx in range(len(temps)):  # pylint:disable=consider-using-enumerate
+                        t = temps[idx]
+                        if t is None:
+                            continue
+                        if t.variables.intersection(original_expr.variables):
+                            # replace
+                            temps[idx] = claripy.replace(t, original_expr, new_expr)
+
+                    l.debug("SimSolver.add: Applied to final state.")
+        elif o.SYMBOLIC not in self.state.options and len(constraints) > 0:
+            for arg in constraints:
+                if self.is_false(arg):
+                    return
 
     #
     # And some convenience stuff
@@ -1067,5 +1122,3 @@ class SimSolver(SimStatePlugin):
 
 
 SimState.register_default("solver", SimSolver)
-
-from .inspect import BP_AFTER

angr/state_plugins/symbolizer.py

@@ -4,11 +4,10 @@ import claripy
 import struct
 
 from .plugin import SimStatePlugin
-from ..storage.memory_mixins import PagedMemoryMixin
+from angr.storage.memory_mixins import PagedMemoryMixin
 
 
 l = logging.getLogger(name=__name__)
-l.setLevel("DEBUG")
 
 
 def _mem_write_cb(s):
@@ -286,6 +285,6 @@ class SimSymbolizer(SimStatePlugin):  # pylint:disable=abstract-method
         return sc
 
 
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 SimState.register_default("symbolizer", SimSymbolizer)

angr/state_plugins/uc_manager.py

@@ -4,7 +4,7 @@ import logging
 import claripy
 
 from .plugin import SimStatePlugin
-from ..errors import SimUCManagerAllocationError
+from angr.errors import SimUCManagerAllocationError
 
 l = logging.getLogger(name=__name__)
 

angr/state_plugins/unicorn_engine.py

@@ -17,10 +17,10 @@ import pyvex
 from angr.engines.vex.claripy import ccall
 from angr.sim_state import SimState
 
-from .. import sim_options as options
-from ..engines.vex.claripy.irop import operations as irop_ops
-from ..errors import SimMemoryError, SimSegfaultError, SimUnicornError, SimUnicornUnsupport, SimValueError
-from ..misc.testing import is_testing
+from angr import sim_options as options
+from angr.engines.vex.claripy.irop import operations as irop_ops
+from angr.errors import SimMemoryError, SimSegfaultError, SimUnicornError, SimUnicornUnsupport, SimValueError
+from angr.misc.testing import is_testing
 from .plugin import SimStatePlugin
 
 l = logging.getLogger(name=__name__)

angr/state_plugins/view.py

@@ -331,7 +331,7 @@ class StructMode:
             self.__getattr__(k).store(v)
 
 
-from ..sim_type import ALL_TYPES, SimTypeFixedSizeArray, SimTypePointer
+from angr.sim_type import ALL_TYPES, SimTypeFixedSizeArray, SimTypePointer
 
 SimMemView.types = ALL_TYPES  # identity purposefully here
 

angr/storage/__init__.py

@@ -1,10 +1,15 @@
-# misc
 from __future__ import annotations
 
 DUMMY_SYMBOLIC_READ_VALUE = 0xC0DEB4BE
 
-# imports
-
 from .file import SimFile
 from .memory_object import SimMemoryObject
-from .memory_mixins import MemoryMixin, DefaultMemory
+from .memory_mixins import DefaultMemory
+
+
+__all__ = (
+    "DUMMY_SYMBOLIC_READ_VALUE",
+    "SimFile",
+    "SimMemoryObject",
+    "DefaultMemory",
+)

angr/storage/file.py

@@ -5,9 +5,9 @@ import itertools
 import claripy
 
 from .memory_mixins import DefaultMemory
-from ..state_plugins.plugin import SimStatePlugin
-from ..state_plugins.sim_action_object import SimActionObject
-from .. import sim_options
+from angr.state_plugins.plugin import SimStatePlugin
+from angr.state_plugins.sim_action_object import SimActionObject
+from angr import sim_options
 
 l = logging.getLogger(name=__name__)
 
@@ -1209,4 +1209,4 @@ class SimPacketsSlots(SimFileBase):
         raise SimMergeError("Widening the filesystem is unsupported")
 
 
-from ..errors import SimMergeError, SimFileError, SimSolverError
+from angr.errors import SimMergeError, SimFileError, SimSolverError

angr/storage/memory_mixins/__init__.py

@@ -1,160 +1,6 @@
-# pylint:disable=abstract-method,wrong-import-position,unused-argument,missing-class-docstring,arguments-differ
 from __future__ import annotations
-from typing import Tuple, Dict, Any, Optional
-from collections.abc import Iterable
-
-import claripy
-
-from ...state_plugins.plugin import SimStatePlugin
-from ...errors import SimMemoryError
-
-
-class MemoryMixin(SimStatePlugin):
-    SUPPORTS_CONCRETE_LOAD = False
-
-    def __init__(self, memory_id=None, endness="Iend_BE"):
-        super().__init__()
-        self.id = memory_id
-        self.endness = endness
-
-    def copy(self, memo):
-        o = type(self).__new__(type(self))
-        o.id = self.id
-        o.endness = self.endness
-        return o
-
-    @property
-    def category(self):
-        """
-        Return the category of this SimMemory instance. It can be one of the three following categories: reg, mem,
-        or file.
-        """
-
-        if self.id in ("reg", "mem"):
-            return self.id
-
-        if self.id.startswith("file"):
-            return "file"
-
-        if "_" in self.id:
-            return self.id.split("_")[0]
-
-        raise SimMemoryError(f'Unknown SimMemory category for memory_id "{self.id}"')
-
-    @property
-    def variable_key_prefix(self):
-        s = self.category
-        if s == "file":
-            return (s, self.id)
-        return (s,)
-
-    def find(self, addr, data, max_search, **kwargs):
-        pass
-
-    def _add_constraints(self, c, add_constraints=True, condition=None, **kwargs):
-        if add_constraints:
-            to_add = c & condition | ~condition if condition is not None else c
-            self.state.add_constraints(to_add)
-
-    def load(self, addr, size=None, **kwargs):
-        pass
-
-    def store(self, addr, data, **kwargs):
-        pass
-
-    def merge(self, others, merge_conditions, common_ancestor=None) -> bool:
-        pass
-
-    def compare(self, other) -> bool:
-        pass
-
-    def widen(self, others):
-        pass
-
-    def permissions(self, addr, permissions=None, **kwargs):
-        pass
-
-    def map_region(self, addr, length, permissions, init_zero=False, **kwargs):
-        pass
-
-    def unmap_region(self, addr, length, **kwargs):
-        pass
-
-    # Optional interface:
-    def concrete_load(self, addr, size, writing=False, **kwargs) -> memoryview:
-        """
-        Set SUPPORTS_CONCRETE_LOAD to True and implement concrete_load if reading concrete bytes is faster in this
-        memory model.
-
-        :param addr:    The address to load from.
-        :param size:    Size of the memory read.
-        :param writing:
-        :return:        A memoryview into the loaded bytes.
-        """
-        raise NotImplementedError
-
-    def erase(self, addr, size=None, **kwargs) -> None:
-        """
-        Set [addr:addr+size) to uninitialized. In many cases this will be faster than overwriting those locations with
-        new values. This is commonly used during static data flow analysis.
-
-        :param addr:    The address to start erasing.
-        :param size:    The number of bytes for erasing.
-        :return:        None
-        """
-        raise NotImplementedError
-
-    def _default_value(self, addr, size, name=None, inspect=True, events=True, key=None, **kwargs):
-        """
-        Override this method to provide default values for a variety of edge cases and base cases.
-
-        :param addr:    If this value is being filled to provide a default memory value, this will be its address.
-                        Otherwise, None.
-        :param size:    The size in bytes of the value to return
-        :param name:    A descriptive identifier for the value, for if a symbol is created.
-
-        The ``inspect``, ``events``, and ``key`` parameters are for ``state.solver.Unconstrained``, if it is used.
-        """
-
-    def _merge_values(self, values: Iterable[tuple[Any, Any]], merged_size: int, **kwargs) -> Any | None:
-        """
-        Override this method to provide value merging support.
-
-        :param values:          A collection of values with their merge conditions.
-        :param merged_size:     The size (in bytes) of the merged value.
-        :return:                The merged value, or None to skip merging of the current value.
-        """
-        raise NotImplementedError
-
-    def _merge_labels(self, labels: Iterable[dict], **kwargs) -> dict | None:
-        """
-        Override this method to provide label merging support.
-
-        :param labels:          A collection of labels.
-        :return:                The merged label, or None to skip merging of the current label.
-        """
-        raise NotImplementedError
-
-    def replace_all(self, old: claripy.ast.BV, new: claripy.ast.BV):
-        raise NotImplementedError
-
-    def _replace_all(self, addrs: Iterable[int], old: claripy.ast.BV, new: claripy.ast.BV):
-        raise NotImplementedError
-
-    def copy_contents(self, dst, src, size, condition=None, **kwargs):
-        """
-        Override this method to provide faster copying of large chunks of data.
-
-        :param dst:     The destination of copying.
-        :param src:     The source of copying.
-        :param size:    The size of copying.
-        :param condition:   The storing condition.
-        :param kwargs:      Other parameters.
-        :return:        None
-        """
-        raise NotImplementedError
-
 
+from angr.sim_state import SimState
 from .actions_mixin import ActionsMixinHigh, ActionsMixinLow
 from .address_concretization_mixin import AddressConcretizationMixin
 from .bvv_conversion_mixin import DataNormalizationMixin
@@ -188,7 +34,19 @@ from .paged_memory.paged_memory_mixin import (
 from .paged_memory.privileged_mixin import PrivilegedPagingMixin
 from .paged_memory.stack_allocation_mixin import StackAllocationMixin
 from .paged_memory.paged_memory_multivalue_mixin import PagedMemoryMultiValueMixin
-from .paged_memory.pages import *
+from .paged_memory.pages import (
+    CooperationBase,
+    MemoryObjectMixin,
+    ISPOMixin,
+    RefcountMixin,
+    PermissionsMixin,
+    HistoryTrackingMixin,
+    PageBase,
+    PageType,
+    ListPage,
+    MVListPage,
+    UltraPage,
+)
 
 from .slotted_memory import SlottedMemoryMixin
 from .regioned_memory import (
@@ -199,8 +57,10 @@ from .regioned_memory import (
     MemoryRegionMetaMixin,
     RegionedAddressConcretizationMixin,
 )
-from .keyvalue_memory import KeyValueMemoryMixin
-from .javavm_memory import JavaVmMemoryMixin
+from .keyvalue_memory_mixin import KeyValueMemoryMixin
+from .javavm_memory_mixin import JavaVmMemoryMixin
+
+# pylint:disable=missing-class-docstring
 
 
 class DefaultMemory(
@@ -335,7 +195,7 @@ class LabeledMemory(
     LabeledMemory is used in static analysis. It allows storing values with labels, such as `Definition`.
     """
 
-    def _default_value(self, addr, size, **kwargs):
+    def _default_value(self, addr, size, **kwargs):  # pylint:disable=arguments-differ
         # TODO: Make _default_value() a separate Mixin
 
         if kwargs.get("name", "").startswith("merge_uc_"):
@@ -356,7 +216,7 @@ class MultiValuedMemory(
     PagedMemoryMixin,
     PagedMemoryMultiValueMixin,
 ):
-    def _default_value(self, addr, size, **kwargs):
+    def _default_value(self, addr, size, **kwargs):  # pylint:disable=arguments-differ
         # TODO: Make _default_value() a separate Mixin
 
         if kwargs.get("name", "").startswith("merge_uc_"):
@@ -381,10 +241,77 @@ class JavaVmMemory(
     pass
 
 
-from angr.sim_state import SimState
-
 SimState.register_default("sym_memory", DefaultMemory)
 SimState.register_default("fast_memory", FastMemory)
 SimState.register_default("abs_memory", AbstractMemory)
 SimState.register_default("keyvalue_memory", KeyValueMemory)
 SimState.register_default("javavm_memory", JavaVmMemory)
+
+
+__all__ = (
+    "ActionsMixinHigh",
+    "ActionsMixinLow",
+    "AddressConcretizationMixin",
+    "DataNormalizationMixin",
+    "InspectMixinHigh",
+    "ConditionalMixin",
+    "ConvenientMappingsMixin",
+    "DefaultFillerMixin",
+    "SpecialFillerMixin",
+    "ExplicitFillerMixin",
+    "DirtyAddrsMixin",
+    "HexDumperMixin",
+    "LabelMergerMixin",
+    "MultiValueMergerMixin",
+    "NameResolutionMixin",
+    "SimplificationMixin",
+    "SimpleInterfaceMixin",
+    "SizeNormalizationMixin",
+    "SizeConcretizationMixin",
+    "SmartFindMixin",
+    "SymbolicMergerMixin",
+    "TopMergerMixin",
+    "UnderconstrainedMixin",
+    "UnwrapperMixin",
+    "ClemoryBackerMixin",
+    "ConcreteBackerMixin",
+    "DictBackerMixin",
+    "PagedMemoryMixin",
+    "ListPagesMixin",
+    "UltraPagesMixin",
+    "ListPagesWithLabelsMixin",
+    "MVListPagesMixin",
+    "MVListPagesWithLabelsMixin",
+    "PrivilegedPagingMixin",
+    "StackAllocationMixin",
+    "PagedMemoryMultiValueMixin",
+    "CooperationBase",
+    "MemoryObjectMixin",
+    "ISPOMixin",
+    "RefcountMixin",
+    "PermissionsMixin",
+    "HistoryTrackingMixin",
+    "PageBase",
+    "PageType",
+    "ListPage",
+    "MVListPage",
+    "UltraPage",
+    "SlottedMemoryMixin",
+    "RegionedMemoryMixin",
+    "RegionCategoryMixin",
+    "StaticFindMixin",
+    "AbstractMergerMixin",
+    "MemoryRegionMetaMixin",
+    "RegionedAddressConcretizationMixin",
+    "KeyValueMemoryMixin",
+    "JavaVmMemoryMixin",
+    "DefaultMemory",
+    "DefaultListPagesMemory",
+    "FastMemory",
+    "AbstractMemory",
+    "RegionedMemory",
+    "LabeledMemory",
+    "MultiValuedMemory",
+    "KeyValueMemory",
+    "JavaVmMemory",
+)

angr/storage/memory_mixins/actions_mixin.py

@@ -1,9 +1,9 @@
 from __future__ import annotations
 import claripy
 
-from ...state_plugins.sim_action import SimActionData, SimActionObject
-from ... import sim_options as o
-from . import MemoryMixin
+from angr.state_plugins.sim_action import SimActionData, SimActionObject
+from angr import sim_options as o
+from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
 
 class ActionsMixinHigh(MemoryMixin):

angr/storage/memory_mixins/address_concretization_mixin.py

@@ -1,13 +1,13 @@
 from __future__ import annotations
 import claripy
 
-from . import MemoryMixin
-from ... import sim_options as options
-from ... import concretization_strategies
-from ...sim_state_options import SimStateOptions
-from ...state_plugins.inspect import BP_BEFORE, BP_AFTER
-from ...errors import SimMergeError, SimUnsatError, SimMemoryAddressError, SimMemoryError
-from ...storage import DUMMY_SYMBOLIC_READ_VALUE
+from angr.storage.memory_mixins.memory_mixin import MemoryMixin
+from angr import sim_options as options
+from angr import concretization_strategies
+from angr.sim_state_options import SimStateOptions
+from angr.state_plugins.inspect import BP_BEFORE, BP_AFTER
+from angr.errors import SimMergeError, SimUnsatError, SimMemoryAddressError, SimMemoryError
+from angr.storage import DUMMY_SYMBOLIC_READ_VALUE
 
 
 class MultiwriteAnnotation(claripy.Annotation):

angr/storage/memory_mixins/bvv_conversion_mixin.py

@@ -2,7 +2,7 @@ from __future__ import annotations
 import logging
 import claripy
 
-from angr.storage.memory_mixins import MemoryMixin
+from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
 l = logging.getLogger(__name__)
 
@@ -70,4 +70,4 @@ class DataNormalizationMixin(MemoryMixin):
             return raw_to_bv()
 
 
-from ...errors import SimMemoryError
+from angr.errors import SimMemoryError

angr/storage/memory_mixins/clouseau_mixin.py

@@ -1,5 +1,6 @@
 from __future__ import annotations
-from . import MemoryMixin
+
+from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
 
 class InspectMixinHigh(MemoryMixin):
@@ -129,4 +130,4 @@ class InspectMixinHigh(MemoryMixin):
         super()._add_constraints(c, add_constraints=add_constraints, inspect=inspect, **kwargs)
 
 
-from ...state_plugins.inspect import BP_BEFORE, BP_AFTER
+from angr.state_plugins.inspect import BP_BEFORE, BP_AFTER

angr/storage/memory_mixins/conditional_store_mixin.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 import claripy
 
-from . import MemoryMixin
+from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
 
 class ConditionalMixin(MemoryMixin):