angr 9.2.119__py3-none-manylinux2014_aarch64.whl → 9.2.120__py3-none-manylinux2014_aarch64.whl

angr/state_plugins/plugin.py

@@ -1,10 +1,11 @@
 from __future__ import annotations
+
 from typing import cast
 
-import angr  # For type annotations; pylint: disable=unused-import
 import logging
 
-from ..misc.ux import once
+import angr
+from angr.misc.ux import once
 
 l = logging.getLogger(name=__name__)
 

angr/state_plugins/posix.py

@@ -5,8 +5,8 @@ import claripy
 
 from .plugin import SimStatePlugin
 from .filesystem import SimMount, Stat
-from ..storage.file import SimFile, SimPacketsStream, Flags, SimFileDescriptor, SimFileDescriptorDuplex
-from .. import sim_options as options
+from angr.storage.file import SimFile, SimPacketsStream, Flags, SimFileDescriptor, SimFileDescriptorDuplex
+from angr import sim_options as options
 
 l = logging.getLogger(name=__name__)
 
@@ -700,4 +700,4 @@ from angr.sim_state import SimState
 
 SimState.register_default("posix", SimSystemPosix)
 
-from ..errors import SimPosixError, SimSolverError, SimMergeError, SimMemoryError
+from angr.errors import SimPosixError, SimSolverError, SimMergeError, SimMemoryError

angr/state_plugins/preconstrainer.py

@@ -4,8 +4,8 @@ import logging
 import claripy
 
 from .plugin import SimStatePlugin
-from .. import sim_options as o
-from ..errors import AngrError
+from angr import sim_options as o
+from angr.errors import AngrError
 
 
 l = logging.getLogger(name=__name__)
@@ -55,8 +55,8 @@ class SimStatePreconstrainer(SimStatePlugin):
         """
         if not isinstance(value, claripy.ast.Base):
             value = claripy.BVV(value, len(variable))
-        elif value.op != "BVV":
-            raise ValueError("Passed a value to preconstrain that was not a BVV or a string")
+        elif value.op not in ["BVV", "FPV"]:
+            raise ValueError("Passed a value to preconstrain that was not a BVV or FPV or a string")
 
         if not variable.is_leaf():
             l.warning(

angr/state_plugins/scratch.py

@@ -167,10 +167,10 @@ class SimStateScratch(SimStatePlugin):
 
 # pylint:disable=wrong-import-position
 from .sim_action import SimActionObject, SimActionData
-from ..errors import SimValueError, SimMissingTempError
-from .. import sim_options as o
+from angr.errors import SimValueError, SimMissingTempError
+from angr import sim_options as o
 from .inspect import BP_AFTER, BP_BEFORE
 
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 SimState.register_default("scratch", SimStateScratch)

angr/state_plugins/sim_action_object.py

@@ -9,7 +9,7 @@ import claripy
 from angr import sim_options as o
 from angr.errors import SimActionError
 from .sim_action import SimActionData, SimActionOperation
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 if typing.TYPE_CHECKING:
     from claripy.annotation import Annotation

angr/state_plugins/solver.py

@@ -346,23 +346,19 @@ class SimSolver(SimStatePlugin):
         """
         if o.SYMBOLIC_INITIAL_VALUES in self.state.options:
             # Return a symbolic value
-            if o.ABSTRACT_MEMORY in self.state.options:
-                l.debug("Creating new top StridedInterval")
-                r = claripy.TSI(bits=bits, name=name, uninitialized=uninitialized, **kwargs)
-            else:
-                l.debug("Creating new unconstrained BV named %s", name)
-                r = self.BVS(
-                    name,
-                    bits,
-                    uninitialized=uninitialized,
-                    key=key,
-                    eternal=eternal,
-                    inspect=inspect,
-                    events=events,
-                    **kwargs,
-                )
-                if uc_alloc_depth is not None:
-                    self.state.uc_manager.set_alloc_depth(r, uc_alloc_depth)
+            l.debug("Creating new unconstrained BV named %s", name)
+            r = self.BVS(
+                name,
+                bits,
+                uninitialized=uninitialized,
+                key=key,
+                eternal=eternal,
+                inspect=inspect,
+                events=events,
+                **kwargs,
+            )
+            if uc_alloc_depth is not None:
+                self.state.uc_manager.set_alloc_depth(r, uc_alloc_depth)
 
             return r
         # Return a default value, aka. 0
@@ -416,7 +412,7 @@ class SimSolver(SimStatePlugin):
                 or min != r.args[1]
                 or max != r.args[2]
                 or stride != r.args[3]
-                or uninitialized != r.args[4]
+                or uninitialized != r.uninitialized
                 or bool(explicit_name) ^ (r.args[0] == name)
             ):
                 l.warning("Variable %s being retrieved with different settings than it was tracked with", name)

angr/state_plugins/symbolizer.py

@@ -4,11 +4,10 @@ import claripy
 import struct
 
 from .plugin import SimStatePlugin
-from ..storage.memory_mixins import PagedMemoryMixin
+from angr.storage.memory_mixins import PagedMemoryMixin
 
 
 l = logging.getLogger(name=__name__)
-l.setLevel("DEBUG")
 
 
 def _mem_write_cb(s):
@@ -286,6 +285,6 @@ class SimSymbolizer(SimStatePlugin):  # pylint:disable=abstract-method
         return sc
 
 
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 SimState.register_default("symbolizer", SimSymbolizer)

angr/state_plugins/uc_manager.py

@@ -4,7 +4,7 @@ import logging
 import claripy
 
 from .plugin import SimStatePlugin
-from ..errors import SimUCManagerAllocationError
+from angr.errors import SimUCManagerAllocationError
 
 l = logging.getLogger(name=__name__)
 

angr/state_plugins/unicorn_engine.py

@@ -17,10 +17,10 @@ import pyvex
 from angr.engines.vex.claripy import ccall
 from angr.sim_state import SimState
 
-from .. import sim_options as options
-from ..engines.vex.claripy.irop import operations as irop_ops
-from ..errors import SimMemoryError, SimSegfaultError, SimUnicornError, SimUnicornUnsupport, SimValueError
-from ..misc.testing import is_testing
+from angr import sim_options as options
+from angr.engines.vex.claripy.irop import operations as irop_ops
+from angr.errors import SimMemoryError, SimSegfaultError, SimUnicornError, SimUnicornUnsupport, SimValueError
+from angr.misc.testing import is_testing
 from .plugin import SimStatePlugin
 
 l = logging.getLogger(name=__name__)

angr/state_plugins/view.py

@@ -331,7 +331,7 @@ class StructMode:
             self.__getattr__(k).store(v)
 
 
-from ..sim_type import ALL_TYPES, SimTypeFixedSizeArray, SimTypePointer
+from angr.sim_type import ALL_TYPES, SimTypeFixedSizeArray, SimTypePointer
 
 SimMemView.types = ALL_TYPES  # identity purposefully here
 

angr/storage/__init__.py

@@ -1,10 +1,16 @@
-# misc
 from __future__ import annotations
 
 DUMMY_SYMBOLIC_READ_VALUE = 0xC0DEB4BE
 
-# imports
-
 from .file import SimFile
 from .memory_object import SimMemoryObject
 from .memory_mixins import MemoryMixin, DefaultMemory
+
+
+__all__ = (
+    "DUMMY_SYMBOLIC_READ_VALUE",
+    "SimFile",
+    "SimMemoryObject",
+    "MemoryMixin",
+    "DefaultMemory",
+)

angr/storage/file.py

@@ -5,9 +5,9 @@ import itertools
 import claripy
 
 from .memory_mixins import DefaultMemory
-from ..state_plugins.plugin import SimStatePlugin
-from ..state_plugins.sim_action_object import SimActionObject
-from .. import sim_options
+from angr.state_plugins.plugin import SimStatePlugin
+from angr.state_plugins.sim_action_object import SimActionObject
+from angr import sim_options
 
 l = logging.getLogger(name=__name__)
 
@@ -1209,4 +1209,4 @@ class SimPacketsSlots(SimFileBase):
         raise SimMergeError("Widening the filesystem is unsupported")
 
 
-from ..errors import SimMergeError, SimFileError, SimSolverError
+from angr.errors import SimMergeError, SimFileError, SimSolverError

angr/storage/memory_mixins/__init__.py

@@ -1,12 +1,12 @@
 # pylint:disable=abstract-method,wrong-import-position,unused-argument,missing-class-docstring,arguments-differ
 from __future__ import annotations
-from typing import Tuple, Dict, Any, Optional
+from typing import Any
 from collections.abc import Iterable
 
 import claripy
 
-from ...state_plugins.plugin import SimStatePlugin
-from ...errors import SimMemoryError
+from angr.state_plugins.plugin import SimStatePlugin
+from angr.errors import SimMemoryError
 
 
 class MemoryMixin(SimStatePlugin):
@@ -188,7 +188,19 @@ from .paged_memory.paged_memory_mixin import (
 from .paged_memory.privileged_mixin import PrivilegedPagingMixin
 from .paged_memory.stack_allocation_mixin import StackAllocationMixin
 from .paged_memory.paged_memory_multivalue_mixin import PagedMemoryMultiValueMixin
-from .paged_memory.pages import *
+from .paged_memory.pages import (
+    CooperationBase,
+    MemoryObjectMixin,
+    ISPOMixin,
+    RefcountMixin,
+    PermissionsMixin,
+    HistoryTrackingMixin,
+    PageBase,
+    PageType,
+    ListPage,
+    MVListPage,
+    UltraPage,
+)
 
 from .slotted_memory import SlottedMemoryMixin
 from .regioned_memory import (
@@ -199,8 +211,8 @@ from .regioned_memory import (
     MemoryRegionMetaMixin,
     RegionedAddressConcretizationMixin,
 )
-from .keyvalue_memory import KeyValueMemoryMixin
-from .javavm_memory import JavaVmMemoryMixin
+from .keyvalue_memory_mixin import KeyValueMemoryMixin
+from .javavm_memory_mixin import JavaVmMemoryMixin
 
 
 class DefaultMemory(
@@ -388,3 +400,73 @@ SimState.register_default("fast_memory", FastMemory)
 SimState.register_default("abs_memory", AbstractMemory)
 SimState.register_default("keyvalue_memory", KeyValueMemory)
 SimState.register_default("javavm_memory", JavaVmMemory)
+
+
+__all__ = (
+    "MemoryMixin",
+    "ActionsMixinHigh",
+    "ActionsMixinLow",
+    "AddressConcretizationMixin",
+    "DataNormalizationMixin",
+    "InspectMixinHigh",
+    "ConditionalMixin",
+    "ConvenientMappingsMixin",
+    "DefaultFillerMixin",
+    "SpecialFillerMixin",
+    "ExplicitFillerMixin",
+    "DirtyAddrsMixin",
+    "HexDumperMixin",
+    "LabelMergerMixin",
+    "MultiValueMergerMixin",
+    "NameResolutionMixin",
+    "SimplificationMixin",
+    "SimpleInterfaceMixin",
+    "SizeNormalizationMixin",
+    "SizeConcretizationMixin",
+    "SmartFindMixin",
+    "SymbolicMergerMixin",
+    "TopMergerMixin",
+    "UnderconstrainedMixin",
+    "UnwrapperMixin",
+    "ClemoryBackerMixin",
+    "ConcreteBackerMixin",
+    "DictBackerMixin",
+    "PagedMemoryMixin",
+    "ListPagesMixin",
+    "UltraPagesMixin",
+    "ListPagesWithLabelsMixin",
+    "MVListPagesMixin",
+    "MVListPagesWithLabelsMixin",
+    "PrivilegedPagingMixin",
+    "StackAllocationMixin",
+    "PagedMemoryMultiValueMixin",
+    "CooperationBase",
+    "MemoryObjectMixin",
+    "ISPOMixin",
+    "RefcountMixin",
+    "PermissionsMixin",
+    "HistoryTrackingMixin",
+    "PageBase",
+    "PageType",
+    "ListPage",
+    "MVListPage",
+    "UltraPage",
+    "SlottedMemoryMixin",
+    "RegionedMemoryMixin",
+    "RegionCategoryMixin",
+    "StaticFindMixin",
+    "AbstractMergerMixin",
+    "MemoryRegionMetaMixin",
+    "RegionedAddressConcretizationMixin",
+    "KeyValueMemoryMixin",
+    "JavaVmMemoryMixin",
+    "DefaultMemory",
+    "DefaultListPagesMemory",
+    "FastMemory",
+    "AbstractMemory",
+    "RegionedMemory",
+    "LabeledMemory",
+    "MultiValuedMemory",
+    "KeyValueMemory",
+    "JavaVmMemory",
+)

angr/storage/memory_mixins/actions_mixin.py

@@ -1,8 +1,8 @@
 from __future__ import annotations
 import claripy
 
-from ...state_plugins.sim_action import SimActionData, SimActionObject
-from ... import sim_options as o
+from angr.state_plugins.sim_action import SimActionData, SimActionObject
+from angr import sim_options as o
 from . import MemoryMixin
 
 

angr/storage/memory_mixins/address_concretization_mixin.py

@@ -2,12 +2,12 @@ from __future__ import annotations
 import claripy
 
 from . import MemoryMixin
-from ... import sim_options as options
-from ... import concretization_strategies
-from ...sim_state_options import SimStateOptions
-from ...state_plugins.inspect import BP_BEFORE, BP_AFTER
-from ...errors import SimMergeError, SimUnsatError, SimMemoryAddressError, SimMemoryError
-from ...storage import DUMMY_SYMBOLIC_READ_VALUE
+from angr import sim_options as options
+from angr import concretization_strategies
+from angr.sim_state_options import SimStateOptions
+from angr.state_plugins.inspect import BP_BEFORE, BP_AFTER
+from angr.errors import SimMergeError, SimUnsatError, SimMemoryAddressError, SimMemoryError
+from angr.storage import DUMMY_SYMBOLIC_READ_VALUE
 
 
 class MultiwriteAnnotation(claripy.Annotation):

angr/storage/memory_mixins/bvv_conversion_mixin.py

@@ -70,4 +70,4 @@ class DataNormalizationMixin(MemoryMixin):
             return raw_to_bv()
 
 
-from ...errors import SimMemoryError
+from angr.errors import SimMemoryError

angr/storage/memory_mixins/clouseau_mixin.py

@@ -129,4 +129,4 @@ class InspectMixinHigh(MemoryMixin):
         super()._add_constraints(c, add_constraints=add_constraints, inspect=inspect, **kwargs)
 
 
-from ...state_plugins.inspect import BP_BEFORE, BP_AFTER
+from angr.state_plugins.inspect import BP_BEFORE, BP_AFTER

angr/storage/memory_mixins/convenient_mappings_mixin.py

@@ -5,8 +5,8 @@ import logging
 import claripy
 
 from angr import sim_options as options
-from ...utils.cowdict import ChainMapCOW
-from ...errors import SimMemoryError, SimMemoryMissingError
+from angr.utils.cowdict import ChainMapCOW
+from angr.errors import SimMemoryError, SimMemoryMissingError
 from . import MemoryMixin
 
 l = logging.getLogger(name=__name__)

angr/storage/memory_mixins/default_filler_mixin.py

@@ -4,9 +4,9 @@ import logging
 import claripy
 
 from . import MemoryMixin
-from ... import sim_options as options
-from ...misc.ux import once
-from ...errors import SimMemoryMissingError
+from angr import sim_options as options
+from angr.misc.ux import once
+from angr.errors import SimMemoryMissingError
 
 l = logging.getLogger(__name__)
 

angr/storage/memory_mixins/hex_dumper_mixin.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 import string
 
-from ...errors import SimValueError
+from angr.errors import SimValueError
 from . import MemoryMixin
 import contextlib
 

angr/storage/memory_mixins/{javavm_memory/javavm_memory_mixin.py → javavm_memory_mixin.py}

@@ -5,9 +5,9 @@ import os
 
 import claripy
 
-from .... import concretization_strategies
-from ....errors import SimUnsatError, SimMemoryAddressError
-from ....engines.soot.values import (
+from angr import concretization_strategies
+from angr.errors import SimUnsatError, SimMemoryAddressError
+from angr.engines.soot.values import (
     SimSootValue_ArrayRef,
     SimSootValue_ArrayBaseRef,
     SimSootValue_InstanceFieldRef,
@@ -16,13 +16,18 @@ from ....engines.soot.values import (
     SimSootValue_StaticFieldRef,
     SimSootValue_StringRef,
 )
-from .. import MemoryMixin
+from . import MemoryMixin
 
 
 l = logging.getLogger(name=__name__)
 
 
+# pylint: disable=too-many-positional-arguments
+
+
 class JavaVmMemoryMixin(MemoryMixin):
+    """A memory mixin for JavaVM memory."""
+
     def __init__(
         self,
         memory_id="mem",
@@ -38,7 +43,7 @@ class JavaVmMemoryMixin(MemoryMixin):
 
         self._stack = [] if stack is None else stack
         # delayed import
-        from .. import KeyValueMemory
+        from . import KeyValueMemory  # pylint: disable=import-outside-toplevel
 
         self.heap = KeyValueMemory("mem") if heap is None else heap
         self.vm_static_table = KeyValueMemory("mem") if vm_static_table is None else vm_static_table
@@ -81,7 +86,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         else:
             l.error("Unknown addr type %s", addr)
 
-    def load(self, addr, frame=0, none_if_missing=False):  # pylint: disable=arguments-differ
+    def load(self, addr, frame=0, none_if_missing=False):  # pylint: disable=arguments-differ,arguments-renamed
         if type(addr) is SimSootValue_Local:
             cstack = self._stack[-1 + (-1 * frame)]
             return cstack.load(addr.id, none_if_missing=none_if_missing)
@@ -118,7 +123,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         return None
 
     def push_stack_frame(self):
-        from .. import KeyValueMemory
+        from . import KeyValueMemory  # pylint: disable=import-outside-toplevel
 
         self._stack.append(KeyValueMemory("mem"))
 
@@ -379,11 +384,9 @@ class JavaVmMemoryMixin(MemoryMixin):
     def merge(self, others, merge_conditions, common_ancestor=None):  # pylint: disable=unused-argument
         l.warning("Merging is not implemented for JavaVM memory!")
 
-    def widen(self, others):  # pylint: disable=unused-argument
+    def widen(self, others):  # pylint: disable=no-self-use,unused-argument
         l.warning("Widening is not implemented for JavaVM memory!")
 
-    def _find(
-        self, addr, what, max_search=None, max_symbolic_bytes=None, default=None
-    ):  # pylint: disable=unused-argument
+    # pylint: disable=no-self-use,unused-argument
+    def _find(self, addr, what, max_search=None, max_symbolic_bytes=None, default=None):
         l.warning("Find is not implemented for JavaVM memory!")
-        return

angr/storage/memory_mixins/{keyvalue_memory/keyvalue_memory_mixin.py → keyvalue_memory_mixin.py}

@@ -1,8 +1,11 @@
 from __future__ import annotations
-from .. import MemoryMixin
+
+from . import MemoryMixin
 
 
 class TypedVariable:
+    """TypedVariable is a simple class that holds a value and a type."""
+
     __slots__ = (
         "type",
         "value",
@@ -14,18 +17,20 @@ class TypedVariable:
 
 
 class KeyValueMemoryMixin(MemoryMixin):
+    """KeyValueMemoryMixin is a mixin that provides a simple key-value store for memory."""
+
     def __init__(self, *args, **kwargs):
         super().__init__(*args, **kwargs)
 
         self._store = {}
 
-    def load(self, key, none_if_missing=False, **kwargs):
-        if none_if_missing and key not in self._store:
+    def load(self, addr, size=None, none_if_missing=False, **kwargs):  # pylint: disable=unused-argument
+        if none_if_missing and addr not in self._store:
             return None
-        return self._store[key].value
+        return self._store[addr].value
 
-    def store(self, key, data, type_=None, **kwargs):
-        self._store[key] = TypedVariable(type_, data)
+    def store(self, addr, data, type_=None, **kwargs):
+        self._store[addr] = TypedVariable(type_, data)
 
     @MemoryMixin.memo
     def copy(self, memo):

angr/storage/memory_mixins/name_resolution_mixin.py

@@ -15,7 +15,7 @@ class NameResolutionMixin(MemoryMixin):
 
     def _resolve_location_name(self, name, is_write=False):
         # Delayed load so SimMemory does not rely on SimEngines
-        from ...engines.vex.claripy.ccall import _get_flags
+        from angr.engines.vex.claripy.ccall import _get_flags
 
         if self.category == "reg":
             if self.state.arch.name in ("X86", "AMD64"):
@@ -64,4 +64,4 @@ class NameResolutionMixin(MemoryMixin):
         return super().load(addr, size=size, **kwargs)
 
 
-from ...errors import SimMemoryError
+from angr.errors import SimMemoryError

angr/storage/memory_mixins/paged_memory/paged_memory_mixin.py

@@ -9,7 +9,7 @@ import claripy
 
 from angr.storage.memory_mixins import MemoryMixin
 from angr.storage.memory_mixins.paged_memory.pages import PageType, ListPage, UltraPage, MVListPage
-from ....errors import SimMemoryError
+from angr.errors import SimMemoryError
 
 # yeet
 ffi = cffi.FFI()

angr/storage/memory_mixins/paged_memory/paged_memory_multivalue_mixin.py

@@ -1,5 +1,5 @@
 from __future__ import annotations
-from .. import MemoryMixin
+from angr.storage.memory_mixins import MemoryMixin
 
 
 class PagedMemoryMultiValueMixin(MemoryMixin):

angr/storage/memory_mixins/paged_memory/pages/__init__.py

@@ -30,3 +30,18 @@ PageType = typing.TypeVar("PageType", bound=PageBase)
 from .list_page import ListPage
 from .mv_list_page import MVListPage
 from .ultra_page import UltraPage
+
+
+__all__ = (
+    "CooperationBase",
+    "MemoryObjectMixin",
+    "ISPOMixin",
+    "RefcountMixin",
+    "PermissionsMixin",
+    "HistoryTrackingMixin",
+    "PageBase",
+    "PageType",
+    "ListPage",
+    "MVListPage",
+    "UltraPage",
+)

angr/storage/memory_mixins/paged_memory/pages/mv_list_page.py

@@ -5,7 +5,7 @@ from typing import Union, Any
 from collections.abc import Callable
 
 from angr.utils.dynamic_dictlist import DynamicDictList
-from .....storage.memory_object import SimMemoryObject, SimLabeledMemoryObject
+from angr.storage.memory_object import SimMemoryObject, SimLabeledMemoryObject
 from . import PageBase
 from .cooperation import MemoryObjectSetMixin
 

angr/storage/memory_mixins/paged_memory/pages/ultra_page.py

@@ -8,7 +8,7 @@ from sortedcontainers import SortedDict
 
 import claripy
 
-from .....errors import SimMemoryError
+from angr.errors import SimMemoryError
 from . import PageBase
 from .cooperation import MemoryObjectMixin, SimMemoryObject
 

angr/storage/memory_mixins/paged_memory/stack_allocation_mixin.py

@@ -2,8 +2,8 @@ from __future__ import annotations
 import logging
 
 from .paged_memory_mixin import PagedMemoryMixin
-from ....errors import SimSegfaultException, SimMemoryError
-from ....sim_options import STRICT_PAGE_ACCESS
+from angr.errors import SimSegfaultException, SimMemoryError
+from angr.sim_options import STRICT_PAGE_ACCESS
 
 l = logging.getLogger(__name__)
 

angr/storage/memory_mixins/regioned_memory/__init__.py

@@ -1,7 +1,17 @@
 from __future__ import annotations
+
 from .regioned_memory_mixin import RegionedMemoryMixin
 from .region_category_mixin import RegionCategoryMixin
 from .static_find_mixin import StaticFindMixin
 from .abstract_merger_mixin import AbstractMergerMixin
 from .region_meta_mixin import MemoryRegionMetaMixin
 from .regioned_address_concretization_mixin import RegionedAddressConcretizationMixin
+
+__all__ = (
+    "RegionedMemoryMixin",
+    "RegionCategoryMixin",
+    "StaticFindMixin",
+    "AbstractMergerMixin",
+    "MemoryRegionMetaMixin",
+    "RegionedAddressConcretizationMixin",
+)

angr/storage/memory_mixins/regioned_memory/abstract_merger_mixin.py

@@ -5,7 +5,7 @@ from collections.abc import Iterable
 from typing import Any
 
 
-from .. import MemoryMixin
+from angr.storage.memory_mixins import MemoryMixin
 
 l = logging.getLogger(name=__name__)