angr 9.2.117__py3-none-win_amd64.whl → 9.2.118__py3-none-win_amd64.whl

angr/engines/light/engine.py

@@ -1,4 +1,5 @@
 # pylint:disable=no-self-use,isinstance-second-argument-not-valid-type,unused-argument
+from __future__ import annotations
 from typing import Any
 import struct
 import re
@@ -15,6 +16,7 @@ from ...engines.vex.claripy.irop import UnsupportedIROpError, SimOperationError,
 from ...code_location import CodeLocation
 from ...utils.constants import DEFAULT_STATEMENT
 from ..engine import SimEngine
+import contextlib
 
 
 class SimEngineLightMixin:
@@ -43,7 +45,7 @@ class SimEngineLightMixin:
         :param size:    The size (in bits) of the TOP value.
         :return:        A TOP value.
         """
-        raise NotImplementedError()
+        raise NotImplementedError
 
     @staticmethod
     def sp_offset(bits: int, offset: int):
@@ -66,17 +68,17 @@ class SimEngineLightMixin:
             # Local variable
             if spoffset_expr.op == "BVS":
                 return 0
-            elif spoffset_expr.op == "__add__":
+            if spoffset_expr.op == "__add__":
                 if len(spoffset_expr.args) == 1:
                     # Unexpected but fine
                     return 0
-                elif isinstance(spoffset_expr.args[1], claripy.ast.Base) and spoffset_expr.args[1].op == "BVV":
+                if isinstance(spoffset_expr.args[1], claripy.ast.Base) and spoffset_expr.args[1].op == "BVV":
                     return spoffset_expr.args[1].args[0]
             elif spoffset_expr.op == "__sub__":
                 if len(spoffset_expr.args) == 1:
                     # Unexpected but fine
                     return 0
-                elif isinstance(spoffset_expr.args[1], claripy.ast.Base) and spoffset_expr.args[1].op == "BVV":
+                if isinstance(spoffset_expr.args[1], claripy.ast.Base) and spoffset_expr.args[1].op == "BVV":
                     return -spoffset_expr.args[1].args[0] & ((1 << spoffset_expr.size()) - 1)
         return None
 
@@ -112,7 +114,7 @@ class SimEngineLight(
         self._process(state, None, block=kwargs.pop("block", None), whitelist=kwargs.pop("whitelist", None))
 
     def _process(self, new_state, successors, *args, **kwargs):
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def _check(self, state, *args, **kwargs):
         return True
@@ -195,12 +197,11 @@ class SimEngineLightVEXMixin(SimEngineLightMixin):
     #
 
     def _handle_Stmt(self, stmt):
-        handler = "_handle_%s" % type(stmt).__name__
+        handler = f"_handle_{type(stmt).__name__}"
         if hasattr(self, handler):
             getattr(self, handler)(stmt)
-        elif type(stmt).__name__ not in ("IMark", "AbiHint"):
-            if self.l is not None:
-                self.l.error("Unsupported statement type %s.", type(stmt).__name__)
+        elif type(stmt).__name__ not in ("IMark", "AbiHint") and self.l is not None:
+            self.l.error("Unsupported statement type %s.", type(stmt).__name__)
 
     # synchronize with function _handle_WrTmpData()
     def _handle_WrTmp(self, stmt):
@@ -237,18 +238,16 @@ class SimEngineLightVEXMixin(SimEngineLightMixin):
     #
 
     def _expr(self, expr):
-        handler = "_handle_%s" % type(expr).__name__
+        handler = f"_handle_{type(expr).__name__}"
         if hasattr(self, handler):
             return getattr(self, handler)(expr)
-        elif self.l is not None:
+        if self.l is not None:
             self.l.error("Unsupported expression type %s.", type(expr).__name__)
         return None
 
     def _handle_Triop(self, expr: pyvex.IRExpr.Triop):  # pylint: disable=useless-return
         handler = None
-        if expr.op.startswith("Iop_AddF"):
-            handler = "_handle_AddF"
-        elif expr.op.startswith("Iop_SubF"):
+        if expr.op.startswith("Iop_AddF") or expr.op.startswith("Iop_SubF"):
             handler = "_handle_AddF"
         elif expr.op.startswith("Iop_MulF"):
             handler = "_handle_MulF"
@@ -319,20 +318,17 @@ class SimEngineLightVEXMixin(SimEngineLightMixin):
         cond = self._expr(expr.cond)
         if cond is True:
             return self._expr(expr.iftrue)
-        elif cond is False:
+        if cond is False:
             return self._expr(expr.iffalse)
-        else:
-            return None
+        return None
 
     def _handle_Unop(self, expr):
         handler = None
 
         # All conversions are handled by the Conversion handler
         simop = None
-        try:
+        with contextlib.suppress(UnsupportedIROpError, SimOperationError):
             simop = vexop_to_simop(expr.op)
-        except (UnsupportedIROpError, SimOperationError):
-            pass
 
         if simop is not None and simop.op_attrs.get("conversion", None):
             handler = "_handle_Conversion"
@@ -352,10 +348,9 @@ class SimEngineLightVEXMixin(SimEngineLightMixin):
 
         if handler is not None and hasattr(self, handler):
             return getattr(self, handler)(expr)
-        else:
-            if self.l is not None:
-                self.l.error("Unsupported Unop %s.", expr.op)
-            return None
+        if self.l is not None:
+            self.l.error("Unsupported Unop %s.", expr.op)
+        return None
 
     def _handle_Binop(self, expr: pyvex.IRExpr.Binop):
         handler = None
@@ -434,16 +429,15 @@ class SimEngineLightVEXMixin(SimEngineLightMixin):
             if vector_size is not None and vector_count is not None:
                 return getattr(self, handler)(expr, vector_size, vector_count)
             return getattr(self, handler)(expr)
-        else:
-            if once(expr.op) and self.l is not None:
-                self.l.warning("Unsupported Binop %s.", expr.op)
+        if once(expr.op) and self.l is not None:
+            self.l.warning("Unsupported Binop %s.", expr.op)
 
         return None
 
     def _handle_CCall(self, expr):  # pylint:disable=useless-return
         if self.l is not None:
             self.l.warning("Unsupported expression type CCall with callee %s.", str(expr.cee))
-        return None
+        return
 
     #
     # Unary operation handlers
@@ -479,11 +473,10 @@ class SimEngineLightVEXMixin(SimEngineLightMixin):
             if expr_.size() > to_size:
                 # truncation
                 return expr_[to_size - 1 : 0]
-            elif expr_.size() < to_size:
+            if expr_.size() < to_size:
                 # extension
                 return claripy.ZeroExt(to_size - expr_.size(), expr_)
-            else:
-                return expr_
+            return expr_
 
         return self._top(to_size)
 
@@ -622,14 +615,13 @@ class SimEngineLightVEXMixin(SimEngineLightMixin):
             return claripy.Concat(
                 claripy.Extract(remainder_size - 1, 0, remainder), claripy.Extract(quotient_size - 1, 0, quotient)
             )
-        else:
-            quotient = expr_0 // claripy.ZeroExt(from_size - to_size, expr_1)
-            remainder = expr_0 % claripy.ZeroExt(from_size - to_size, expr_1)
-            quotient_size = to_size
-            remainder_size = to_size
-            return claripy.Concat(
-                claripy.Extract(remainder_size - 1, 0, remainder), claripy.Extract(quotient_size - 1, 0, quotient)
-            )
+        quotient = expr_0 // claripy.ZeroExt(from_size - to_size, expr_1)
+        remainder = expr_0 % claripy.ZeroExt(from_size - to_size, expr_1)
+        quotient_size = to_size
+        remainder_size = to_size
+        return claripy.Concat(
+            claripy.Extract(remainder_size - 1, 0, remainder), claripy.Extract(quotient_size - 1, 0, quotient)
+        )
 
     def _handle_Div(self, expr):
         args, r = self._binop_get_args(expr)
@@ -865,7 +857,9 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
         self.tmps = {}
         self.block: ailment.Block = block
         self.state = state
-        self.arch = state.arch
+        if self.arch is None:
+            # we only access state.arch if the arch of this engine itself is not previously configured
+            self.arch = state.arch
 
         self._process_Stmt(whitelist=whitelist)
 
@@ -893,12 +887,12 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
             expr_type_name += "Expr"
 
         h = None
-        handler = "_handle_%s" % expr_type_name
+        handler = f"_handle_{expr_type_name}"
         if hasattr(self, handler):
             h = getattr(self, handler)
 
         if h is None:
-            handler = "_ail_handle_%s" % expr_type_name
+            handler = f"_ail_handle_{expr_type_name}"
             if hasattr(self, handler):
                 h = getattr(self, handler)
 
@@ -926,31 +920,33 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
     #
 
     def _handle_Stmt(self, stmt):
-        handler = "_handle_%s" % type(stmt).__name__
+        handler = f"_handle_{type(stmt).__name__}"
         if hasattr(self, handler):
-            getattr(self, handler)(stmt)
-            return
+            return getattr(self, handler)(stmt)
 
         # compatibility
-        old_handler = "_ail_handle_%s" % type(stmt).__name__
+        old_handler = f"_ail_handle_{type(stmt).__name__}"
         if hasattr(self, old_handler):
-            getattr(self, old_handler)(stmt)
-            return
+            return getattr(self, old_handler)(stmt)
 
         if self.l is not None:
             self.l.warning("Unsupported statement type %s.", type(stmt).__name__)
+        return None
+
+    def _ail_handle_Assignment(self, stmt):
+        pass
 
     def _ail_handle_Label(self, stmt):
         pass
 
     def _ail_handle_Jump(self, stmt):
-        raise NotImplementedError("Please implement the Jump handler with your own logic.")
+        pass
 
     def _ail_handle_Call(self, stmt):
-        raise NotImplementedError("Please implement the Call handler with your own logic.")
+        pass
 
     def _ail_handle_Return(self, stmt):
-        raise NotImplementedError("Please implement the Return handler with your own logic.")
+        pass
 
     #
     # Expression handlers
@@ -962,6 +958,9 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
     def _ail_handle_Const(self, expr):  # pylint:disable=no-self-use
         return expr.value
 
+    def _ail_handle_StackBaseOffset(self, expr: ailment.Expr.StackBaseOffset):
+        return expr
+
     def _ail_handle_Tmp(self, expr):
         tmp_idx = expr.tmp_idx
 
@@ -970,11 +969,13 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
         except KeyError:
             return None
 
-    def _ail_handle_Load(self, expr):
-        raise NotImplementedError("Please implement the Load handler with your own logic.")
+    def _ail_handle_Load(self, expr: ailment.Expr.Load):
+        self._expr(expr.addr)
+        return expr
 
-    def _ail_handle_CallExpr(self, expr):
-        raise NotImplementedError("Please implement the CallExpr handler with your own logic.")
+    def _ail_handle_CallExpr(self, expr: ailment.Stmt.Call):
+        self._expr(expr.target)
+        return expr
 
     def _ail_handle_Reinterpret(self, expr: ailment.Expr.Reinterpret):
         arg = self._expr(expr.operand)
@@ -984,9 +985,8 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
         ):
             # int -> float
             b = struct.pack("<I", arg)
-            f = struct.unpack("<f", b)[0]
-            return f
-        elif (
+            return struct.unpack("<f", b)[0]
+        if (
             isinstance(arg, float)
             and expr.from_bits == 32
             and expr.from_type == "F"
@@ -995,8 +995,7 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
         ):
             # float -> int
             b = struct.pack("<f", arg)
-            v = struct.unpack("<I", b)[0]
-            return v
+            return struct.unpack("<I", b)[0]
 
         return expr
 
@@ -1005,7 +1004,7 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
         try:
             handler = getattr(self, handler_name)
         except AttributeError:
-            handler_name = "_ail_handle_%s" % expr.op
+            handler_name = f"_ail_handle_{expr.op}"
             try:
                 handler = getattr(self, handler_name)
             except AttributeError:
@@ -1020,7 +1019,7 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
         try:
             handler = getattr(self, handler_name)
         except AttributeError:
-            handler_name = "_ail_handle_%s" % expr.op
+            handler_name = f"_ail_handle_{expr.op}"
             try:
                 handler = getattr(self, handler_name)
             except AttributeError:
@@ -1035,7 +1034,7 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
         try:
             handler = getattr(self, handler_name)
         except AttributeError:
-            handler_name = "_ail_handle_%s" % expr.op
+            handler_name = f"_ail_handle_{expr.op}"
             try:
                 handler = getattr(self, handler_name)
             except AttributeError:
@@ -1132,14 +1131,8 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
     def _ail_handle_Sub(self, expr):
         arg0, arg1 = expr.operands
 
-        if not isinstance(arg0, claripy.ast.Base):
-            expr_0 = self._expr(arg0)
-        else:
-            expr_0 = arg0
-        if not isinstance(arg1, claripy.ast.Base):
-            expr_1 = self._expr(arg1)
-        else:
-            expr_1 = self._expr(arg1)
+        expr_0 = self._expr(arg0) if not isinstance(arg0, claripy.ast.Base) else arg0
+        expr_1 = self._expr(arg1) if not isinstance(arg1, claripy.ast.Base) else self._expr(arg1)
 
         if expr_0 is None:
             expr_0 = arg0
@@ -1415,9 +1408,8 @@ class SimEngineLightAILMixin(SimEngineLightMixin):
 
     def _ail_handle_Convert(self, expr):
         data = self._expr(expr.operand)
-        if data is not None:
-            if type(data) is int:
-                return data
+        if data is not None and type(data) is int:
+            return data
         return None
 
     def _ail_handle_Not(self, expr):

angr/engines/pcode/__init__.py

@@ -1,2 +1,3 @@
+from __future__ import annotations
 from .engine import HeavyPcodeMixin
 from .cc import register_pcode_arch_default_cc

angr/engines/pcode/behavior.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import operator
 from collections.abc import Callable, Iterable
 
@@ -20,10 +21,9 @@ def make_bv_sizes_equal(bv1: BV, bv2: BV) -> tuple[BV, BV]:
     """
     if bv1.size() < bv2.size():
         return (bv1.sign_extend(bv2.size() - bv1.size()), bv2)
-    elif bv1.size() > bv2.size():
+    if bv1.size() > bv2.size():
         return (bv1, bv2.sign_extend(bv1.size() - bv2.size()))
-    else:
-        return (bv1, bv2)
+    return (bv1, bv2)
 
 
 # FIXME: Unimplemented ops (mostly floating point related) have associated C++

angr/engines/pcode/cc.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 from archinfo import ArchPcode

angr/engines/pcode/emulate.py

@@ -1,5 +1,5 @@
+from __future__ import annotations
 import logging
-from typing import Optional
 
 import claripy
 from claripy.ast.bv import BV
@@ -10,11 +10,10 @@ from .lifter import IRSB
 from .behavior import OpBehavior
 from ...errors import AngrError
 from ...state_plugins.inspect import BP_BEFORE, BP_AFTER
+import contextlib
 
-try:
+with contextlib.suppress(ImportError):
     from pypcode import OpCode, Varnode, PcodeOp
-except ImportError:
-    pass
 
 
 l = logging.getLogger(__name__)
@@ -25,7 +24,7 @@ class PcodeEmulatorMixin(SimEngineBase):
     Mixin for p-code execution.
     """
 
-    _current_op: Optional["PcodeOp"]
+    _current_op: PcodeOp | None
     _current_op_idx: int
     _current_behavior: OpBehavior | None
 
@@ -129,7 +128,7 @@ class PcodeEmulatorMixin(SimEngineBase):
 
         self._current_behavior = None
 
-    def _map_register_name(self, varnode: "Varnode") -> int:
+    def _map_register_name(self, varnode: Varnode) -> int:
         """
         Map SLEIGH register offset to ArchInfo register offset based on name.
 
@@ -156,14 +155,13 @@ class PcodeEmulatorMixin(SimEngineBase):
             v_out = v_in[num_bits - 1 : 0]
             l.debug("Truncating value %s (%d bits) to %s (%d bits)", v_in, v_in.size(), v_out, num_bits)
             return v_out
-        elif v_in.size() < num_bits:
+        if v_in.size() < num_bits:
             v_out = v_in.zero_extend(num_bits - v_in.size())
             l.debug("Extending value %s (%d bits) to %s (%d bits)", v_in, v_in.size(), v_out, num_bits)
             return v_out
-        else:
-            return v_in
+        return v_in
 
-    def _set_value(self, varnode: "Varnode", value: BV) -> None:
+    def _set_value(self, varnode: Varnode, value: BV) -> None:
         """
         Store a value for a given varnode.
 
@@ -194,7 +192,7 @@ class PcodeEmulatorMixin(SimEngineBase):
         else:
             raise AngrError(f"Attempted write to unhandled address space '{space.name}'")
 
-    def _get_value(self, varnode: "Varnode") -> BV:
+    def _get_value(self, varnode: Varnode) -> BV:
         """
         Get a value for a given varnode.
 
@@ -209,12 +207,12 @@ class PcodeEmulatorMixin(SimEngineBase):
         l.debug("Loading %s - %x x %d", space_name, varnode.offset, size)
         if space_name == "const":
             return claripy.BVV(varnode.offset, size * 8)
-        elif space_name == "register":
+        if space_name == "register":
             return self.state.registers.load(
                 self._map_register_name(varnode), size=size, endness=self.project.arch.register_endness
             )
 
-        elif space_name == "unique":
+        if space_name == "unique":
             # FIXME: Support loading data of different sizes. For now, assume
             # size of values read are same as size written.
             try:
@@ -225,13 +223,12 @@ class PcodeEmulatorMixin(SimEngineBase):
                 self._pcode_tmps[varnode.offset] = claripy.BVV(0, size * 8)
             return self._pcode_tmps[varnode.offset]
 
-        elif space_name.lower() in ("ram", "mem"):
+        if space_name.lower() in ("ram", "mem"):
             val = self.state.memory.load(varnode.offset, endness=self.project.arch.memory_endness, size=size)
             l.debug("Loaded %s from offset %s", val, varnode.offset)
             return val
 
-        else:
-            raise AngrError(f"Attempted read from unhandled address space '{space_name}'")
+        raise AngrError(f"Attempted read from unhandled address space '{space_name}'")
 
     def _execute_unary(self) -> None:
         """

angr/engines/pcode/engine.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from collections.abc import Iterable
 
 import claripy
@@ -107,6 +108,7 @@ class HeavyPcodeMixin(
 
         self._process_successor_exits(successors)
         successors.processed = True
+        return None
 
     def _lift_irsb(self):
         irsb = self.state.scratch.irsb
@@ -123,9 +125,9 @@ class HeavyPcodeMixin(
         if irsb.size == 0:
             if irsb.jumpkind == "Ijk_NoDecode" and not self.state.project.is_hooked(irsb.addr):
                 raise errors.SimIRSBNoDecodeError(
-                    "IR decoding error at %#x. You can hook this instruction with "
+                    f"IR decoding error at {self._addr:#x}. You can hook this instruction with "
                     "a python replacement using project.hook"
-                    "(%#x, your_function, length=length_of_instruction)." % (self._addr, self._addr)
+                    f"({self._addr:#x}, your_function, length=length_of_instruction)."
                 )
             raise errors.SimIRSBError("Empty IRSB passed to HeavyPcodeMixin.")
         self.state.scratch.irsb = irsb
@@ -167,7 +169,7 @@ class HeavyPcodeMixin(
         except errors.SimReliftException as e:
             self.state = e.state
             if self._insn_bytes is not None:
-                raise errors.SimEngineError("You cannot pass self-modifying code as insn_bytes!!!")
+                raise errors.SimEngineError("You cannot pass self-modifying code as insn_bytes!!!") from e
             new_ip = self.state.scratch.ins_addr
             if self._size is not None:
                 self._size -= new_ip - self._addr