angr 9.2.117__py3-none-manylinux2014_x86_64.whl → 9.2.118__py3-none-manylinux2014_x86_64.whl

angr/simos/simos.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 import struct
 
@@ -26,7 +27,7 @@ class SimOS:
     A class describing OS/arch-level configuration.
     """
 
-    def __init__(self, project: "angr.Project", name=None):
+    def __init__(self, project: angr.Project, name=None):
         self.arch = project.arch
         self.project = project
         self.name = name
@@ -62,11 +63,8 @@ class SimOS:
                 resolver_addr, concrete_only=True, base_state=base_state, prototype=prototype
             )
             try:
-                if isinstance(self.arch, ArchS390X):
-                    # On s390x ifunc resolvers expect hwcaps.
-                    val = resolver(0)
-                else:
-                    val = resolver()
+                # On s390x ifunc resolvers expect hwcaps.
+                val = resolver(0) if isinstance(self.arch, ArchS390X) else resolver()
             except AngrCallableMultistateError:
                 _l.error("Resolver at %#x failed to resolve! (multivalued)", resolver_addr)
                 return None
@@ -79,16 +77,12 @@ class SimOS:
         self.project.loader.perform_irelative_relocs(irelative_resolver)
 
     def _weak_hook_symbol(self, name, hook, scope=None):
-        if scope is None:
-            sym = self.project.loader.find_symbol(name)
-        else:
-            sym = scope.get_symbol(name)
+        sym = self.project.loader.find_symbol(name) if scope is None else scope.get_symbol(name)
 
         if sym is not None:
             addr, _ = self.prepare_function_symbol(name, basic_addr=sym.rebased_addr)
-            if self.project.is_hooked(addr):
-                if not self.project.hooked_by(addr).is_stub:
-                    return
+            if self.project.is_hooked(addr) and not self.project.hooked_by(addr).is_stub:
+                return
             self.project.hook(addr, hook)
 
     def state_blank(
@@ -146,10 +140,8 @@ class SimOS:
                         perms |= 4  # PROT_EXEC
                     permission_map[(seg.min_addr, seg.max_addr)] = perms
             kwargs["permissions_map"] = permission_map
-        if self.project.loader.main_object.execstack:
-            stack_perms = 1 | 2 | 4  # RWX
-        else:
-            stack_perms = 1 | 2  # RW
+        # RWX or RW
+        stack_perms = 1 | 2 | 4 if self.project.loader.main_object.execstack else 1 | 2
 
         state = SimState(self.project, stack_end=stack_end, stack_size=stack_size, stack_perms=stack_perms, **kwargs)
 
@@ -178,7 +170,7 @@ class SimOS:
             for reg in state.arch.default_symbolic_registers:
                 state.registers.store(
                     reg,
-                    claripy.BVS(
+                    state.solver.BVS(
                         initial_prefix + "_" + reg, state.arch.bits, explicit_name=True, key=("reg", reg), eternal=True
                     ),
                 )
@@ -197,7 +189,7 @@ class SimOS:
                     # Backward compatibility
                     region_base = 0
                 else:
-                    raise AngrSimOSError('You must specify the base address for memory region "%s". ' % mem_region)
+                    raise AngrSimOSError(f'You must specify the base address for memory region "{mem_region}". ')
 
             # special case for stack_end overriding sp default
             if actual_stack_end is not None and state.arch.registers[reg][0] == state.arch.sp_offset:
@@ -343,7 +335,7 @@ class SimOS:
         return None
 
     def syscall_cc(self, state) -> angr.calling_conventions.SimCCSyscall | None:
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def is_syscall_addr(self, addr):
         return False
@@ -415,8 +407,7 @@ class SimOS:
         fs = selector
         selector = self._create_selector(4, S_GDT | S_PRIV_0)
         gs = selector
-        global_descriptor_table = GlobalDescriptorTable(GDT_ADDR, GDT_LIMIT, table, gdt, cs, ds, es, ss, fs, gs)
-        return global_descriptor_table
+        return GlobalDescriptorTable(GDT_ADDR, GDT_LIMIT, table, gdt, cs, ds, es, ss, fs, gs)
 
     @staticmethod
     def _create_selector(idx, flags):

angr/simos/snimmuc_nxp.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from typing import TYPE_CHECKING
 
 from io import BytesIO
@@ -16,17 +17,13 @@ class SimSnimmucNxp(SimOS):
     This class implements the "OS" for a bare-metal firmware used at an imaginary company.
     """
 
-    def __init__(self, project: "Project", name=None, **kwargs):  # pylint:disable=unused-argument
+    def __init__(self, project: Project, name=None, **kwargs):  # pylint:disable=unused-argument
         super().__init__(project, name=name)
 
     def configure_project(self):
         # pattern match the entry point to figure out if we support parsing this binary
         entry_bytes = self.project.loader.memory.load(self.project.entry, 3 * 4)
-        if not entry_bytes == (
-            b"\x94\x21\xff\xf0"  #  stwu   r1, -10(r1)
-            b"\x7c\x08\x02\xa6"  #  mfspr  r0, lr
-            b"\x90\x01\x00\x14"  #  stw    r0, 4(r1)
-        ):
+        if entry_bytes != b"\x94!\xff\xf0" b"|\x08\x02\xa6" b"\x90\x01\x00\x14":
             return
 
         entry_block = self.project.factory.block(self.project.entry)

angr/simos/userland.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 from ..calling_conventions import SYSCALL_CC, SimCCSyscall
@@ -74,14 +75,13 @@ class SimUserland(SimOS):
         sym_num = cc.syscall_num(state)
         try:
             num = state.solver.eval_one(sym_num)
-        except SimSolverError:
+        except SimSolverError as err:
             if allow_unsupported:
                 num = self.unknown_syscall_number
             else:
                 if not state.solver.satisfiable():
-                    raise AngrUnsupportedSyscallError("The program state is not satisfiable")
-                else:
-                    raise AngrUnsupportedSyscallError("Got a symbolic syscall number")
+                    raise AngrUnsupportedSyscallError("The program state is not satisfiable") from err
+                raise AngrUnsupportedSyscallError("Got a symbolic syscall number") from err
 
         proc = self.syscall_from_number(num, allow_unsupported=allow_unsupported, abi=abi)
         proc.cc = cc
@@ -91,7 +91,7 @@ class SimUserland(SimOS):
         """
         Optionally, override this function to determine which abi is being used for the state's current syscall.
         """
-        return None
+        return
 
     def is_syscall_addr(self, addr):
         """
@@ -146,7 +146,7 @@ class SimUserland(SimOS):
 
         if self.syscall_library is None:
             if not allow_unsupported:
-                raise AngrUnsupportedSyscallError("%s does not have a library of syscalls implemented" % self.name)
+                raise AngrUnsupportedSyscallError(f"{self.name} does not have a library of syscalls implemented")
             proc = P["stubs"]["syscall"]()
         elif not allow_unsupported and not self.syscall_library.has_implementation(number, self.arch, abilist):
             raise AngrUnsupportedSyscallError("No implementation for syscall %d" % number)

angr/simos/windows.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import enum
 import os
 import logging
@@ -79,8 +80,7 @@ class SimWindows(SimOS):
         sym = self.project.loader.find_symbol(name)
         if sym is None:
             return self.project.loader.extern_object.get_pseudo_addr(name)
-        else:
-            return sym.rebased_addr
+        return sym.rebased_addr
 
     # pylint: disable=arguments-differ
     def state_entry(self, args=None, env=None, argc=None, **kwargs):
@@ -269,7 +269,7 @@ class SimWindows(SimOS):
                                 init_order.append(depo)
 
                 fuck_load(self.project.loader.main_object)
-                load_order = [self.project.loader.main_object] + init_order
+                load_order = [self.project.loader.main_object, *init_order]
 
                 def link(a, b):
                     state.mem[a].dword = b
@@ -309,9 +309,12 @@ class SimWindows(SimOS):
         if engine is not self.project.factory.default_engine:
             raise exception
         # don't bother handling symbolic-address exceptions
-        if type(exception) is SimSegfaultException:
-            if exception.original_addr is not None and exception.original_addr.symbolic:
-                raise exception
+        if (
+            type(exception) is SimSegfaultException
+            and exception.original_addr is not None
+            and exception.original_addr.symbolic
+        ):
+            raise exception
 
         _l.debug("Handling exception from block at %#x: %r", successors.addr, exception)
 
@@ -380,12 +383,12 @@ class SimWindows(SimOS):
         tib_addr = exc_state.regs._fs.concat(claripy.BVV(0, 16))
         if exc_state.solver.is_true(exc_state.mem[tib_addr].long.resolved == -1):
             _l.debug("... no handlers registered")
-            exception.args = ("Unhandled exception: %r" % exception,)
+            exception.args = (f"Unhandled exception: {exception!r}",)
             raise exception
         # catch nested exceptions here with magic value
         if exc_state.solver.is_true(exc_state.mem[tib_addr].long.resolved == 0xBADFACE):
             _l.debug("... nested exception")
-            exception.args = ("Unhandled exception: %r" % exception,)
+            exception.args = (f"Unhandled exception: {exception!r}",)
             raise exception
 
         # serialize the thread context and set up the exception record...
@@ -508,7 +511,7 @@ class SimWindows(SimOS):
         """
         exfiltration_reg = "eax"
         # instruction to inject for reading the value at segment value = offset
-        read_fs0_x86 = b"\x64\xA1\x18\x00\x00\x00\x90\x90\x90\x90"  # mov eax, fs:[0x18]
+        read_fs0_x86 = b"\x64\xa1\x18\x00\x00\x00\x90\x90\x90\x90"  # mov eax, fs:[0x18]
         return concrete_target.execute_shellcode(read_fs0_x86, exfiltration_reg)
 
     @staticmethod
@@ -522,7 +525,7 @@ class SimWindows(SimOS):
         """
         exfiltration_reg = "rax"
         # instruction to inject for reading the value at segment value = offset
-        read_gs0_x64 = b"\x65\x48\x8B\x04\x25\x30\x00\x00\x00\x90\x90\x90\x90"  # mov rax, gs:[0x30]
+        read_gs0_x64 = b"\x65\x48\x8b\x04\x25\x30\x00\x00\x00\x90\x90\x90\x90"  # mov rax, gs:[0x30]
         return concrete_target.execute_shellcode(read_gs0_x64, exfiltration_reg)
 
     def get_segment_register_name(self):

angr/slicer.py

@@ -1,4 +1,5 @@
 # pylint:disable=no-self-use
+from __future__ import annotations
 import pyvex
 
 from .errors import SimSlicerError
@@ -118,7 +119,7 @@ class SimSlicer:
         :return:
         """
 
-        funcname = "_forward_handler_stmt_%s" % type(stmt).__name__
+        funcname = f"_forward_handler_stmt_{type(stmt).__name__}"
 
         if hasattr(self, funcname):
             getattr(self, funcname)(stmt, state)
@@ -144,7 +145,7 @@ class SimSlicer:
         :return:
         """
 
-        funcname = "_forward_handler_expr_%s" % type(expr).__name__
+        funcname = f"_forward_handler_expr_{type(expr).__name__}"
 
         if hasattr(self, funcname):
             return getattr(self, funcname)(expr, state)
@@ -154,10 +155,12 @@ class SimSlicer:
     def _forward_handler_expr_Get(self, expr, state):
         reg = expr.offset
 
-        if state.options["mock_sp"] and reg == self._arch.sp_offset:
-            return state.regs[reg]
-
-        elif state.options["mock_bp"] and reg == self._arch.bp_offset:
+        if (
+            state.options["mock_sp"]
+            and reg == self._arch.sp_offset
+            or state.options["mock_bp"]
+            and reg == self._arch.bp_offset
+        ):
             return state.regs[reg]
 
         return None
@@ -174,7 +177,7 @@ class SimSlicer:
         return expr.con.value
 
     def _forward_handler_expr_Binop(self, expr, state):
-        funcname = "_forward_handler_expr_binop_%s" % expr.op.strip("Iop_")
+        funcname = "_forward_handler_expr_binop_{}".format(expr.op.strip("Iop_"))
 
         if hasattr(self, funcname):
             op0_val = self._forward_handler_expr(expr.args[0], state)
@@ -224,7 +227,7 @@ class SimSlicer:
     #
 
     def _backward_handler_stmt(self, stmt, state):
-        funcname = "_backward_handler_stmt_%s" % type(stmt).__name__
+        funcname = f"_backward_handler_stmt_{type(stmt).__name__}"
 
         in_slice = False
         if hasattr(self, funcname):
@@ -262,8 +265,7 @@ class SimSlicer:
 
             return True
 
-        else:
-            return False
+        return False
 
     def _backward_handler_stmt_Store(self, stmt, state):
         addr = stmt.addr
@@ -301,7 +303,7 @@ class SimSlicer:
     #
 
     def _backward_handler_expr(self, expr, state):
-        funcname = "_backward_handler_expr_%s" % type(expr).__name__
+        funcname = f"_backward_handler_expr_{type(expr).__name__}"
         if hasattr(self, funcname):
             getattr(self, funcname)(expr, state)
 

angr/state_hierarchy.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 import weakref
 import itertools
@@ -52,8 +53,7 @@ class StateHierarchy:
             self._weakref_cache[id(obj)] = ref
             self._reverse_weakref_cache[ref] = id(obj)
             return ref
-        else:
-            return self._weakref_cache[id(obj)]
+        return self._weakref_cache[id(obj)]
 
     def dead_ref(self, ref):
         if self._defer_cleanup:
@@ -195,7 +195,7 @@ class StateHierarchy:
                 root = lineage[bad]
                 l.debug("... returning %d (%s)", bad, root)
                 return root
-            elif lineage[cur]().reachable():
+            if lineage[cur]().reachable():
                 l.debug("... %d is reachable", cur)
                 good = cur
             else:

angr/state_plugins/__init__.py

@@ -1,4 +1,5 @@
 # pylint:disable=wildcard-import
+from __future__ import annotations
 from .plugin import *
 from .libc import *
 from .inspect import *

angr/state_plugins/callstack.py

@@ -1,7 +1,7 @@
+from __future__ import annotations
 import collections
 from itertools import dropwhile
 import logging
-from typing import Optional
 from collections.abc import Iterator
 
 from .plugin import SimStatePlugin
@@ -23,7 +23,7 @@ class CallStack(SimStatePlugin):
         stack_ptr=0,
         ret_addr=0,
         jumpkind="Ijk_Call",
-        next_frame: Optional["CallStack"] = None,
+        next_frame: CallStack | None = None,
         invoke_return_variable=None,
     ):
         super().__init__()
@@ -78,7 +78,7 @@ class CallStack(SimStatePlugin):
     def widen(self, others):  # pylint: disable=unused-argument
         l.warning("Widening not implemented for callstacks")
 
-    def __iter__(self) -> Iterator["CallStack"]:
+    def __iter__(self) -> Iterator[CallStack]:
         """
         Iterate through the callstack, from top to bottom
         (most recent first).
@@ -122,9 +122,11 @@ class CallStack(SimStatePlugin):
         return "<CallStack (depth %d)>" % len(self)
 
     def __str__(self):
-        return "Backtrace:\n%s" % "\n".join(
-            "Frame %d: %#x => %#x, sp = %#x" % (i, f.call_site_addr, f.func_addr, f.stack_ptr)
-            for i, f in enumerate(self)
+        return "Backtrace:\n{}".format(
+            "\n".join(
+                "Frame %d: %#x => %#x, sp = %#x" % (i, f.call_site_addr, f.func_addr, f.stack_ptr)
+                for i, f in enumerate(self)
+            )
         )
 
     def __eq__(self, other):
@@ -202,8 +204,7 @@ class CallStack(SimStatePlugin):
         :return: A string representation
         :rtype: str
         """
-        s = "[" + ",".join([("0x%x" % i) if i is not None else "Unspecified" for i in stack_suffix]) + "]"
-        return s
+        return "[" + ",".join([(f"0x{i:x}") if i is not None else "Unspecified" for i in stack_suffix]) + "]"
 
     @staticmethod
     def _rfind(lst, item):
@@ -219,7 +220,7 @@ class CallStack(SimStatePlugin):
         try:
             return dropwhile(lambda x: lst[x] != item, next(reversed(range(len(lst)))))
         except Exception as e:
-            raise ValueError("%s not in the list" % item) from e
+            raise ValueError(f"{item} not in the list") from e
 
     @property
     def top(self):
@@ -320,9 +321,9 @@ class CallStack(SimStatePlugin):
         for i, frame in enumerate(self):
             s = "%d | %s -> %s, returning to %s" % (
                 i,
-                "None" if frame.call_site_addr is None else "%#x" % frame.call_site_addr,
-                "None" if frame.func_addr is None else "%#x" % frame.func_addr,
-                "None" if frame.current_return_target is None else "%#x" % frame.current_return_target,
+                "None" if frame.call_site_addr is None else f"{frame.call_site_addr:#x}",
+                "None" if frame.func_addr is None else f"{frame.func_addr:#x}",
+                "None" if frame.current_return_target is None else f"{frame.current_return_target:#x}",
             )
             stack.append(s)
 
@@ -342,10 +343,10 @@ class CallStack(SimStatePlugin):
         for frame in self:
             if len(ret) >= context_sensitivity_level * 2:
                 break
-            ret = (frame.call_site_addr, frame.func_addr) + ret
+            ret = (frame.call_site_addr, frame.func_addr, *ret)
 
         while len(ret) < context_sensitivity_level * 2:
-            ret = (None, None) + ret
+            ret = (None, None, *ret)
 
         return ret
 
@@ -381,7 +382,7 @@ class CallStackAction:
         self.action = action
 
         if action not in ("push", "pop"):
-            raise AngrError('Unsupported action string "%s".' % action)
+            raise AngrError(f'Unsupported action string "{action}".')
 
         self.callframe = callframe
         self.ret_site_addr = ret_site_addr
@@ -394,9 +395,9 @@ class CallStackAction:
 
     def __repr__(self):
         if self.action == "push":
-            return "<CallStackAction push with %s>" % self.callframe
-        else:  # pop
-            return "<CallStackAction pop, ret site %#x>" % self.ret_site_addr
+            return f"<CallStackAction push with {self.callframe}>"
+        # pop
+        return f"<CallStackAction pop, ret site {self.ret_site_addr:#x}>"
 
 
 from angr.sim_state import SimState

angr/state_plugins/cgc.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import operator
 from .plugin import SimStatePlugin
 
@@ -83,7 +84,7 @@ class SimStateCGC(SimStatePlugin):
         return not self.state.solver.solution(a != 0, True)
 
     def _combine(self, others):
-        merging_occured = False
+        merging_occurred = False
 
         new_allocation_base = max(o.allocation_base for o in others)
         if self.state.solver.symbolic(new_allocation_base):
@@ -94,9 +95,9 @@ class SimStateCGC(SimStatePlugin):
 
         if concrete_allocation_base != concrete_new_allocation_base:
             self.allocation_base = new_allocation_base
-            merging_occured = True
+            merging_occurred = True
 
-        return merging_occured
+        return merging_occurred
 
     def merge(self, others, merge_conditions, common_ancestor=None):  # pylint: disable=unused-argument
         return self._combine(others)
@@ -116,7 +117,7 @@ class SimStateCGC(SimStatePlugin):
         sinkhole is removed.
         """
 
-        ordered_sinks = sorted(list(self.sinkholes), key=operator.itemgetter(0), reverse=True)
+        ordered_sinks = sorted(self.sinkholes, key=operator.itemgetter(0), reverse=True)
         max_pair = None
         for addr, sz in ordered_sinks:
             if sz >= length:

angr/state_plugins/concrete.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import cle
 import io
 import logging
@@ -43,14 +44,13 @@ class Concrete(SimStatePlugin):
             self.already_sync_objects_addresses = already_sync_objects_addresses
 
     def copy(self, _memo):
-        conc = Concrete(
+        return Concrete(
             segment_registers_initialized=self.segment_registers_initialized,
             segment_registers_callback_initialized=self.segment_registers_callback_initialized,
             whitelist=list(self.whitelist),
             fs_register_bp=self.fs_register_bp,
             already_sync_objects_addresses=list(self.already_sync_objects_addresses),
         )
-        return conc
 
     def merge(self, _others, _merge_conditions, _common_ancestor=None):
         pass
@@ -112,7 +112,7 @@ class Concrete(SimStatePlugin):
             # before let's sync all the subregisters of the current register.
             # sometimes this can be helpful ( i.e. ymmm0 e xmm0 )
             if register.subregisters:
-                subregisters_names = map(lambda x: x[0], register.subregisters)
+                subregisters_names = (x[0] for x in register.subregisters)
                 self._sync_registers(subregisters_names, target)
 
             # finally let's synchronize the whole register
@@ -173,11 +173,10 @@ class Concrete(SimStatePlugin):
         def _check_mapping_name(cle_mapping_name, concrete_mapping_name):
             if cle_mapping_name == concrete_mapping_name:
                 return True
-            else:
-                # removing version and extension information from the library name
-                cle_mapping_name = re.findall(r"[\w']+", cle_mapping_name)
-                concrete_mapping_name = re.findall(r"[\w']+", concrete_mapping_name)
-                return (cle_mapping_name[0] == concrete_mapping_name[0]) if len(concrete_mapping_name) else False
+            # removing version and extension information from the library name
+            cle_mapping_name = re.findall(r"[\w']+", cle_mapping_name)
+            concrete_mapping_name = re.findall(r"[\w']+", concrete_mapping_name)
+            return (cle_mapping_name[0] == concrete_mapping_name[0]) if len(concrete_mapping_name) else False
 
         l.debug("Synchronizing CLE backend with the concrete process memory mapping")
         try:

angr/state_plugins/debug_variables.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from typing import TYPE_CHECKING
 import logging
 
@@ -28,19 +29,19 @@ class SimDebugVariable:
         self.type = var_type
 
     @staticmethod
-    def from_cle_variable(state: SimState, cle_variable: Variable, dwarf_cfa) -> "SimDebugVariable":
+    def from_cle_variable(state: SimState, cle_variable: Variable, dwarf_cfa) -> SimDebugVariable:
         addr = cle_variable.rebased_addr_from_cfa(dwarf_cfa)
         var_type = cle_variable.type
         return SimDebugVariable(state, addr, var_type)
 
     @property
-    def mem_untyped(self) -> "SimMemView":
+    def mem_untyped(self) -> SimMemView:
         if self.addr is None:
             raise Exception("Cannot view a variable without an address")
         return self.state.mem[self.addr]
 
     @property
-    def mem(self) -> "SimMemView":
+    def mem(self) -> SimMemView:
         if isinstance(self.type, TypedefType):
             unpacked = SimDebugVariable(self.state, self.addr, self.type.type)
             return unpacked.mem
@@ -62,12 +63,12 @@ class SimDebugVariable:
     # methods and properties equivalent to SimMemView
 
     @property
-    def string(self) -> "SimMemView":
+    def string(self) -> SimMemView:
         first_char = self.deref
         # first char should have some char type (could be checked here)
         return first_char.mem_untyped.string
 
-    def with_type(self, sim_type: "SimType") -> "SimMemView":
+    def with_type(self, sim_type: SimType) -> SimMemView:
         return self.mem_untyped.with_type(sim_type)
 
     @property
@@ -88,20 +89,20 @@ class SimDebugVariable:
     def __getitem__(self, i):
         if isinstance(i, int):
             return self.array(i)
-        elif isinstance(i, str):
+        if isinstance(i, str):
             return self.member(i)
         raise KeyError
 
     @property
-    def deref(self) -> "SimDebugVariable":
+    def deref(self) -> SimDebugVariable:
         # dereferincing is equivalent to getting the first array element
         return self.array(0)
 
-    def array(self, i) -> "SimDebugVariable":
+    def array(self, i) -> SimDebugVariable:
         if isinstance(self.type, TypedefType):
             unpacked = SimDebugVariable(self.state, self.addr, self.type.type)
             return unpacked.array(i)
-        elif isinstance(self.type, ArrayType):
+        if isinstance(self.type, ArrayType):
             # an array already addresses its first element
             addr = self.addr
             el_type = self.type.element_type
@@ -122,16 +123,13 @@ class SimDebugVariable:
             new_addr = addr + i * el_type.byte_size
         return SimDebugVariable(self.state, new_addr, el_type)
 
-    def member(self, member_name: str) -> "SimDebugVariable":
+    def member(self, member_name: str) -> SimDebugVariable:
         if isinstance(self.type, TypedefType):
             unpacked = SimDebugVariable(self.state, self.addr, self.type.type)
             return unpacked.member(member_name)
-        elif isinstance(self.type, StructType):
+        if isinstance(self.type, StructType):
             member = self.type[member_name]
-            if self.addr is None:
-                addr = None
-            else:
-                addr = self.addr + member.addr_offset
+            addr = None if self.addr is None else self.addr + member.addr_offset
             return SimDebugVariable(self.state, addr, member.type)
 
         raise Exception(f"{self.type} object has no members")
@@ -142,7 +140,7 @@ class SimDebugVariablePlugin(SimStatePlugin):
     This is the plugin you'll use to interact with (global/local) program variables.
     These variables have a name and a visibility scope which depends on the pc address of the state.
     With this plugin, you can access/modify the value of such variable or find its memory address.
-    For creating program varibles, or for importing them from cle, see the knowledge plugin debug_variables.
+    For creating program variables, or for importing them from cle, see the knowledge plugin debug_variables.
     Run ``p.kb.dvars.load_from_dwarf()`` before using this plugin.
 
     Example:
@@ -186,7 +184,7 @@ class SimDebugVariablePlugin(SimStatePlugin):
         # FIXME This is only an approximation!
         if self.state.arch.name == "AMD64":
             return self.state.regs.rbp + 16
-        elif self.state.arch.name == "X86":
+        if self.state.arch.name == "X86":
             return self.state.regs.ebp + 8
         return 0