angr 9.2.117__py3-none-manylinux2014_aarch64.whl → 9.2.118__py3-none-manylinux2014_aarch64.whl

angr/storage/memory_mixins/paged_memory/pages/history_tracking_mixin.py

@@ -1,4 +1,5 @@
 # pylint:disable=arguments-differ,unused-argument,no-member
+from __future__ import annotations
 
 from angr.storage.memory_mixins import MemoryMixin
 from angr.utils.segment_list import SegmentList
@@ -26,8 +27,7 @@ class HistoryTrackingMixin(RefcountMixin, MemoryMixin):
         return super().store(addr, data, **kwargs)
 
     def copy(self, memo):
-        o = super().copy(memo)
-        return o
+        return super().copy(memo)
 
     def acquire_unique(self):
         page = super().acquire_unique()
@@ -52,8 +52,8 @@ class HistoryTrackingMixin(RefcountMixin, MemoryMixin):
     def changed_bytes(self, other, **kwargs) -> set[int] | None:
         candidates: set[int] = set()
 
-        self_history_list = [self] + list(self.parents())
-        other_history_list = [other] + list(other.parents())
+        self_history_list = [self, *list(self.parents())]
+        other_history_list = [other, *list(other.parents())]
         if self_history_list and other_history_list and self_history_list[-1] is other_history_list[-1]:
             # two pages have the same root. we can get a list of candidate offsets this way
 

angr/storage/memory_mixins/paged_memory/pages/ispo_mixin.py

@@ -1,4 +1,5 @@
 # pylint:disable=arguments-differ
+from __future__ import annotations
 from angr.storage.memory_mixins import MemoryMixin
 
 

angr/storage/memory_mixins/paged_memory/pages/list_page.py

@@ -1,4 +1,5 @@
 # pylint:disable=abstract-method,arguments-differ
+from __future__ import annotations
 import logging
 
 import claripy
@@ -24,9 +25,8 @@ class ListPage(MemoryObjectMixin, PageBase):
             DynamicDictList(max_size=memory.page_size, content=content) if content is not None else None
         )
         self.stored_offset = set()
-        if self.content is None:
-            if memory is not None:
-                self.content: DynamicDictList[SimMemoryObject | None] = DynamicDictList(max_size=memory.page_size)
+        if self.content is None and memory is not None:
+            self.content: DynamicDictList[SimMemoryObject | None] = DynamicDictList(max_size=memory.page_size)
         self._mo_cmp = mo_cmp
 
         self.sinkhole: SimMemoryObject | None = sinkhole
@@ -113,10 +113,10 @@ class ListPage(MemoryObjectMixin, PageBase):
 
     def merge(
         self,
-        others: list["ListPage"],
+        others: list[ListPage],
         merge_conditions,
         common_ancestor=None,
-        page_addr: int = None,
+        page_addr: int | None = None,
         memory=None,
         changed_offsets: set[int] | None = None,
     ):
@@ -125,7 +125,7 @@ class ListPage(MemoryObjectMixin, PageBase):
             for other in others:
                 changed_offsets |= self.changed_bytes(other, page_addr)
 
-        all_pages: list["ListPage"] = [self] + others
+        all_pages: list[ListPage] = [self, *others]
         if merge_conditions is None:
             merge_conditions = [None] * len(all_pages)
 
@@ -165,7 +165,7 @@ class ListPage(MemoryObjectMixin, PageBase):
                 to_merge = [(mo.object, fv) for mo, fv in memory_objects]
 
                 # Update `merged_to`
-                mo_base = list(mo_bases)[0]
+                mo_base = next(iter(mo_bases))
                 mo_length = memory_objects[0][0].length
                 size = mo_length - (page_addr + b - mo_base)
                 merged_to = b + size
@@ -202,7 +202,7 @@ class ListPage(MemoryObjectMixin, PageBase):
                     if min_size is None or mo_size < min_size:
                         min_size = mo_size
                 for um, _ in unconstrained_in:
-                    for i in range(0, min_size):
+                    for i in range(min_size):
                         if um._contains(b + i, page_addr):
                             min_size = i
                             break
@@ -240,7 +240,7 @@ class ListPage(MemoryObjectMixin, PageBase):
         self.stored_offset |= merged_offsets
         return merged_offsets
 
-    def changed_bytes(self, other: "ListPage", page_addr: int = None):
+    def changed_bytes(self, other: ListPage, page_addr: int | None = None):
         candidates = super().changed_bytes(other)
         if candidates is None:
             candidates: set[int] = set()
@@ -263,16 +263,11 @@ class ListPage(MemoryObjectMixin, PageBase):
         for c in candidates:
             s_contains = self._contains(c, page_addr)
             o_contains = other._contains(c, page_addr)
-            if not s_contains and o_contains:
-                differences.add(c)
-            elif s_contains and not o_contains:
+            if not s_contains and o_contains or s_contains and not o_contains:
                 differences.add(c)
             else:
                 if self.content[c] is None:
-                    if self.sinkhole is None:
-                        v = claripy.BVV(0, 8)
-                    else:
-                        v = (self.sinkhole.bytes_at(page_addr + c, 1),)
+                    v = claripy.BVV(0, 8) if self.sinkhole is None else (self.sinkhole.bytes_at(page_addr + c, 1),)
                     self.content[c] = SimMemoryObject(
                         v,
                         page_addr + c,
@@ -280,10 +275,7 @@ class ListPage(MemoryObjectMixin, PageBase):
                         endness="Iend_BE",
                     )
                 if other.content[c] is None:
-                    if other.sinkhole is None:
-                        v = claripy.BVV(0, 8)
-                    else:
-                        v = (other.sinkhole.bytes_at(page_addr + c, 1),)
+                    v = claripy.BVV(0, 8) if other.sinkhole is None else (other.sinkhole.bytes_at(page_addr + c, 1),)
                     other.content[c] = SimMemoryObject(
                         v,
                         page_addr + c,

angr/storage/memory_mixins/paged_memory/pages/multi_values.py

@@ -1,4 +1,4 @@
-from typing import Union
+from __future__ import annotations
 from collections.abc import Iterator
 import archinfo
 
@@ -25,7 +25,7 @@ class MultiValues:
 
     def __init__(
         self,
-        v: Union[claripy.ast.Bits, "MultiValues", None, dict[int, set[claripy.ast.Bits]]] = None,
+        v: claripy.ast.Bits | MultiValues | None | dict[int, set[claripy.ast.Bits]] = None,
         offset_to_values=None,
     ):
         if v is not None and offset_to_values is not None:
@@ -46,10 +46,9 @@ class MultiValues:
             self._values = {}
 
         # if only one value is passed in, assign it to self._single_value
-        if self._values:
-            if len(self._values) == 1 and 0 in self._values and len(self._values[0]) == 1:
-                self._single_value = next(iter(self._values[0]))
-                self._values = None
+        if self._values and len(self._values) == 1 and 0 in self._values and len(self._values[0]) == 1:
+            self._single_value = next(iter(self._values[0]))
+            self._values = None
 
         if self._values:
             # sanity check
@@ -156,7 +155,7 @@ class MultiValues:
         max_len = max(x.size() for x in self._values[max_offset])
         return max_offset * 8 + max_len  # FIXME: we are assuming byte_width of 8
 
-    def merge(self, mv: "MultiValues") -> "MultiValues":
+    def merge(self, mv: MultiValues) -> MultiValues:
         new_values = {k: set(v) for k, v in self.items()}
         for off, vs in mv.items():
             if off not in new_values:
@@ -178,10 +177,7 @@ class MultiValues:
         assert other._values is not None
         if set(self._values.keys()) != set(other._values.keys()):
             return False
-        for k in self._values.keys():
-            if self._values[k] != other._values[k]:
-                return False
-        return True
+        return all(self._values[k] == other._values[k] for k in self._values)
 
     def __repr__(self):
         if self._single_value is not None:
@@ -197,9 +193,9 @@ class MultiValues:
         if self._single_value is not None:
             if offset == 0:
                 return {self._single_value}
-            raise KeyError()
-        elif not self._values:
-            raise KeyError()
+            raise KeyError
+        if not self._values:
+            raise KeyError
         return self._values[offset]
 
     def keys(self) -> set[int]:
@@ -231,7 +227,7 @@ class MultiValues:
             return 0
         return len(self._values)
 
-    def extract(self, offset: int, length: int, endness: str) -> "MultiValues":
+    def extract(self, offset: int, length: int, endness: str) -> MultiValues:
         end = offset + length
         result = MultiValues(claripy.BVV(b""))
         for obj_offset, values in self.items():
@@ -250,7 +246,7 @@ class MultiValues:
 
         return result
 
-    def concat(self, other: Union["MultiValues", claripy.ast.Bits, bytes]) -> "MultiValues":
+    def concat(self, other: MultiValues | claripy.ast.Bits | bytes) -> MultiValues:
         if isinstance(other, bytes):
             other = claripy.BVV(other)
         if isinstance(other, claripy.ast.Bits):
@@ -276,14 +272,13 @@ class MultiValues:
         :return:        The adjacent offset as requested. If the requested adjacent offset does not exist, return None.
         """
 
-        sorted_offsets = list(sorted(self._values.keys())) if self._values is not None else [0]
+        sorted_offsets = sorted(self._values.keys()) if self._values is not None else [0]
 
         for i, off in enumerate(sorted_offsets):
             if off == offset:
                 if before:
                     return sorted_offsets[i - 1] if i > 0 else None
-                else:
-                    return sorted_offsets[i + 1] if i + 1 < len(sorted_offsets) else None
+                return sorted_offsets[i + 1] if i + 1 < len(sorted_offsets) else None
             if off > offset:
                 # we missed it...
                 return None

angr/storage/memory_mixins/paged_memory/pages/mv_list_page.py

@@ -1,4 +1,5 @@
 # pylint:disable=abstract-method,arguments-differ,assignment-from-no-return
+from __future__ import annotations
 import logging
 from typing import Union, Any
 from collections.abc import Callable
@@ -35,15 +36,12 @@ class MVListPage(
         self.stored_offset = set()
         self._mo_cmp: Callable | None = mo_cmp
 
-        if self.content is None:
-            if memory is not None:
-                self.content: DynamicDictList[_MOTYPE | set[_MOTYPE] | None] = DynamicDictList(
-                    max_size=memory.page_size
-                )
+        if self.content is None and memory is not None:
+            self.content: DynamicDictList[_MOTYPE | set[_MOTYPE] | None] = DynamicDictList(max_size=memory.page_size)
 
         self.sinkhole: _MOTYPE | None = sinkhole
 
-    def copy(self, memo) -> "MVListPage":
+    def copy(self, memo) -> MVListPage:
         o = super().copy(memo)
         o.content = DynamicDictList(max_size=self.content.max_size, content=self.content)
         o.sinkhole = self.sinkhole
@@ -142,10 +140,10 @@ class MVListPage(
 
     def merge(
         self,
-        others: list["MVListPage"],
+        others: list[MVListPage],
         merge_conditions,
         common_ancestor=None,
-        page_addr: int = None,
+        page_addr: int | None = None,
         memory=None,
         changed_offsets: set[int] | None = None,
     ):
@@ -154,7 +152,7 @@ class MVListPage(
             for other in others:
                 changed_offsets |= self.changed_bytes(other, page_addr)
 
-        all_pages: list["MVListPage"] = [self] + others
+        all_pages: list[MVListPage] = [self, *others]
         if merge_conditions is None:
             merge_conditions = [None] * len(all_pages)
 
@@ -217,7 +215,7 @@ class MVListPage(
                         to_merge.append((mo.object, fv))
 
                 # Update `merged_to`
-                mo_base = list(mo_bases)[0]
+                mo_base = next(iter(mo_bases))
                 mo_length = next(iter(mo_lengths))
                 size = min(mo_length - (page_addr + b - mo_base), len(self.content) - b)
                 merged_to = b + size
@@ -245,7 +243,7 @@ class MVListPage(
                     for mo in mo_set:
                         min_size = min(min_size, mo.length - ((b + page_addr - mo.base) & mask))
                 for um, _ in unconstrained_in:
-                    for i in range(0, min_size):
+                    for i in range(min_size):
                         if um._contains(b + i, page_addr):
                             min_size = i
                             break
@@ -280,7 +278,7 @@ class MVListPage(
         return merged_offsets
 
     def compare(
-        self, other: "MVListPage", page_addr: int = None, memory=None, changed_offsets=None
+        self, other: MVListPage, page_addr: int | None = None, memory=None, changed_offsets=None
     ) -> bool:  # pylint: disable=unused-argument
         compared_to = None
         for b in sorted(changed_offsets):
@@ -312,7 +310,7 @@ class MVListPage(
 
         return True
 
-    def changed_bytes(self, other: "MVListPage", page_addr: int = None):
+    def changed_bytes(self, other: MVListPage, page_addr: int | None = None):
         candidates: set[int] = super().changed_bytes(other)
         if candidates is not None:
             # using the result from the history tracking mixin as an approximation
@@ -341,27 +339,23 @@ class MVListPage(
         for c in candidates:
             s_contains = self._contains(c, page_addr)
             o_contains = other._contains(c, page_addr)
-            if not s_contains and o_contains:
-                differences.add(c)
-            elif s_contains and not o_contains:
+            if not s_contains and o_contains or s_contains and not o_contains:
                 differences.add(c)
             else:
-                if self.content[c] is None:
-                    if self.sinkhole is not None:
-                        self.content[c] = SimMemoryObject(
-                            self.sinkhole.bytes_at(page_addr + c, 1),
-                            page_addr + c,
-                            byte_width=byte_width,
-                            endness="Iend_BE",
-                        )
-                if other.content[c] is None:
-                    if other.sinkhole is not None:
-                        other.content[c] = SimMemoryObject(
-                            other.sinkhole.bytes_at(page_addr + c, 1),
-                            page_addr + c,
-                            byte_width=byte_width,
-                            endness="Iend_BE",
-                        )
+                if self.content[c] is None and self.sinkhole is not None:
+                    self.content[c] = SimMemoryObject(
+                        self.sinkhole.bytes_at(page_addr + c, 1),
+                        page_addr + c,
+                        byte_width=byte_width,
+                        endness="Iend_BE",
+                    )
+                if other.content[c] is None and other.sinkhole is not None:
+                    other.content[c] = SimMemoryObject(
+                        other.sinkhole.bytes_at(page_addr + c, 1),
+                        page_addr + c,
+                        byte_width=byte_width,
+                        endness="Iend_BE",
+                    )
                 if s_contains and self.content[c] != other.content[c]:
                     same = None
                     if self._mo_cmp is not None:

angr/storage/memory_mixins/paged_memory/pages/permissions_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import claripy
 
 from angr.storage.memory_mixins import MemoryMixin

angr/storage/memory_mixins/paged_memory/pages/refcount_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from angr.storage.memory_mixins import MemoryMixin
 from angr.misc import PicklableLock
 
@@ -29,8 +30,7 @@ class RefcountMixin(MemoryMixin):
         with self.lock:
             if self.refcount == 1:
                 return self
-            else:
-                self.refcount -= 1
+            self.refcount -= 1
         return self.copy(
             {}
         )  # TODO: evaluate if it's worth making the lock a reentrant lock (RLock) so this can go in the else arm

angr/storage/memory_mixins/paged_memory/pages/ultra_page.py

@@ -1,4 +1,5 @@
 # pylint:disable=arguments-differ
+from __future__ import annotations
 import logging
 from typing import Any
 from collections.abc import Iterable
@@ -138,7 +139,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
         self,
         addr,
         data: int | SimMemoryObject,
-        size: int = None,
+        size: int | None = None,
         endness=None,
         memory=None,
         page_addr=None,  # pylint: disable=arguments-differ
@@ -158,24 +159,23 @@ class UltraPage(MemoryObjectMixin, PageBase):
 
         byte_width = memory.state.arch.byte_width
 
-        if type(data) is not int:
-            if data.object.op == "BVV" and not data.object.annotations:
-                # trim the unnecessary leading bytes if there are any
-                full_bits = len(data.object)
-                start = (page_addr + addr - data.base) & ((1 << memory.state.arch.bits) - 1)
-                if start >= data.base + data.length:
-                    raise SimMemoryError("Not enough bytes to store.")
-                start_bits = full_bits - start * byte_width - 1
-                # trim the overflowing bytes if there are any
-                end_bits = start_bits + 1 - size * byte_width
-                if start_bits != full_bits - 1 or end_bits != 0:
-                    if endness == "Iend_LE":
-                        start_bits, end_bits = len(data.object) - end_bits - 1, len(data.object) - start_bits - 1
-
-                    concrete_data: bytes = data.concrete_bytes(
-                        (full_bits - start_bits - 1) // byte_width, (start_bits - end_bits + 1) // byte_width
-                    )
-                    data = int.from_bytes(concrete_data, "big")
+        if type(data) is not int and data.object.op == "BVV" and not data.object.annotations:
+            # trim the unnecessary leading bytes if there are any
+            full_bits = len(data.object)
+            start = (page_addr + addr - data.base) & ((1 << memory.state.arch.bits) - 1)
+            if start >= data.base + data.length:
+                raise SimMemoryError("Not enough bytes to store.")
+            start_bits = full_bits - start * byte_width - 1
+            # trim the overflowing bytes if there are any
+            end_bits = start_bits + 1 - size * byte_width
+            if start_bits != full_bits - 1 or end_bits != 0:
+                if endness == "Iend_LE":
+                    start_bits, end_bits = len(data.object) - end_bits - 1, len(data.object) - start_bits - 1
+
+                concrete_data: bytes = data.concrete_bytes(
+                    (full_bits - start_bits - 1) // byte_width, (start_bits - end_bits + 1) // byte_width
+                )
+                data = int.from_bytes(concrete_data, "big")
 
         if type(data) is int or (data.object.op == "BVV" and not data.object.annotations):
             # mark range as not symbolic
@@ -183,10 +183,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
 
             # store
             arange = range(addr, addr + size)
-            if type(data) is int:
-                ival = data
-            else:  # data.object.op == 'BVV'
-                ival = data.object.args[0]
+            ival = data if type(data) is int else data.object.args[0]
             if endness == "Iend_BE":
                 arange = reversed(arange)
 
@@ -217,14 +214,14 @@ class UltraPage(MemoryObjectMixin, PageBase):
 
     def merge(
         self,
-        others: list["UltraPage"],
+        others: list[UltraPage],
         merge_conditions,
         common_ancestor=None,
-        page_addr: int = None,  # pylint: disable=arguments-differ
+        page_addr: int | None = None,  # pylint: disable=arguments-differ
         memory=None,
         changed_offsets: set[int] | None = None,
     ):
-        all_pages = [self] + others
+        all_pages = [self, *others]
         merged_to = None
         merged_objects = set()
         merged_offsets = set()
@@ -242,7 +239,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
 
             memory_objects: list[tuple[SimMemoryObject, Any]] = []
             concretes: list[tuple[int, Any]] = []
-            unconstrained_in: list[tuple["UltraPage", Any]] = []
+            unconstrained_in: list[tuple[UltraPage, Any]] = []
             our_mo: SimMemoryObject | None = None
 
             # first get a list of all memory objects at that location, and
@@ -285,7 +282,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
                 to_merge = [(mo.object, fv) for mo, fv in memory_objects]
 
                 # Update `merged_to`
-                merged_to = b + list(mo_lengths)[0]
+                merged_to = b + next(iter(mo_lengths))
 
                 merged_val = self._merge_values(to_merge, memory_objects[0][0].length, memory=memory)
                 if merged_val is None:
@@ -295,7 +292,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
                     # this object does not exist in the current page. do the store
                     new_object = SimMemoryObject(merged_val, page_addr + b, memory_objects[0][0].endness)
                     self.store(
-                        b, new_object, size=list(mo_lengths)[0], cooperate=True, page_addr=page_addr, memory=memory
+                        b, new_object, size=next(iter(mo_lengths)), cooperate=True, page_addr=page_addr, memory=memory
                     )
                     merged_objects.add(new_object)
                 else:
@@ -311,7 +308,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
                 # the size of all memory objects and unallocated spaces.
                 min_size = min(mo.length - (page_addr + b - mo.base) for mo, _ in memory_objects)
                 for um, _ in unconstrained_in:
-                    for i in range(0, min_size):
+                    for i in range(min_size):
                         if um._contains(b + i, page_addr):
                             min_size = i
                             break
@@ -352,8 +349,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
                 memoryview(self.concrete_data)[addr : addr + size],
                 memoryview(self.symbolic_bitmap)[addr : addr + size],
             )
-        else:
-            return self.concrete_data[addr : addr + size], memoryview(self.symbolic_bitmap)[addr : addr + size]
+        return self.concrete_data[addr : addr + size], memoryview(self.symbolic_bitmap)[addr : addr + size]
 
     def changed_bytes(self, other, page_addr=None) -> set[int]:
         changed_candidates = super().changed_bytes(other)
@@ -411,9 +407,8 @@ class UltraPage(MemoryObjectMixin, PageBase):
         if not self.symbolic_bitmap[start]:
             # concrete data
             return True
-        else:
-            # symbolic data or does not exist
-            return self._get_object(start, page_addr) is not None
+        # symbolic data or does not exist
+        return self._get_object(start, page_addr) is not None
 
     def _get_object(self, start: int, page_addr: int, memory=None) -> SimMemoryObject | None:
         try:
@@ -422,12 +417,13 @@ class UltraPage(MemoryObjectMixin, PageBase):
             return None
         else:
             obj = self.symbolic_data[place]
-            if obj.includes(start + page_addr):
-                return obj
-            elif memory is not None and obj.includes(start + page_addr + (1 << memory.state.arch.bits)):
+            if (
+                obj.includes(start + page_addr)
+                or memory is not None
+                and obj.includes(start + page_addr + (1 << memory.state.arch.bits))
+            ):
                 return obj
-            else:
-                return None
+            return None
 
     def _get_next_place(self, start):
         try:
@@ -439,7 +435,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
 
     def replace_all_with_offsets(self, offsets: Iterable[int], old: claripy.ast.BV, new: claripy.ast.BV, memory=None):
         memory_objects = set()
-        for offset in sorted(list(offsets)):
+        for offset in sorted(offsets):
             try:
                 a = next(self.symbolic_data.irange(maximum=offset, reverse=True))
             except StopIteration:

angr/storage/memory_mixins/paged_memory/privileged_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from .paged_memory_mixin import PagedMemoryMixin
 
 

angr/storage/memory_mixins/paged_memory/stack_allocation_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 from .paged_memory_mixin import PagedMemoryMixin

angr/storage/memory_mixins/regioned_memory/__init__.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from .regioned_memory_mixin import RegionedMemoryMixin
 from .region_category_mixin import RegionCategoryMixin
 from .static_find_mixin import StaticFindMixin

angr/storage/memory_mixins/regioned_memory/abstract_address_descriptor.py

@@ -1,6 +1,7 @@
+from __future__ import annotations
 from collections.abc import Generator
 
-from claripy.vsa import StridedInterval
+from claripy.ast import BV
 
 
 class AbstractAddressDescriptor:
@@ -12,13 +13,13 @@ class AbstractAddressDescriptor:
     __slots__ = ("_regioned_addrs",)
 
     def __init__(self):
-        self._regioned_addrs: list[tuple[str, StridedInterval]] = []
+        self._regioned_addrs: list[tuple[str, BV]] = []
 
     def __len__(self) -> int:
         # this may raise an OverflowError if self.cardinality is greater than sys.maxint
         return self.cardinality
 
-    def __iter__(self) -> Generator[tuple[str, StridedInterval], None, None]:
+    def __iter__(self) -> Generator[tuple[str, BV]]:
         yield from self._regioned_addrs
 
     @property
@@ -28,7 +29,7 @@ class AbstractAddressDescriptor:
             n += si.cardinality
         return n
 
-    def add_regioned_address(self, region: str, addr: StridedInterval):
+    def add_regioned_address(self, region: str, addr: BV):
         self._regioned_addrs.append((region, addr))
 
     def clear(self):

angr/storage/memory_mixins/regioned_memory/abstract_merger_mixin.py

@@ -1,8 +1,9 @@
+from __future__ import annotations
+
 import logging
 from collections.abc import Iterable
 from typing import Any
 
-import claripy
 
 from .. import MemoryMixin
 
@@ -10,36 +11,20 @@ l = logging.getLogger(name=__name__)
 
 
 class AbstractMergerMixin(MemoryMixin):
-    def _merge_values(self, values: Iterable[tuple[Any, Any]], merged_size: int, **kwargs):
-        # if self.category == 'reg' and self.state.arch.register_endness == 'Iend_LE':
-        #     should_reverse = True
-        # elif self.state.arch.memory_endness == 'Iend_LE':
-        #     should_reverse = True
-        # else:
-        #     should_reverse = False
+    """AbstractMergerMixin handles merging initialized values."""
 
+    def _merge_values(self, values: Iterable[tuple[Any, Any]], merged_size: int, **kwargs):
         values = list(values)
         merged_val = values[0][0]
 
-        # if should_reverse: merged_val = merged_val.reversed
-
         for tm, _ in values[1:]:
-            # if should_reverse: tm = tm.reversed
-
-            if self._is_uninitialized(tm):
+            if tm.uninitialized:
                 continue
             l.info("Merging %s %s...", merged_val, tm)
             merged_val = merged_val.union(tm)
             l.info("... Merged to %s", merged_val)
 
-        # if should_reverse:
-        #     merged_val = merged_val.reversed
-
-        if not values[0][0].uninitialized and claripy.backends.vsa.identical(merged_val, values[0][0]):
+        if not values[0][0].uninitialized and merged_val.identical(values[0][0]):
             return None
 
         return merged_val
-
-    @staticmethod
-    def _is_uninitialized(a):
-        return getattr(claripy.backends.vsa.convert(a), "uninitialized", False)

angr/storage/memory_mixins/regioned_memory/region_category_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from .. import MemoryMixin