angr 9.2.117__py3-none-macosx_11_0_arm64.whl → 9.2.119__py3-none-macosx_11_0_arm64.whl

angr/state_plugins/callstack.py

@@ -1,7 +1,7 @@
+from __future__ import annotations
 import collections
 from itertools import dropwhile
 import logging
-from typing import Optional
 from collections.abc import Iterator
 
 from .plugin import SimStatePlugin
@@ -23,7 +23,7 @@ class CallStack(SimStatePlugin):
         stack_ptr=0,
         ret_addr=0,
         jumpkind="Ijk_Call",
-        next_frame: Optional["CallStack"] = None,
+        next_frame: CallStack | None = None,
         invoke_return_variable=None,
     ):
         super().__init__()
@@ -78,7 +78,7 @@ class CallStack(SimStatePlugin):
     def widen(self, others):  # pylint: disable=unused-argument
         l.warning("Widening not implemented for callstacks")
 
-    def __iter__(self) -> Iterator["CallStack"]:
+    def __iter__(self) -> Iterator[CallStack]:
         """
         Iterate through the callstack, from top to bottom
         (most recent first).
@@ -122,9 +122,11 @@ class CallStack(SimStatePlugin):
         return "<CallStack (depth %d)>" % len(self)
 
     def __str__(self):
-        return "Backtrace:\n%s" % "\n".join(
-            "Frame %d: %#x => %#x, sp = %#x" % (i, f.call_site_addr, f.func_addr, f.stack_ptr)
-            for i, f in enumerate(self)
+        return "Backtrace:\n{}".format(
+            "\n".join(
+                "Frame %d: %#x => %#x, sp = %#x" % (i, f.call_site_addr, f.func_addr, f.stack_ptr)
+                for i, f in enumerate(self)
+            )
         )
 
     def __eq__(self, other):
@@ -202,8 +204,7 @@ class CallStack(SimStatePlugin):
         :return: A string representation
         :rtype: str
         """
-        s = "[" + ",".join([("0x%x" % i) if i is not None else "Unspecified" for i in stack_suffix]) + "]"
-        return s
+        return "[" + ",".join([(f"0x{i:x}") if i is not None else "Unspecified" for i in stack_suffix]) + "]"
 
     @staticmethod
     def _rfind(lst, item):
@@ -219,7 +220,7 @@ class CallStack(SimStatePlugin):
         try:
             return dropwhile(lambda x: lst[x] != item, next(reversed(range(len(lst)))))
         except Exception as e:
-            raise ValueError("%s not in the list" % item) from e
+            raise ValueError(f"{item} not in the list") from e
 
     @property
     def top(self):
@@ -320,9 +321,9 @@ class CallStack(SimStatePlugin):
         for i, frame in enumerate(self):
             s = "%d | %s -> %s, returning to %s" % (
                 i,
-                "None" if frame.call_site_addr is None else "%#x" % frame.call_site_addr,
-                "None" if frame.func_addr is None else "%#x" % frame.func_addr,
-                "None" if frame.current_return_target is None else "%#x" % frame.current_return_target,
+                "None" if frame.call_site_addr is None else f"{frame.call_site_addr:#x}",
+                "None" if frame.func_addr is None else f"{frame.func_addr:#x}",
+                "None" if frame.current_return_target is None else f"{frame.current_return_target:#x}",
             )
             stack.append(s)
 
@@ -342,10 +343,10 @@ class CallStack(SimStatePlugin):
         for frame in self:
             if len(ret) >= context_sensitivity_level * 2:
                 break
-            ret = (frame.call_site_addr, frame.func_addr) + ret
+            ret = (frame.call_site_addr, frame.func_addr, *ret)
 
         while len(ret) < context_sensitivity_level * 2:
-            ret = (None, None) + ret
+            ret = (None, None, *ret)
 
         return ret
 
@@ -381,7 +382,7 @@ class CallStackAction:
         self.action = action
 
         if action not in ("push", "pop"):
-            raise AngrError('Unsupported action string "%s".' % action)
+            raise AngrError(f'Unsupported action string "{action}".')
 
         self.callframe = callframe
         self.ret_site_addr = ret_site_addr
@@ -394,9 +395,9 @@ class CallStackAction:
 
     def __repr__(self):
         if self.action == "push":
-            return "<CallStackAction push with %s>" % self.callframe
-        else:  # pop
-            return "<CallStackAction pop, ret site %#x>" % self.ret_site_addr
+            return f"<CallStackAction push with {self.callframe}>"
+        # pop
+        return f"<CallStackAction pop, ret site {self.ret_site_addr:#x}>"
 
 
 from angr.sim_state import SimState

angr/state_plugins/cgc.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import operator
 from .plugin import SimStatePlugin
 
@@ -83,7 +84,7 @@ class SimStateCGC(SimStatePlugin):
         return not self.state.solver.solution(a != 0, True)
 
     def _combine(self, others):
-        merging_occured = False
+        merging_occurred = False
 
         new_allocation_base = max(o.allocation_base for o in others)
         if self.state.solver.symbolic(new_allocation_base):
@@ -94,9 +95,9 @@ class SimStateCGC(SimStatePlugin):
 
         if concrete_allocation_base != concrete_new_allocation_base:
             self.allocation_base = new_allocation_base
-            merging_occured = True
+            merging_occurred = True
 
-        return merging_occured
+        return merging_occurred
 
     def merge(self, others, merge_conditions, common_ancestor=None):  # pylint: disable=unused-argument
         return self._combine(others)
@@ -116,7 +117,7 @@ class SimStateCGC(SimStatePlugin):
         sinkhole is removed.
         """
 
-        ordered_sinks = sorted(list(self.sinkholes), key=operator.itemgetter(0), reverse=True)
+        ordered_sinks = sorted(self.sinkholes, key=operator.itemgetter(0), reverse=True)
         max_pair = None
         for addr, sz in ordered_sinks:
             if sz >= length:

angr/state_plugins/concrete.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import cle
 import io
 import logging
@@ -43,14 +44,13 @@ class Concrete(SimStatePlugin):
             self.already_sync_objects_addresses = already_sync_objects_addresses
 
     def copy(self, _memo):
-        conc = Concrete(
+        return Concrete(
             segment_registers_initialized=self.segment_registers_initialized,
             segment_registers_callback_initialized=self.segment_registers_callback_initialized,
             whitelist=list(self.whitelist),
             fs_register_bp=self.fs_register_bp,
             already_sync_objects_addresses=list(self.already_sync_objects_addresses),
         )
-        return conc
 
     def merge(self, _others, _merge_conditions, _common_ancestor=None):
         pass
@@ -112,7 +112,7 @@ class Concrete(SimStatePlugin):
             # before let's sync all the subregisters of the current register.
             # sometimes this can be helpful ( i.e. ymmm0 e xmm0 )
             if register.subregisters:
-                subregisters_names = map(lambda x: x[0], register.subregisters)
+                subregisters_names = (x[0] for x in register.subregisters)
                 self._sync_registers(subregisters_names, target)
 
             # finally let's synchronize the whole register
@@ -173,11 +173,10 @@ class Concrete(SimStatePlugin):
         def _check_mapping_name(cle_mapping_name, concrete_mapping_name):
             if cle_mapping_name == concrete_mapping_name:
                 return True
-            else:
-                # removing version and extension information from the library name
-                cle_mapping_name = re.findall(r"[\w']+", cle_mapping_name)
-                concrete_mapping_name = re.findall(r"[\w']+", concrete_mapping_name)
-                return (cle_mapping_name[0] == concrete_mapping_name[0]) if len(concrete_mapping_name) else False
+            # removing version and extension information from the library name
+            cle_mapping_name = re.findall(r"[\w']+", cle_mapping_name)
+            concrete_mapping_name = re.findall(r"[\w']+", concrete_mapping_name)
+            return (cle_mapping_name[0] == concrete_mapping_name[0]) if len(concrete_mapping_name) else False
 
         l.debug("Synchronizing CLE backend with the concrete process memory mapping")
         try:

angr/state_plugins/debug_variables.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from typing import TYPE_CHECKING
 import logging
 
@@ -28,19 +29,19 @@ class SimDebugVariable:
         self.type = var_type
 
     @staticmethod
-    def from_cle_variable(state: SimState, cle_variable: Variable, dwarf_cfa) -> "SimDebugVariable":
+    def from_cle_variable(state: SimState, cle_variable: Variable, dwarf_cfa) -> SimDebugVariable:
         addr = cle_variable.rebased_addr_from_cfa(dwarf_cfa)
         var_type = cle_variable.type
         return SimDebugVariable(state, addr, var_type)
 
     @property
-    def mem_untyped(self) -> "SimMemView":
+    def mem_untyped(self) -> SimMemView:
         if self.addr is None:
             raise Exception("Cannot view a variable without an address")
         return self.state.mem[self.addr]
 
     @property
-    def mem(self) -> "SimMemView":
+    def mem(self) -> SimMemView:
         if isinstance(self.type, TypedefType):
             unpacked = SimDebugVariable(self.state, self.addr, self.type.type)
             return unpacked.mem
@@ -62,12 +63,12 @@ class SimDebugVariable:
     # methods and properties equivalent to SimMemView
 
     @property
-    def string(self) -> "SimMemView":
+    def string(self) -> SimMemView:
         first_char = self.deref
         # first char should have some char type (could be checked here)
         return first_char.mem_untyped.string
 
-    def with_type(self, sim_type: "SimType") -> "SimMemView":
+    def with_type(self, sim_type: SimType) -> SimMemView:
         return self.mem_untyped.with_type(sim_type)
 
     @property
@@ -88,20 +89,20 @@ class SimDebugVariable:
     def __getitem__(self, i):
         if isinstance(i, int):
             return self.array(i)
-        elif isinstance(i, str):
+        if isinstance(i, str):
             return self.member(i)
         raise KeyError
 
     @property
-    def deref(self) -> "SimDebugVariable":
+    def deref(self) -> SimDebugVariable:
         # dereferincing is equivalent to getting the first array element
         return self.array(0)
 
-    def array(self, i) -> "SimDebugVariable":
+    def array(self, i) -> SimDebugVariable:
         if isinstance(self.type, TypedefType):
             unpacked = SimDebugVariable(self.state, self.addr, self.type.type)
             return unpacked.array(i)
-        elif isinstance(self.type, ArrayType):
+        if isinstance(self.type, ArrayType):
             # an array already addresses its first element
             addr = self.addr
             el_type = self.type.element_type
@@ -122,16 +123,13 @@ class SimDebugVariable:
             new_addr = addr + i * el_type.byte_size
         return SimDebugVariable(self.state, new_addr, el_type)
 
-    def member(self, member_name: str) -> "SimDebugVariable":
+    def member(self, member_name: str) -> SimDebugVariable:
         if isinstance(self.type, TypedefType):
             unpacked = SimDebugVariable(self.state, self.addr, self.type.type)
             return unpacked.member(member_name)
-        elif isinstance(self.type, StructType):
+        if isinstance(self.type, StructType):
             member = self.type[member_name]
-            if self.addr is None:
-                addr = None
-            else:
-                addr = self.addr + member.addr_offset
+            addr = None if self.addr is None else self.addr + member.addr_offset
             return SimDebugVariable(self.state, addr, member.type)
 
         raise Exception(f"{self.type} object has no members")
@@ -142,7 +140,7 @@ class SimDebugVariablePlugin(SimStatePlugin):
     This is the plugin you'll use to interact with (global/local) program variables.
     These variables have a name and a visibility scope which depends on the pc address of the state.
     With this plugin, you can access/modify the value of such variable or find its memory address.
-    For creating program varibles, or for importing them from cle, see the knowledge plugin debug_variables.
+    For creating program variables, or for importing them from cle, see the knowledge plugin debug_variables.
     Run ``p.kb.dvars.load_from_dwarf()`` before using this plugin.
 
     Example:
@@ -186,7 +184,7 @@ class SimDebugVariablePlugin(SimStatePlugin):
         # FIXME This is only an approximation!
         if self.state.arch.name == "AMD64":
             return self.state.regs.rbp + 16
-        elif self.state.arch.name == "X86":
+        if self.state.arch.name == "X86":
             return self.state.regs.ebp + 8
         return 0
 

angr/state_plugins/filesystem.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import os
 import logging
 from collections import namedtuple
@@ -108,10 +109,8 @@ class SimFilesystem(SimStatePlugin):  # pretends links don't exist
         for fname in self._mountpoints:
             try:
                 subdeck = [o._mountpoints[fname] for o in others]
-            except KeyError:
-                raise SimMergeError(
-                    "Can't merge filesystems with disparate file sets"
-                )  # pylint: disable=raise-missing-from
+            except KeyError as err:
+                raise SimMergeError("Can't merge filesystems with disparate file sets") from err
 
             if common_ancestor is not None and fname in common_ancestor._mountpoints:
                 common_mp = common_ancestor._mountpoints[fname]
@@ -121,10 +120,10 @@ class SimFilesystem(SimStatePlugin):  # pretends links don't exist
             self._mountpoints[fname].merge(subdeck, merge_conditions, common_ancestor=common_mp)
 
         # this is a little messy
-        deck = [self] + others
+        deck = [self, *others]
         all_files = set.union(*(set(o._files.keys()) for o in deck))
         for fname in all_files:
-            subdeck = [o._files[fname] if fname in o._files else None for o in deck]
+            subdeck = [o._files.get(fname, None) for o in deck]
             representative = next(x for x in subdeck if x is not None)
             for i, v in enumerate(subdeck):
                 if v is None:
@@ -158,9 +157,7 @@ class SimFilesystem(SimStatePlugin):  # pretends links don't exist
         keys = path.split(self.pathsep)
         i = 0
         while i < len(keys):
-            if keys[i] == b"":
-                keys.pop(i)
-            elif keys[i] == b".":
+            if keys[i] == b"" or keys[i] == b".":
                 keys.pop(i)
             elif keys[i] == b"..":
                 keys.pop(i)
@@ -191,8 +188,7 @@ class SimFilesystem(SimStatePlugin):  # pretends links don't exist
 
         if mountpoint is None:
             return self._files.get(self._join_chunks(chunks))
-        else:
-            return mountpoint.get(chunks)
+        return mountpoint.get(chunks)
 
     def insert(self, path, simfile):
         """
@@ -205,8 +201,7 @@ class SimFilesystem(SimStatePlugin):  # pretends links don't exist
         if mountpoint is None:
             self._files[self._join_chunks(chunks)] = simfile
             return True
-        else:
-            return mountpoint.insert(chunks, simfile)
+        return mountpoint.insert(chunks, simfile)
 
     def delete(self, path):
         """
@@ -370,7 +365,7 @@ class SimConcreteFilesystem(SimMount):
             self.cache[fname].set_state(state)
 
     def merge(self, others, merge_conditions, common_ancestor=None):
-        merging_occured = False
+        merging_occurred = False
 
         for o in others:
             if o.pathsep != self.pathsep:
@@ -378,7 +373,7 @@ class SimConcreteFilesystem(SimMount):
             if o.deleted_list != self.deleted_list:
                 raise SimMergeError("Can't merge concrete filesystems with disparate deleted files")
 
-        deck = [self] + others
+        deck = [self, *others]
         all_files = set.union(*(set(o._files.keys()) for o in deck))
         for fname in all_files:
             subdeck = []
@@ -396,8 +391,8 @@ class SimConcreteFilesystem(SimMount):
             else:
                 common_simfile = None
 
-            merging_occured |= subdeck[0].merge(subdeck[1:], merge_conditions, common_ancestor=common_simfile)
-        return merging_occured
+            merging_occurred |= subdeck[0].merge(subdeck[1:], merge_conditions, common_ancestor=common_simfile)
+        return merging_occurred
 
     def widen(self, others):  # pylint: disable=unused-argument
         if once("host_fs_widen_warning"):
@@ -446,7 +441,7 @@ class SimHostFilesystem(SimConcreteFilesystem):
             if dereference:
                 path = os.path.realpath(path)
             s = os.stat(path)
-            stat = Stat(
+            return Stat(
                 s.st_dev,
                 s.st_ino,
                 s.st_nlink,
@@ -464,6 +459,5 @@ class SimHostFilesystem(SimConcreteFilesystem):
                 round(s.st_ctime),
                 s.st_ctime_ns,
             )
-            return stat
         except OSError:
             return None

angr/state_plugins/gdb.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import os
 import re
 import logging
@@ -124,8 +125,8 @@ class GDB(SimStatePlugin):
     def _read_data(path):
         if not os.path.exists(path):
             raise SimStateError("File does not exist")
-        f = open(path, "rb")
-        return f.read()
+        with open(path, "rb") as f:
+            return f.read()
 
     def _write(self, addr, data):
         self.state.memory.store(addr, data)

angr/state_plugins/globals.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 from .plugin import SimStatePlugin
@@ -15,7 +16,7 @@ class SimStateGlobals(SimStatePlugin):
 
     def merge(self, others, merge_conditions, common_ancestor=None):  # pylint: disable=unused-argument
         for other in others:
-            for k in other.keys():
+            for k in other:
                 if k not in self:
                     self[k] = other[k]
 
@@ -25,6 +26,9 @@ class SimStateGlobals(SimStatePlugin):
         l.warning("Widening is unimplemented for globals")
         return False
 
+    def __iter__(self):
+        return iter(self._backer)
+
     def __getitem__(self, k):
         return self._backer[k]
 

angr/state_plugins/heap/__init__.py

@@ -1,4 +1,5 @@
 # pylint:disable=wildcard-import
+from __future__ import annotations
 from .heap_base import *
 from .heap_brk import *
 from .heap_libc import *

angr/state_plugins/heap/heap_base.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from ..plugin import SimStatePlugin
 
 from ...errors import SimMemoryError

angr/state_plugins/heap/heap_brk.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 import claripy
@@ -62,7 +63,7 @@ class SimHeapBrk(SimHeapBase):
         """
         requested = self._conc_alloc_size(sim_size)
         used = self.heap_location - self.heap_base
-        released = requested if requested <= used else used
+        released = min(requested, used)
         self.heap_location -= released
         l.debug("Releasing %d bytes from the heap (%d bytes were requested to be released)", released, requested)
 
@@ -89,9 +90,12 @@ class SimHeapBrk(SimHeapBase):
 
         final_size = size * nmemb
 
-        if self.state.solver.symbolic(sim_nmemb) or self.state.solver.symbolic(sim_size):
-            if final_size > plugin.max_variable_size:
-                final_size = plugin.max_variable_size
+        if (
+            self.state.solver.symbolic(sim_nmemb)
+            or self.state.solver.symbolic(sim_size)
+            and final_size > plugin.max_variable_size
+        ):
+            final_size = plugin.max_variable_size
 
         addr = self.state.heap.allocate(final_size)
         v = claripy.BVV(0, final_size * 8)
@@ -121,8 +125,7 @@ class SimHeapBrk(SimHeapBase):
         if self.heap_location != new_heap_location:
             self.heap_location = new_heap_location
             return True
-        else:
-            return False
+        return False
 
     def merge(self, others, merge_conditions, common_ancestor=None):  # pylint:disable=unused-argument
         return self._combine(others)

angr/state_plugins/heap/heap_freelist.py

@@ -1,20 +1,24 @@
+from __future__ import annotations
+import logging
 from . import SimHeapLibc
 from .utils import concretize
 from ...errors import SimHeapError
 
-import logging
 
 l = logging.getLogger("angr.state_plugins.heap.heap_freelist")
 
 
 class Chunk:
     """
-    The sort of chunk as would typically be found in a freelist-style heap implementation. Provides a representation of
-    a chunk via a view into the memory plugin. Chunks may be adjacent, in different senses, to as many as four other
-    chunks. For any given chunk, two of these chunks are adjacent to it in memory, and are referred to as the "previous"
-    and "next" chunks throughout this implementation. For any given free chunk, there may also be two significant chunks
-    that are adjacent to it in some linked list of free chunks. These chunks are referred to the "backward" and "foward"
-    chunks relative to the chunk in question.
+    The sort of chunk as would typically be found in a freelist-style heap
+    implementation. Provides a representation of a chunk via a view into the
+    memory plugin. Chunks may be adjacent, in different senses, to as many as
+    four other chunks. For any given chunk, two of these chunks are adjacent to
+    it in memory, and are referred to as the "previous" and "next" chunks
+    throughout this implementation. For any given free chunk, there may also be
+    two significant chunks that are adjacent to it in some linked list of free
+    chunks. These chunks are referred to the "backward" and "forward" chunks
+    relative to the chunk in question.
 
     :ivar base: the location of the base of the chunk in memory
     :ivar state: the program state that the chunk is resident in
@@ -106,8 +110,7 @@ class Chunk:
     def _compare(self, other, comparison):
         if self.state is other.state:
             return comparison
-        else:
-            raise SimHeapError("Chunks must originate from the same simulation state to be compared!")
+        raise SimHeapError("Chunks must originate from the same simulation state to be compared!")
 
     def __lt__(self, other):
         """

angr/state_plugins/heap/heap_libc.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from . import SimHeapBase