angr 9.2.116__py3-none-manylinux2014_aarch64.whl → 9.2.117__py3-none-manylinux2014_aarch64.whl

angr/storage/file.py

@@ -1,7 +1,8 @@
-import claripy
 import logging
 import itertools
 
+import claripy
+
 from .memory_mixins import DefaultMemory
 from ..state_plugins.plugin import SimStatePlugin
 from ..state_plugins.sim_action_object import SimActionObject
@@ -291,19 +292,19 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
         # If it's not possible to EOF (because there's no EOF), this is very simple!
         if not self.has_end:
             # bump the storage size as we read
-            self._size = self.state.solver.If(size + pos > self._size, size + pos, self._size)
+            self._size = claripy.If(size + pos > self._size, size + pos, self._size)
             return self.load(pos, passed_max_size, disable_actions=disable_actions, inspect=inspect), size, size + pos
 
         # Step 2.2: check harder for the possibility of EOFs
         # This is the size if we're reading to the end of the file
         distance_to_eof = self._size - pos
-        distance_to_eof = self.state.solver.If(self.state.solver.SLE(distance_to_eof, 0), 0, distance_to_eof)
+        distance_to_eof = claripy.If(claripy.SLE(distance_to_eof, 0), 0, distance_to_eof)
 
         # try to frontload some constraint solving to see if it's impossible for this read to EOF
         if self.state.solver.satisfiable(extra_constraints=(size > distance_to_eof,)):
             # it's possible to EOF
             # final size = min(passed_size, max(distance_to_eof, 0))
-            real_size = self.state.solver.If(size >= distance_to_eof, distance_to_eof, size)
+            real_size = claripy.If(size >= distance_to_eof, distance_to_eof, size)
 
             return (
                 self.load(pos, passed_max_size, disable_actions=disable_actions, inspect=inspect),
@@ -327,7 +328,7 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
         # \(_^^)/
         self.store(pos, data, size=size)
         new_end = _deps_unpack(pos + size)[0]  # decline to store SAO
-        self._size = self.state.solver.If(new_end > self._size, new_end, self._size)
+        self._size = claripy.If(new_end > self._size, new_end, self._size)
         return new_end
 
     @SimStatePlugin.memo
@@ -349,7 +350,7 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
         if any(o.has_end != self.has_end for o in others):
             raise SimMergeError("Cannot merge files where some have ends and some don't")
 
-        self._size = self.state.solver.ite_cases(zip(merge_conditions[1:], (o._size for o in others)), self._size)
+        self._size = claripy.ite_cases(zip(merge_conditions[1:], (o._size for o in others)), self._size)
 
         return super().merge(others, merge_conditions, common_ancestor=common_ancestor)
 
@@ -378,7 +379,7 @@ class SimFileStream(SimFile):
     def set_state(self, state):
         super().set_state(state)
         if type(self.pos) is int:
-            self.pos = state.solver.BVV(self.pos, state.arch.bits)
+            self.pos = claripy.BVV(self.pos, state.arch.bits)
         elif len(self.pos) != state.arch.bits:
             raise TypeError("SimFileStream position must be a bitvector of size %d (arch.bits)" % state.arch.bits)
 
@@ -402,7 +403,7 @@ class SimFileStream(SimFile):
         return c
 
     def merge(self, others, merge_conditions, common_ancestor=None):  # pylint: disable=unused-argument
-        self.pos = self.state.solver.ite_cases(zip(merge_conditions[1:], [o.pos for o in others]), self.pos)
+        self.pos = claripy.ite_cases(zip(merge_conditions[1:], [o.pos for o in others]), self.pos)
         return super().merge(others, merge_conditions, common_ancestor=common_ancestor)
 
 
@@ -525,7 +526,7 @@ class SimPackets(SimFileBase):
 
         # Type check
         if type(size) is int:
-            size = self.state.solver.BVV(size, self.state.arch.bits)
+            size = claripy.BVV(size, self.state.arch.bits)
 
         # The read is on the frontier. let's generate a new packet.
         orig_size = size
@@ -596,7 +597,7 @@ class SimPackets(SimFileBase):
         if size is None:
             size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
         if type(size) is int:
-            size = self.state.solver.BVV(size, self.state.arch.bits)
+            size = claripy.BVV(size, self.state.arch.bits)
 
         # sanity check on packet number and determine if data is already present
         if pos is None:
@@ -641,16 +642,14 @@ class SimPackets(SimFileBase):
 
         for i, default in enumerate(self.content):
             max_data_length = max(len(default[0]), max(len(o.content[i][0]) for o in others))
-            merged_data = self.state.solver.ite_cases(
+            merged_data = claripy.ite_cases(
                 zip(
                     merge_conditions[1:],
                     (o.content[i][0].concat(claripy.BVV(0, max_data_length - len(o.content[i][0]))) for o in others),
                 ),
                 default[0],
             )
-            merged_size = self.state.solver.ite_cases(
-                zip(merge_conditions[1:], (o.content[i][1] for o in others)), default[1]
-            )
+            merged_size = claripy.ite_cases(zip(merge_conditions[1:], (o.content[i][1] for o in others)), default[1])
             self.content[i] = (merged_data, merged_size)
 
         return True
@@ -917,7 +916,7 @@ class SimFileDescriptor(SimFileDescriptorBase):
             return claripy.false
 
         if type(offset) is int:
-            offset = self.state.solver.BVV(offset, self.state.arch.bits)
+            offset = claripy.BVV(offset, self.state.arch.bits)
 
         if whence == "start":
             new_pos = offset
@@ -926,10 +925,8 @@ class SimFileDescriptor(SimFileDescriptorBase):
         elif whence == "end":
             new_pos = self.file.size + offset
 
-        success_condition = self.state.solver.And(
-            self.state.solver.SGE(new_pos, 0), self.state.solver.SLE(new_pos, self.file.size)
-        )
-        self._pos = _deps_unpack(self.state.solver.If(success_condition, new_pos, self._pos))[0]
+        success_condition = claripy.And(claripy.SGE(new_pos, 0), claripy.SLE(new_pos, self.file.size))
+        self._pos = _deps_unpack(claripy.If(success_condition, new_pos, self._pos))[0]
         return success_condition
 
     def eof(self):
@@ -1006,7 +1003,7 @@ class SimFileDescriptor(SimFileDescriptorBase):
         elif self._pos is None or any(o._pos is None for o in others):
             raise SimMergeError("Cannot merge SimFileDescriptors with inconsistent None-position - please report this!")
         else:
-            self._pos = self.state.solver.ite_cases(zip(merge_conditions[1:], (o._pos for o in others)), self._pos)
+            self._pos = claripy.ite_cases(zip(merge_conditions[1:], (o._pos for o in others)), self._pos)
 
         return True
 
@@ -1113,9 +1110,7 @@ class SimFileDescriptorDuplex(SimFileDescriptorBase):
         elif self._read_pos is None or any(o._read_pos is None for o in others):
             raise SimMergeError("Cannot merge SimFileDescriptors with inconsistent None-position - please report this!")
         else:
-            self._read_pos = self.state.solver.ite_cases(
-                zip(merge_conditions[1:], (o._read_pos for o in others)), self._read_pos
-            )
+            self._read_pos = claripy.ite_cases(zip(merge_conditions[1:], (o._read_pos for o in others)), self._read_pos)
 
         if type(self._write_pos) is int and all(type(o._write_pos) is int for o in others):
             if any(o._write_pos != self._write_pos for o in others):
@@ -1125,7 +1120,7 @@ class SimFileDescriptorDuplex(SimFileDescriptorBase):
         elif self._write_pos is None or any(o._write_pos is None for o in others):
             raise SimMergeError("Cannot merge SimFileDescriptors with inconsistent None-position - please report this!")
         else:
-            self._write_pos = self.state.solver.ite_cases(
+            self._write_pos = claripy.ite_cases(
                 zip(merge_conditions[1:], (o._write_pos for o in others)), self._write_pos
             )
 
@@ -1159,7 +1154,7 @@ class SimPacketsSlots(SimFileBase):
 
     def read(self, pos, size, **kwargs):
         if not self.read_sizes:
-            return self.state.solver.BVV(0, 0), 0, None
+            return claripy.BVV(0, 0), 0, None
 
         try:
             req_size = self.state.solver.eval_one(size)
@@ -1206,7 +1201,7 @@ class SimPacketsSlots(SimFileBase):
             raise SimMergeError("Can't merge SimPacketsSlots with disparate reads")
 
         for i, default_var in self.read_data:
-            self.read_data[i] = self.state.solver.ite_cases(
+            self.read_data[i] = claripy.ite_cases(
                 zip(merge_conditions[1:], [o.read_data[i] for o in others]), default_var
             )
 

angr/storage/memory_mixins/actions_mixin.py

@@ -1,3 +1,5 @@
+import claripy
+
 from ...state_plugins.sim_action import SimActionData, SimActionObject
 from ... import sim_options as o
 from . import MemoryMixin
@@ -43,12 +45,12 @@ class ActionsMixinHigh(MemoryMixin):
             self.state, region_type, kind, addr=addr, data=data, size=ref_size, condition=condition, fallback=fallback
         )
 
-        action.added_constraints = self.state.solver.true
+        action.added_constraints = claripy.true
         return action
 
     def _add_constraints(self, c, action=None, **kwargs):
         if action is not None:
-            action.added_constraints = self.state.solver.And(action.added_constraints, c)
+            action.added_constraints = claripy.And(action.added_constraints, c)
         return super()._add_constraints(c, action=action, **kwargs)
 
 

angr/storage/memory_mixins/address_concretization_mixin.py

@@ -255,7 +255,7 @@ class AddressConcretizationMixin(MemoryMixin):
         if read_value is None:
             return sub_value
         else:
-            return self.state.solver.If(addr == concrete_addr, sub_value, read_value)
+            return claripy.If(addr == concrete_addr, sub_value, read_value)
 
     def load(self, addr, size=None, condition=None, **kwargs):
         if type(size) is not int:
@@ -285,7 +285,7 @@ class AddressConcretizationMixin(MemoryMixin):
         if not trivial:
             # apply the concretization results to the state
             constraint_options = [addr == concrete_addr for concrete_addr in concrete_addrs]
-            conditional_constraint = self.state.solver.Or(*constraint_options)
+            conditional_constraint = claripy.Or(*constraint_options)
             self._add_constraints(conditional_constraint, condition=condition, **kwargs)
 
         # quick optimization to not introduce the DUMMY value if there's only one loop
@@ -338,7 +338,7 @@ class AddressConcretizationMixin(MemoryMixin):
         if not trivial:
             # apply the concretization results to the state
             constraint_options = [addr == concrete_addr for concrete_addr in concrete_addrs]
-            conditional_constraint = self.state.solver.Or(*constraint_options)
+            conditional_constraint = claripy.Or(*constraint_options)
             self._add_constraints(conditional_constraint, condition=condition, **kwargs)
 
             if len(concrete_addrs) == 1:

angr/storage/memory_mixins/default_filler_mixin.py

@@ -1,5 +1,7 @@
 import logging
 
+import claripy
+
 from . import MemoryMixin
 from ... import sim_options as options
 from ...misc.ux import once
@@ -15,7 +17,7 @@ class DefaultFillerMixin(MemoryMixin):
         if self.state.project and self.state.project.concrete_target:
             mem = self.state.project.concrete_target.read_memory(addr, size)
             endness = kwargs["endness"]
-            bvv = self.state.solver.BVV(mem)
+            bvv = claripy.BVV(mem)
             return bvv if endness == "Iend_BE" else bvv.reversed
 
         if fill_missing is False:
@@ -25,13 +27,13 @@ class DefaultFillerMixin(MemoryMixin):
 
         if type(addr) is int:
             if self.category == "mem" and options.ZERO_FILL_UNCONSTRAINED_MEMORY in self.state.options:
-                return self.state.solver.BVV(0, bits)
+                return claripy.BVV(0, bits)
             elif self.category == "reg" and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options:
-                return self.state.solver.BVV(0, bits)
+                return claripy.BVV(0, bits)
 
         if self.category == "reg" and type(addr) is int and addr == self.state.arch.ip_offset:
             # short-circuit this pathological case
-            return self.state.solver.BVV(0, self.state.arch.bits)
+            return claripy.BVV(0, self.state.arch.bits)
 
         is_mem = (
             self.category == "mem"

angr/storage/memory_mixins/javavm_memory/javavm_memory_mixin.py

@@ -1,6 +1,8 @@
-import os
 import binascii
 import logging
+import os
+
+import claripy
 
 from .... import concretization_strategies
 from ....errors import SimUnsatError, SimMemoryAddressError
@@ -188,7 +190,7 @@ class JavaVmMemoryMixin(MemoryMixin):
                     )
 
             # constraint start_idx, s.t. it evals to one of the concretized indexes
-            constraint_on_start_idx = self.state.solver.Or(*start_idx_options)
+            constraint_on_start_idx = claripy.Or(*start_idx_options)
             self.state.add_constraints(constraint_on_start_idx)
 
     def _store_array_element_on_heap(self, array, idx, value, value_type, store_condition=None):
@@ -197,7 +199,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         if store_condition is not None:
             current_value = self._load_array_element_from_heap(array, idx)
             new_value = value
-            value = self.state.solver.If(store_condition, new_value, current_value)
+            value = claripy.If(store_condition, new_value, current_value)
         self.heap.store(heap_elem_id, value, value_type)
 
     #
@@ -256,11 +258,11 @@ class JavaVmMemoryMixin(MemoryMixin):
                     # => if concrete_start_idx == start_idx
                     #    then use new value
                     #    else use the current value
-                    load_values[i] = self.state.solver.If(concrete_start_idx == start_idx, value, load_values[i])
+                    load_values[i] = claripy.If(concrete_start_idx == start_idx, value, load_values[i])
                 start_idx_options.append(start_idx == concrete_start_idx)
 
             # constraint start_idx, s.t. it evals to one of the concretized indexes
-            constraint_on_start_idx = self.state.solver.Or(*start_idx_options)
+            constraint_on_start_idx = claripy.Or(*start_idx_options)
             self.state.add_constraints(constraint_on_start_idx)
 
         return load_values

angr/storage/memory_mixins/paged_memory/paged_memory_mixin.py

@@ -323,7 +323,7 @@ class PagedMemoryMixin(MemoryMixin):
             raise SimMemoryError("%#x is not mapped" % addr) from e
 
         if type(permissions) is int:
-            permissions = self.state.solver.BVV(permissions, 3)
+            permissions = claripy.BVV(permissions, 3)
 
         result = page.permissions
         if permissions is not None:

angr/storage/memory_mixins/regioned_memory/abstract_merger_mixin.py

@@ -35,7 +35,7 @@ class AbstractMergerMixin(MemoryMixin):
         # if should_reverse:
         #     merged_val = merged_val.reversed
 
-        if not values[0][0].uninitialized and self.state.solver.backends.vsa.identical(merged_val, values[0][0]):
+        if not values[0][0].uninitialized and claripy.backends.vsa.identical(merged_val, values[0][0]):
             return None
 
         return merged_val

angr/storage/memory_mixins/regioned_memory/region_data.py

@@ -1,5 +1,7 @@
 from sortedcontainers import SortedDict
 
+import claripy
+
 from ....errors import SimRegionMapError
 from ....state_plugins import SimStatePlugin
 
@@ -50,7 +52,7 @@ class AddressWrapper:
         :param state: A state
         :return: The converted ValueSet instance
         """
-        return state.solver.VS(state.arch.bits, self.region, self.region_base_addr, self.address)
+        return claripy.VS(state.arch.bits, self.region, self.region_base_addr, self.address)
 
 
 class RegionDescriptor:

angr/storage/memory_mixins/regioned_memory/region_meta_mixin.py

@@ -74,7 +74,7 @@ class MemoryRegionMetaMixin(MemoryMixin):
             aloc_id = bbl_addr
 
         if aloc_id not in self.alocs:
-            self.alocs[aloc_id] = self.state.solver.AbstractLocation(
+            self.alocs[aloc_id] = AbstractLocation(
                 bbl_addr, stmt_id, self.id, region_offset=addr, size=len(data) // self.state.arch.byte_width
             )
             return super().store(addr, data, endness=endness, **kwargs)

angr/storage/memory_mixins/regioned_memory/regioned_memory_mixin.py

@@ -58,7 +58,7 @@ class RegionedMemoryMixin(MemoryMixin):
 
         if regioned_memory_cls is None:
             # delayed import
-            from .. import RegionedMemory
+            from .. import RegionedMemory  # pylint:disable=import-outside-toplevel
 
             regioned_memory_cls = RegionedMemory
 
@@ -176,7 +176,7 @@ class RegionedMemoryMixin(MemoryMixin):
             r, s, i = self._regions[region].find(si, data, max_search, **kwargs)
             # Post-process r so that it's still a ValueSet
             region_base_addr = self._region_base(region)
-            r = self.state.solver.ValueSet(r.size(), region, region_base_addr, claripy.backends.vsa.convert(r))
+            r = claripy.ValueSet(r.size(), region, region_base_addr, claripy.backends.vsa.convert(r))
             return r, s, i
 
     def set_state(self, state):
@@ -424,8 +424,9 @@ class RegionedMemoryMixin(MemoryMixin):
 
             return AddressWrapper(new_region_id, self._region_base(new_region_id), new_relative_address, False, None)
 
-    def _apply_condition_to_symbolic_addr(self, addr, condition):
-        _, converted = self.state.solver.constraint_to_si(condition)
+    @staticmethod
+    def _apply_condition_to_symbolic_addr(addr, condition):
+        _, converted = claripy.constraint_to_si(condition)
         for original_expr, constrained_expr in converted:
             addr = addr.replace(original_expr, constrained_expr)
         return addr

angr/storage/memory_mixins/simple_interface_mixin.py

@@ -36,9 +36,9 @@ class SimpleInterfaceMixin(MemoryMixin):
 
     def _translate_data(self, d, size):
         if type(d) in (bytes, bytearray):
-            return self.state.solver.BVV(d)
+            return claripy.BVV(d)
         elif type(d) is int:
-            return self.state.solver.BVV(d, size * self.state.arch.byte_width)
+            return claripy.BVV(d, size * self.state.arch.byte_width)
         elif isinstance(d, claripy.ast.Base):
             return d
         else:

angr/storage/memory_mixins/size_resolution_mixin.py

@@ -1,5 +1,7 @@
 import logging
 
+import claripy
+
 from . import MemoryMixin
 from ...errors import SimMemoryLimitError, SimMemoryError, SimUnsatError
 
@@ -133,7 +135,7 @@ class SizeConcretizationMixin(MemoryMixin):
             conc_sizes = [min(cs, self._max_symbolic_size) for cs in conc_sizes]
 
         if condition is None:
-            condition = self.state.solver.true
+            condition = claripy.true
         for conc_size in conc_sizes:
             if conc_size == 0:
                 continue

angr/storage/memory_mixins/slotted_memory.py

@@ -38,7 +38,7 @@ class SlottedMemoryMixin(MemoryMixin):
                 addr,
                 0,
                 self.width,
-                self.state.solver.ite_cases(
+                claripy.ite_cases(
                     zip(merge_conditions[1:], (o._single_load(addr, 0, self.width) for o in others)),
                     self._single_load(addr, 0, self.width),
                 ),

angr/storage/memory_mixins/smart_find_mixin.py

@@ -98,7 +98,7 @@ class SmartFindMixin(MemoryMixin):
         able to handle wide characters
         """
         if condition is None:
-            condition = self.state.solver.true
+            condition = claripy.true
         chunk = None
         chunk_progress = chunk_size
 
@@ -155,5 +155,5 @@ class SmartFindMixin(MemoryMixin):
             default = claripy.BVV(0, self.state.arch.bits)
         if cases and cases[-1][0].is_true():
             default = cases.pop(-1)[1]
-        result = self.state.solver.ite_cases(cases, default)
+        result = claripy.ite_cases(cases, default)
         return result, constraints, match_indices

angr/storage/memory_mixins/symbolic_merger_mixin.py

@@ -1,12 +1,14 @@
-from typing import Any
 from collections.abc import Iterable
+from typing import Any
+
+import claripy
 
 from . import MemoryMixin
 
 
 class SymbolicMergerMixin(MemoryMixin):
     def _merge_values(self, values: Iterable[tuple[Any, Any]], merged_size: int, **kwargs):
-        merged_val = self.state.solver.BVV(0, merged_size * self.state.arch.byte_width)
+        merged_val = claripy.BVV(0, merged_size * self.state.arch.byte_width)
         for tm, fv in values:
-            merged_val = self.state.solver.If(fv, tm, merged_val)
+            merged_val = claripy.If(fv, tm, merged_val)
         return merged_val

angr/tablespecs.py

@@ -62,7 +62,7 @@ class StringTableSpec:
 
     def dump(self, state, end_addr, align=0x10):
         if isinstance(end_addr, int):
-            end_addr = state.solver.BVV(end_addr, state.arch.bits)
+            end_addr = claripy.BVV(end_addr, state.arch.bits)
         ptr_size = len(self._contents) * state.arch.bytes
         size = self._str_len + ptr_size
         start_addr = end_addr - size
@@ -80,11 +80,11 @@ class StringTableSpec:
                 str_i += len(item) // self._byte_width
             else:
                 if isinstance(item, int):
-                    item = state.solver.BVV(item, state.arch.bits)
+                    item = claripy.BVV(item, state.arch.bits)
                 state.memory.store(ptr_i, item, endness=state.arch.memory_endness)
                 ptr_i += state.arch.bytes
 
         if zero_fill != 0:
-            state.memory.store(end_addr - zero_fill, state.solver.BVV(0, self._byte_width * zero_fill))
+            state.memory.store(end_addr - zero_fill, claripy.BVV(0, self._byte_width * zero_fill))
 
         return start_addr

{angr-9.2.116.dist-info → angr-9.2.117.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: angr
-Version: 9.2.116
+Version: 9.2.117
 Summary: A multi-architecture binary analysis toolkit, with the ability to perform dynamic symbolic execution and various static analyses on binaries
 Home-page: https://github.com/angr/angr
 License: BSD-2-Clause
@@ -15,13 +15,13 @@ Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: CppHeaderParser
 Requires-Dist: GitPython
-Requires-Dist: ailment==9.2.116
-Requires-Dist: archinfo==9.2.116
+Requires-Dist: ailment==9.2.117
+Requires-Dist: archinfo==9.2.117
 Requires-Dist: cachetools
 Requires-Dist: capstone==5.0.2
 Requires-Dist: cffi>=1.14.0
-Requires-Dist: claripy==9.2.116
-Requires-Dist: cle==9.2.116
+Requires-Dist: claripy==9.2.117
+Requires-Dist: cle==9.2.117
 Requires-Dist: dpkt
 Requires-Dist: itanium-demangler
 Requires-Dist: mulpyplexer
@@ -31,7 +31,7 @@ Requires-Dist: protobuf>=3.19.0
 Requires-Dist: psutil
 Requires-Dist: pycparser>=2.18
 Requires-Dist: pyformlang
-Requires-Dist: pyvex==9.2.116
+Requires-Dist: pyvex==9.2.117
 Requires-Dist: rich>=13.1.0
 Requires-Dist: rpyc
 Requires-Dist: sortedcontainers