FABulous-FPGA 2__py3-none-any.whl

fabulous/__init__.py

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+"""FABulous FPGA framework package.
+
+This file marks the FABulous directory as a Python package so Sphinx and tools can
+import modules (e.g., FABulous.fabric_definition) during documentation builds.
+"""

fabulous/custom_exception.py

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+"""Custom exception classes for the FABulous framework.
+
+This module defines all custom exceptions used throughout the FABulous framework for
+better error handling and debugging. Each exception class is designed for specific error
+scenarios that can occur during fabric generation, parsing, and configuration.
+"""
+
+
+class CommandError(Exception):
+    """Exception raised for errors in the command execution."""
+
+
+class EnvironmentNotSet(Exception):
+    """Exception raised when the environment is not set."""
+
+
+class InvalidFileType(Exception):
+    """Exception raised for unsupported file types."""
+
+
+class FabricParsingError(Exception):
+    """Exception raised for errors in fabric parsing."""
+
+
+class SpecMissMatch(Exception):
+    """Exception raised when a required FASM file is missing."""
+
+
+class InvalidPortType(Exception):
+    """Exception raised for invalid port types."""
+
+
+class InvalidFabricDefinition(Exception):
+    """Exception raised for invalid fabric definitions."""
+
+
+class InvalidFabricParameter(Exception):
+    """Exception raised for invalid fabric parameters."""
+
+
+class InvalidSwitchMatrixDefinition(Exception):
+    """Exception raised for invalid matrix definitions."""
+
+
+class InvalidListFileDefinition(Exception):
+    """Exception raised for invalid list file formats."""
+
+
+class InvalidTileDefinition(Exception):
+    """Exception raised for invalid tile definitions."""
+
+
+class InvalidSupertileDefinition(Exception):
+    """Exception raised for invalid supertile definitions."""
+
+
+class InvalidBelDefinition(Exception):
+    """Exception raised for invalid BEL definitions."""
+
+
+class PipelineCommandError(Exception):
+    """Exception raised for errors in command line arguments."""
+
+
+class InvalidState(Exception):
+    """Exception raised for invalid state during fabric generation."""

fabulous/fabric_cad/README.md

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+# FABulous bitstream generation
+
+## Bitstream for a single tile
+
+The fabric description file contains a table with the allocation of all tiles, like for example:
+
+|FabricBegin| | | | | | | | | |
+|---|---|---|---|---|---|---|---|---|---|
+|NULL|N_term_single2|N_term_single2|N_term_single|N_term_single|N_term_single|N_term_single|N_term_single|N_term_single|NULL|
+|W_IO|RegFile|DSP_top|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|CPU_IO|
+|W_IO|RegFile|DSP_bot|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|CPU_IO|
+|W_IO|RegFile|DSP_top|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|CPU_IO|
+|W_IO|RegFile|DSP_bot|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|CPU_IO|
+|W_IO|RegFile|DSP_top|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|CPU_IO|
+|W_IO|RegFile|DSP_bot|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|CPU_IO|
+|W_IO|RegFile|DSP_top|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|CPU_IO|
+|W_IO|RegFile|DSP_bot|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|LUT4AB|CPU_IO|
+|NULL|S_term_single2|S_term_single2|S_term_single|S_term_single|S_term_single|S_term_single|S_term_single|S_term_single|NULL|
+|**FabricEnd**|
+
+Let us take tile type LUT4AB as an example for the bitstream. This tile has the following BELs:
+
+| | | |
+|---|---|---|
+|BEL|LUT4c_frame_config.vhdl|LA_|
+|BEL|LUT4c_frame_config.vhdl|LB_|
+|BEL|LUT4c_frame_config.vhdl|LC_|
+|BEL|LUT4c_frame_config.vhdl|LD_|
+|BEL|LUT4c_frame_config.vhdl|LE_|
+|BEL|LUT4c_frame_config.vhdl|LF_|
+|BEL|LUT4c_frame_config.vhdl|LG_|
+|BEL|LUT4c_frame_config.vhdl|LH_|
+|BEL|MUX8LUT_frame_config.vhdl|
+|MATRIX|LUT4AB_switch_matrix.VHDL|
+|EndTILE|
+
+These are 8 LUT BELs (each of which use 18 configuration bits) and a MUX8LUT (which uses 2 configuration bits). The latter BEL is used to cascade multiple smaller LUTs to implement one or more larger LUTs, if needed. The LUT4AB tile also provides a switch matrix (which uses 392 configuration bits).
+
+The configuration bits for each LUT4c BEL are:
+
+    - [15…0]  LUT init value (the truth table)
+    - [16]      c_out_mux; ‘1’: use flip flop output, ‘0’: use combinatorial LUT output
+    - [17]      c_I0mux; ‘1’: use I0 as Carry in; ‘0’ normal mode (I0 driven by  input routing multiplexer)
+
+The 2 configuration bits of the MUX8LUT BEL describe if we cascade to implement 4 x LUT5, 2 x LUT6 or 1 x LUT7.
+
+The switch matrix is generated from the adjacency table ```LUT4AB_switch_matrix.csv```.
+
+In that file, each row describes one configurable switch matrix multiplexer. The exact encoding of switch matrix multiplexers is defined in function TODO where we generate the multiplexer and where we write a dictionary for the final bitstream assembly.
+The configuration bits of the individual switch matrix multiplexers are concatenated in the order they appear in the adjacency table, as can be seen in the generated RTL code:
+
+```
+-- switch matrix multiplexer  N1BEG0        MUX-4
+N1BEG0_input     <= J_l_CD_END1 & JW2END3 & J2MID_CDb_END3 & LC_O after 80 ps;
+N1BEG0  <= N1BEG0_input(TO_INTEGER(UNSIGNED(ConfigBits(1 downto 0))));
+
+-- switch matrix multiplexer  N1BEG1        MUX-4
+N1BEG1_input     <= J_l_EF_END2 & JW2END0 & J2MID_EFb_END0 & LD_O after 80 ps;
+N1BEG1  <= N1BEG1_input(TO_INTEGER(UNSIGNED(ConfigBits(3 downto 2))));
+
+…
+
+-- switch matrix multiplexer  J_l_GH_BEG3       MUX-4
+J_l_GH_BEG3_input    <= JW2END4 & W2END0 & E6END0 & N4END0 after 80 ps;
+J_l_GH_BEG3 <= J_l_GH_BEG3_input(TO_INTEGER(UNSIGNED(ConfigBits(391 downto 390))));
+```
+
+When generating the Multiplexers, FABulous is writing metadata that contains a dictionary that denotes for each possible switch matrix multiplexer setting the corresponding bits.
+
+A tile bitstream is formed by concatenating all configuration bits of all BELs in exactly the order as specified in the LUT4AB tile descriptor followed by the switch matrix configuration bits.
+Note that all BELs (including the LUTs, DSPs, etc.) and the switch matrix expose their configuration bits in the respective BEL interface and the configuration bits are stored centralized in a module <tile_type>_ConfigMem, which is provided in each tile.
+For a LUT4AB tile, the concatenated tile bitstream is:
+
+| | |
+|---|---|
+|[17…0]|LUT LA|
+|[35…18]|LUT LB|
+|[53…36]|LUT LC|
+|[71…54]|LUT LD|
+|[89…72]|LUT LE|
+|[107…90]|LUT LF|
+|[125…108]|LUT LG|
+|[143…126]|LUT LH|
+|[145…144]|MUX8LUT|
+|[537…146]|Switch matrix|
+
+The bold numbers are the base configuration bit offsets for the different BELs and the switch matrix. For instance, to configure the C-LUT (LC) as a 4-input AND gate using the flip-flop output and not using the carry chain, we have to set the tile configuration bits:
+
+| | |
+|---|---|
+|[53]|‘0’   # no carry chain|
+|[52]|‘1’   # use flip-flop output|
+|[51…36]|‘1000_0000_0000_0000’    # AND truth table|
+
+In order to translate a FASM switch matrix routing entry into the tile configuration, we look up the FASM entry in the corresponding tile type switch matrix routing dictionary (file TODO) and add the base bit offset (here 146) to the reported bits.
+For instance, to configure the switch matrix setting JW2END0  N1BEG1, we set tile configuration bits [149]=’1’ and [148]=’0’.
+
+## Shift register configuration mode
+
+In shift register configuration mode, the tile configuration bitstream is implemented as a single long shift register. At the moment we configure bitserial. To speed this up, multiple parallel chains (e.g., 32) maybe used. However, bitserial mode is expensive as it needs flip flops (rather than latches) and it is not well suited for partial reconfiguration.
+Therefore, we recommend shift register configuration only for tiny fabrics (less than 200 LUTs) as frame-based reconfiguration is in almost any case superior.
+
+## Frame-based configuration
+
+A typical CLB tile with 8 LUTs will have somewhere between 500 and 1500 configuration bits. This is mostly depending on the LUT size and switch matrix multiplexer encoding (e.g. binary encoded versus one-hot).
+These configuration bits have to be packed into i configuration frames with a tile frame data width of j bits. Ideally, i and j are about the same for minimal wire cost. In FABulous, we use j horizontal frame data bits per CLB row. This means that we use the same number of horizontal fame data bits for all tile types. The number of configuration frames (which correspond to an equal number of vertical select frame lines), will be adjusted for the actual total number of required tile configuration bits. For example, a DSP tile commonly needs fewer configuration bits as a LUT tile.
+
+As a pragmatic solution, we defined the frame data width j=32 bits in FABulous. This fits well most practical requirements and makes it easy to interface the configuration logic with standard buses.
+
+For the LUT2AB tile with 538 tile configuration bits, we have selected i=20 configuration frames. This results in i x j = 640 addressable configuration bits. In this example, we will leave 640 – 538 = 102 addressable configuration bits unused in each LUT4AB tile. Note that no latches will be generated for those unused configuration bits.
+
+By default, FABulous is tightly packing the used configuration bits (538 for the LUT4AB example) in their original order into 32-bit frames (starting with frame 0).
+However, a user can specify a tile configuration mapping file that looks as follows (see file LUT4AB_ConfigMem.csv for the full example):
+
+```
+#frame_name,frame_index,bits_used_in_frame,used_bits_mask,ConfigBits_ranges
+frame0,0,32,1111_1111_1111_1111_0001_0001_0001_0001,15:00,16,17,144,145
+frame1,1,32,1111_1111_1111_1111_0001_0001_0000_0000,33:18,34,35
+frame2,2,32,1111_1111_1111_1111_0001_0001_0011_0011,51:36,52,53,515:514,517:516,#,J_l_CD_BEG0,J_l_CD_BEG1
+frame3,3,32,1111_1111_1111_1111_0001_0001_0011_0011,69:54,70,71,519:518,521:520,#,J_l_CD_BEG2,J_l_CD_BEG3
+```
+
+The important information in each line (i.e. a tile configuration frame) is a bitmask that is for each frame denoting which addressable configuration bits will be used. For instance in frame0, we are using 20 configuration bits (out of the 32 possible configuration bits). The bitmask is specified MSB to LSB index [31…0].
+
+After the bit mask, we specify a list of tile configuration bits in exactly the same order as the bit mask. These tile configuration bits will be mapped to the frame configuration bits.
+
+For example, the 20 bits of frame0 are specified as:
+
+```frame0,0,32,1111_1111_1111_1111_0001_0001_0001_0001,15:00,16,17,144,145```
+
+This will map tile configuration bit [15] to bit 31 in frame0, 14 to bit 30 and so forth until tile configuration bit 145 is mapped to bit 0 in frame0. Therefore, the number of tile configuration bits has to match the number of ones in the frame mask. Ranges of tile configuration bits can be specified with the : operator. In the example, the tile configuration bits 15:0 are the init values of the A-LUT and they will be mapped to the 16 MSBs in frame0.
+
+Future versions of FABulous will use the bitstream mapping feature for optimizing the physical implementation. In our first test chip, we used this feature to create a more human readable bitstream. For instance, we use this to locate the A-LUT to H-LUT init values in the first 8 frames at the high word position. The configuration modes are shown by nibbles (which will show up as one digit in a hex editor). Similarly, most multiplexers are represented by a single hex digit.
+
+## Bitstream assembly and configuration frame addressing
+
+Configuration frames are composed by concatenating the same configuration frame index for an entire resource column. For instance, in our example, we are considering an FPGA fabric with 8 rows and 10 columns. This corresponds to resource columns with 8 CLBs, 8 RegFiles or 4 DSPs (DSPs take two vertically aligned tiles).
+Each configuration frame is masked by a frame_address_mask in 32 bits. ```frame_address_mask[31:27]``` performs as binary index to indicate the column index. ```frame_address_mask[19:0]``` performs as one-hot data code to index the frame address.
+
+In the following example, the first line is the frame_address_mask, ```frame_address_mask[31:27] = 00100``` presents the 8th column (X7), ```frame_address_mask[19:0] = 0000_0000_0000_0000_0010``` presents 2nd frame (frame1). The rest 8 lines binary bits will be masked to all LUT4ABs' frame1 at column X7.
+
+```
+20 00 00 02
+FF FE FF FE
+FF FE 00 00
+FF FF FF FF
+00 00 00 00
+FF FF FF FF
+00 00 00 00
+FF FE FF FE
+FF FE FF FE
+```

fabulous/fabric_cad/__init__.py

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+"""Computer-aided design (CAD) tools for FPGA fabric development.
+
+This package provides tools for fabric analysis, bitstream generation, and design flow
+automation for FABulous FPGA fabrics.
+"""

fabulous/fabric_cad/gen_bitstream_spec.py

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+"""Bitstream specification generation module.
+
+This module provides functionality to generate bitstream specifications from FPGA fabric
+definitions. The specification defines how configuration bits map to physical frame
+locations and is used during bitstream generation.
+"""
+
+import string
+from importlib.metadata import version
+from typing import TYPE_CHECKING
+
+from loguru import logger
+
+from fabulous.fabric_definition.fabric import Fabric
+from fabulous.fabric_generator.parser.parse_configmem import parseConfigMem
+from fabulous.fabric_generator.parser.parse_switchmatrix import parseList, parseMatrix
+from fabulous.fabulous_settings import get_context
+
+if TYPE_CHECKING:
+    from fabulous.fabric_definition.configmem import ConfigMem
+
+
+def generateBitstreamSpec(fabric: Fabric) -> dict[str, dict]:
+    """Generate the fabric's bitstream specification.
+
+    This is needed to tell where each FASM configuration is mapped to the physical
+    bitstream
+    The result file will be further parsed by `bit_gen.py`.
+
+    Parameters
+    ----------
+    fabric : Fabric
+        The fabric object for generating the bitstream specification
+
+    Returns
+    -------
+    dict[str, dict]
+        The bits stream specification of the fabric.
+    """
+    specData = {
+        "TileMap": {},
+        "TileSpecs": {},
+        "TileSpecs_No_Mask": {},
+        "FrameMap": {},
+        "FrameMapEncode": {},
+        "ArchSpecs": {
+            "MaxFramesPerCol": fabric.maxFramesPerCol,
+            "FrameBitsPerRow": fabric.frameBitsPerRow,
+            "FrameSelectWidth": fabric.frameSelectWidth,
+            "DesyncBit": fabric.desync_flag,
+            "SyncHeaderHex": fabric.syncHeaderHex,
+            "IncludeBorderRows": False,  # Currently not supported in FABulous
+            "FABulousVersion": version("FABulous-FPGA"),
+        },
+    }
+
+    tileMap = {}
+    for y, row in enumerate(fabric.tile):
+        for x, tile in enumerate(row):
+            if tile is not None:
+                tileMap[f"X{x}Y{y}"] = tile.name
+            else:
+                tileMap[f"X{x}Y{y}"] = "NULL"
+
+    specData["TileMap"] = tileMap
+    configMemList: list[ConfigMem] = []
+    for y, row in enumerate(fabric.tile):
+        for x, tile in enumerate(row):
+            if tile is None:
+                continue
+            if "fabric.csv" in str(tile.tileDir):
+                # backward compatibility for old project structure
+                # We need to take the matrixDir from the tile, since there
+                # is the actual path to the tile defined in the fabric.csv
+                if tile.matrixDir.is_file():
+                    configMemPath = tile.matrixDir.parent / f"{tile.name}_ConfigMem.csv"
+                elif tile.matrixDir.is_dir():
+                    configMemPath = tile.matrixDir / f"{tile.name}_ConfigMem.csv"
+                else:
+                    configMemPath = (
+                        get_context().proj_dir
+                        / "Tile"
+                        / tile.name
+                        / f"{tile.name}_ConfigMem.csv"
+                    )
+                    logger.warning(
+                        f"MatrixDir for {tile.name} is not a valid file or directory. "
+                        f"Assuming default path: {configMemPath}"
+                    )
+            else:
+                configMemPath = tile.tileDir.parent.joinpath(
+                    f"{tile.name}_ConfigMem.csv"
+                )
+            logger.info(f"ConfigMemPath: {configMemPath}")
+
+            if configMemPath.exists() and configMemPath.is_file():
+                configMemList = parseConfigMem(
+                    configMemPath,
+                    fabric.maxFramesPerCol,
+                    fabric.frameBitsPerRow,
+                    tile.globalConfigBits,
+                )
+            elif tile.globalConfigBits > 0:
+                logger.critical(
+                    f"No ConfigMem csv file found for {tile.name} which "
+                    "have config bits"
+                )
+                configMemList = []
+            else:
+                logger.info(f"No config memory for {tile.name}.")
+                configMemList = []
+
+            encodeDict = [-1] * (fabric.maxFramesPerCol * fabric.frameBitsPerRow)
+            maskDic = {}
+            for cfm in configMemList:
+                maskDic[cfm.frameIndex] = cfm.usedBitMask
+                # matching the value in the configBitRanges with the reversedBitMask
+                # bit 0 in bit mask is the first value in the configBitRanges
+                for i, char in enumerate(cfm.usedBitMask):
+                    if char == "1":
+                        encodeDict[cfm.configBitRanges.pop(0)] = (
+                            fabric.frameBitsPerRow - 1 - i
+                        ) + fabric.frameBitsPerRow * cfm.frameIndex
+
+            # filling the maskDic with the unused frames
+            for i in range(fabric.maxFramesPerCol - len(configMemList)):
+                maskDic[len(configMemList) + i] = "0" * fabric.frameBitsPerRow
+
+            specData["FrameMap"][tile.name] = maskDic
+            if tile.globalConfigBits == 0:
+                logger.info(f"No config memory for X{x}Y{y}_{tile.name}.")
+                specData["FrameMap"][tile.name] = {}
+                specData["FrameMapEncode"][tile.name] = {}
+
+            curBitOffset = 0
+            curTileMap = {}
+            curTileMapNoMask = {}
+
+            for i, bel in enumerate(tile.bels):
+                for featureKey, keyDict in bel.belFeatureMap.items():
+                    for entry in keyDict:
+                        if isinstance(entry, int):
+                            for v in keyDict[entry]:
+                                curTileMap[
+                                    f"{string.ascii_uppercase[i]}.{featureKey}"
+                                ] = {encodeDict[curBitOffset + v]: keyDict[entry][v]}
+                                curTileMapNoMask[
+                                    f"{string.ascii_uppercase[i]}.{featureKey}"
+                                ] = {encodeDict[curBitOffset + v]: keyDict[entry][v]}
+                            curBitOffset += len(keyDict[entry])
+
+            # All the generation will be working on the tile level with the tileDic
+            # This is added to propagate the updated switch matrix to each of the tile
+            # in the fabric
+            if tile.matrixDir.suffix == ".list":
+                tile.matrixDir = tile.matrixDir.with_suffix(".csv")
+
+            result = parseMatrix(tile.matrixDir, tile.name)
+            for source, sinkList in result.items():
+                controlWidth = 0
+                for i, sink in enumerate(reversed(sinkList)):
+                    controlWidth = (len(sinkList) - 1).bit_length()
+                    controlValue = f"{len(sinkList) - 1 - i:0{controlWidth}b}"
+                    pip = f"{sink}.{source}"
+                    if len(sinkList) < 2:
+                        curTileMap[pip] = {}
+                        curTileMapNoMask[pip] = {}
+                        continue
+
+                    for c, curChar in enumerate(controlValue[::-1]):
+                        if pip not in curTileMap:
+                            curTileMap[pip] = {}
+                            curTileMapNoMask[pip] = {}
+
+                        curTileMap[pip][encodeDict[curBitOffset + c]] = curChar
+                        curTileMapNoMask[pip][encodeDict[curBitOffset + c]] = curChar
+
+                curBitOffset += controlWidth
+
+            # And now we add empty config bit mappings for immutable connections
+            # (i.e. wires), as nextpnr sees these the same as normal pips
+            for wire in tile.wireList:
+                curTileMap[f"{wire.source}.{wire.destination}"] = {}
+                curTileMapNoMask[f"{wire.source}.{wire.destination}"] = {}
+
+            specData["TileSpecs"][f"X{x}Y{y}"] = curTileMap
+            specData["TileSpecs_No_Mask"][f"X{x}Y{y}"] = curTileMapNoMask
+
+    # Supertile bitstream features. A supertile's config bits physically live in
+    # its master tile's frame column (the master tile's own ConfigMem leaves those
+    # bits free). Within the supertile config space the bit order is
+    # [switch-matrix bits][BEL bits], matching genSuperTile()'s ST_ConfigBits
+    # slicing. The BEL and switch-matrix features are added to the master tile's
+    # TileSpecs entry alongside the master tile's own features.
+    st_bel_count: dict[tuple[int, int], int] = {}
+    for superTile in fabric.superTileDic.values():
+        if not superTile.bels and superTile.supertile_matrix_dir is None:
+            continue
+
+        st_config_bits = superTile.total_config_bits
+
+        st_encode_dict = [-1] * (fabric.maxFramesPerCol * fabric.frameBitsPerRow)
+        st_mask_dic: dict[int, str] = {}
+        if st_config_bits > 0:
+            st_config_mem_list = parseConfigMem(
+                superTile.tileDir.parent / f"{superTile.name}_ConfigMem.csv",
+                fabric.maxFramesPerCol,
+                fabric.frameBitsPerRow,
+                st_config_bits,
+            )
+            for cfm in st_config_mem_list:
+                st_mask_dic[cfm.frameIndex] = cfm.usedBitMask
+                for i, char in enumerate(cfm.usedBitMask):
+                    if char == "1":
+                        st_encode_dict[cfm.configBitRanges.pop(0)] = (
+                            fabric.frameBitsPerRow - 1 - i
+                        ) + fabric.frameBitsPerRow * cfm.frameIndex
+
+        sm_connections: dict[str, list[str]] = {}
+        if superTile.supertile_matrix_dir is not None:
+            mat_path = superTile.supertile_matrix_dir
+            if mat_path.suffix == ".list":
+                for dest, src in parseList(mat_path):
+                    sm_connections.setdefault(dest, []).append(src)
+            else:
+                sm_connections = parseMatrix(mat_path, superTile.name)
+
+        tx_local, ty_local = superTile.get_master_tile_coords()
+
+        for base_fx, base_fy, _ in fabric.iter_super_tile_placements(superTile):
+            ftx = base_fx + tx_local
+            fty = base_fy + ty_local
+            master_tile = fabric.tile[fty][ftx]
+
+            frame_map = specData["FrameMap"].setdefault(master_tile.name, {})
+            for frame_idx, mask in st_mask_dic.items():
+                existing = frame_map.get(frame_idx, "0" * fabric.frameBitsPerRow)
+                frame_map[frame_idx] = "".join(
+                    "1" if a == "1" or b == "1" else "0"
+                    for a, b in zip(existing, mask, strict=True)
+                )
+
+            curTileMap = specData["TileSpecs"].setdefault(f"X{ftx}Y{fty}", {})
+            curTileMapNoMask = specData["TileSpecs_No_Mask"].setdefault(
+                f"X{ftx}Y{fty}", {}
+            )
+
+            curBitOffset = 0
+            for source, sinkList in sm_connections.items():
+                controlWidth = (len(sinkList) - 1).bit_length()
+                if st_config_bits == 0:
+                    # No config bits — all connections are passthrough.
+                    for sink in sinkList:
+                        for t in (curTileMap, curTileMapNoMask):
+                            t[f"{sink}.{source}"] = {}
+                    continue
+                for i, sink in enumerate(reversed(sinkList)):
+                    pip = f"{sink}.{source}"
+                    if len(sinkList) < 2:
+                        for t in (curTileMap, curTileMapNoMask):
+                            t[pip] = {}
+                        continue
+                    controlValue = f"{len(sinkList) - 1 - i:0{controlWidth}b}"
+                    for c, curChar in enumerate(controlValue[::-1]):
+                        for t in (curTileMap, curTileMapNoMask):
+                            t.setdefault(pip, {})
+                            t[pip][st_encode_dict[curBitOffset + c]] = curChar
+                curBitOffset += controlWidth
+
+            bel_coord = (ftx, fty)
+            bel_offset = len(master_tile.bels) + st_bel_count.get(bel_coord, 0)
+            for i, bel in enumerate(superTile.bels):
+                letter = string.ascii_uppercase[bel_offset + i]
+                for featureKey, keyDict in bel.belFeatureMap.items():
+                    for entry in keyDict:
+                        if not isinstance(entry, int):
+                            continue
+                        for v in keyDict[entry]:
+                            for t in (curTileMap, curTileMapNoMask):
+                                t[f"{letter}.{featureKey}"] = {
+                                    st_encode_dict[curBitOffset + v]: keyDict[entry][v]
+                                }
+                        curBitOffset += len(keyDict[entry])
+            st_bel_count[bel_coord] = bel_offset + len(superTile.bels)
+
+    return specData