zexus 1.6.2

package/src/zexus/vm/bytecode_converter.py

@@ -0,0 +1,297 @@
+"""
+Stack-to-Register Bytecode Converter
+
+Converts stack-based bytecode to register-based bytecode for
+improved arithmetic performance (1.5-3x speedup).
+
+Strategy:
+1. Identify arithmetic patterns in stack code
+2. Allocate virtual registers for temporaries
+3. Convert stack operations to 3-address register code
+4. Keep complex operations on stack (hybrid mode)
+
+Example conversion:
+  Stack:    LOAD_CONST 10, LOAD_CONST 20, ADD, STORE_NAME "x"
+  Register: LOAD_REG r0, 10; LOAD_REG r1, 20; ADD_REG r2, r0, r1; STORE_REG r2, "x"
+"""
+
+from typing import List, Tuple, Dict, Any, Optional
+from .bytecode import Opcode, Bytecode
+from .register_vm import RegisterOpcode, RegisterAllocator
+
+
+class BytecodeConverter:
+    """
+    Converts stack-based bytecode to register-based bytecode.
+    
+    Optimizes arithmetic-heavy code by using registers instead of stack,
+    reducing memory access overhead.
+    """
+    
+    def __init__(self, num_registers: int = 16, aggressive: bool = False, debug: bool = False):
+        """
+        Initialize converter
+        
+        Args:
+            num_registers: Number of virtual registers available
+            aggressive: Aggressively convert all operations (not just arithmetic)
+            debug: Enable debug output
+        """
+        self.num_registers = num_registers
+        self.aggressive = aggressive
+        self.debug = debug
+        self.allocator = RegisterAllocator(num_registers)
+        
+        # Next available temporary register
+        self.next_temp_reg = 0
+        
+        # Conversion statistics
+        self.stats = {
+            'stack_instructions': 0,
+            'register_instructions': 0,
+            'conversions': 0,
+            'skipped': 0,
+        }
+    
+    def convert(self, bytecode: Bytecode) -> Bytecode:
+        """
+        Convert stack bytecode to register bytecode.
+        
+        Args:
+            bytecode: Stack-based bytecode
+            
+        Returns:
+            Hybrid bytecode (registers for arithmetic, stack for rest)
+        """
+        self.stats['stack_instructions'] = len(bytecode.instructions)
+        
+        # Reset state
+        self.allocator.clear()
+        self.next_temp_reg = 0
+        
+        converted_instructions = []
+        constants = bytecode.constants.copy()
+        
+        i = 0
+        while i < len(bytecode.instructions):
+            inst = bytecode.instructions[i]
+            opcode = inst[0] if isinstance(inst, tuple) else inst
+            
+            # Try to convert arithmetic patterns
+            pattern, advance = self._detect_arithmetic_pattern(bytecode.instructions, i)
+            
+            if pattern:
+                # Convert pattern to register ops
+                register_insts = self._convert_pattern(pattern, constants)
+                converted_instructions.extend(register_insts)
+                self.stats['conversions'] += 1
+                i += advance
+            else:
+                # Keep as stack instruction
+                converted_instructions.append(inst)
+                self.stats['skipped'] += 1
+                i += 1
+        
+        self.stats['register_instructions'] = len(converted_instructions)
+        
+        # Create new bytecode with converted instructions
+        result = Bytecode(converted_instructions, constants)
+        if bytecode.metadata:
+            result.metadata.update(bytecode.metadata)
+        result.set_metadata('converted_to_register', True)
+        result.set_metadata('conversion_stats', self.stats.copy())
+        
+        if self.debug:
+            print(f"Conversion: {self.stats['stack_instructions']} → {self.stats['register_instructions']} instructions")
+            print(f"  Converted: {self.stats['conversions']}, Skipped: {self.stats['skipped']}")
+        
+        return result
+    
+    def _detect_arithmetic_pattern(
+        self,
+        instructions: List[Tuple],
+        start: int
+    ) -> Tuple[Optional[Dict], int]:
+        """
+        Detect arithmetic patterns that can be converted to register ops.
+        
+        Patterns:
+        1. Binary arithmetic: LOAD_CONST a, LOAD_CONST b, ADD/SUB/MUL/DIV
+        2. Variable arithmetic: LOAD_NAME x, LOAD_CONST y, ADD
+        3. Chains: a + b * c → multiple register ops
+        
+        Returns:
+            (pattern_dict, num_instructions_consumed) or (None, 0)
+        """
+        if start >= len(instructions):
+            return None, 0
+        
+        # Pattern 1: Constant arithmetic (LOAD_CONST, LOAD_CONST, BINARY_OP)
+        if start + 2 < len(instructions):
+            inst1, inst2, inst3 = instructions[start:start+3]
+            
+            if (inst1[0] == Opcode.LOAD_CONST and
+                inst2[0] == Opcode.LOAD_CONST and
+                inst3[0] in [Opcode.ADD, Opcode.SUB, Opcode.MUL, Opcode.DIV, Opcode.MOD, Opcode.POW]):
+                
+                return {
+                    'type': 'const_binary_op',
+                    'const1': inst1[1],
+                    'const2': inst2[1],
+                    'operation': inst3[0],
+                }, 3
+        
+        # Pattern 2: Variable arithmetic (LOAD_NAME, LOAD_CONST, BINARY_OP)
+        if start + 2 < len(instructions):
+            inst1, inst2, inst3 = instructions[start:start+3]
+            
+            if (inst1[0] == Opcode.LOAD_NAME and
+                inst2[0] == Opcode.LOAD_CONST and
+                inst3[0] in [Opcode.ADD, Opcode.SUB, Opcode.MUL, Opcode.DIV]):
+                
+                return {
+                    'type': 'var_const_binary_op',
+                    'var_name': inst1[1],
+                    'const': inst2[1],
+                    'operation': inst3[0],
+                }, 3
+        
+        # Pattern 3: Two variables (LOAD_NAME x, LOAD_NAME y, BINARY_OP)
+        if start + 2 < len(instructions):
+            inst1, inst2, inst3 = instructions[start:start+3]
+            
+            if (inst1[0] == Opcode.LOAD_NAME and
+                inst2[0] == Opcode.LOAD_NAME and
+                inst3[0] in [Opcode.ADD, Opcode.SUB, Opcode.MUL, Opcode.DIV]):
+                
+                return {
+                    'type': 'var_var_binary_op',
+                    'var1': inst1[1],
+                    'var2': inst2[1],
+                    'operation': inst3[0],
+                }, 3
+        
+        # Pattern 4: Store result (... STORE_NAME)
+        # This is an extension pattern, not standalone
+        
+        return None, 0
+    
+    def _convert_pattern(self, pattern: Dict, constants: List[Any]) -> List[Tuple]:
+        """
+        Convert detected pattern to register instructions.
+        
+        Args:
+            pattern: Pattern dictionary from _detect_arithmetic_pattern
+            constants: Constants table
+            
+        Returns:
+            List of register-based instructions
+        """
+        instructions = []
+        
+        if pattern['type'] == 'const_binary_op':
+            # LOAD_CONST a, LOAD_CONST b, ADD
+            # → LOAD_REG r0, a; LOAD_REG r1, b; ADD_REG r2, r0, r1
+            const1_idx = pattern['const1']
+            const2_idx = pattern['const2']
+            operation = pattern['operation']
+            
+            # Allocate temporary registers
+            r0 = self._alloc_temp_reg()
+            r1 = self._alloc_temp_reg()
+            r2 = self._alloc_temp_reg()
+            
+            # Load constants to registers
+            instructions.append((RegisterOpcode.LOAD_REG, r0, const1_idx))
+            instructions.append((RegisterOpcode.LOAD_REG, r1, const2_idx))
+            
+            # Perform operation
+            reg_op = self._map_stack_op_to_register_op(operation)
+            instructions.append((reg_op, r2, r0, r1))
+            
+            # Push result back to stack (hybrid mode)
+            instructions.append((RegisterOpcode.PUSH_REG, r2))
+        
+        elif pattern['type'] == 'var_const_binary_op':
+            # LOAD_NAME x, LOAD_CONST y, ADD
+            # → LOAD_VAR_REG r0, "x"; LOAD_REG r1, y; ADD_REG r2, r0, r1; PUSH_REG r2
+            var_name = pattern['var_name']
+            const_idx = pattern['const']
+            operation = pattern['operation']
+            
+            r0 = self._alloc_temp_reg()
+            r1 = self._alloc_temp_reg()
+            r2 = self._alloc_temp_reg()
+            
+            instructions.append((RegisterOpcode.LOAD_VAR_REG, r0, var_name))
+            instructions.append((RegisterOpcode.LOAD_REG, r1, const_idx))
+            
+            reg_op = self._map_stack_op_to_register_op(operation)
+            instructions.append((reg_op, r2, r0, r1))
+            
+            instructions.append((RegisterOpcode.PUSH_REG, r2))
+        
+        elif pattern['type'] == 'var_var_binary_op':
+            # LOAD_NAME x, LOAD_NAME y, ADD
+            # → LOAD_VAR_REG r0, "x"; LOAD_VAR_REG r1, "y"; ADD_REG r2, r0, r1; PUSH_REG r2
+            var1 = pattern['var1']
+            var2 = pattern['var2']
+            operation = pattern['operation']
+            
+            r0 = self._alloc_temp_reg()
+            r1 = self._alloc_temp_reg()
+            r2 = self._alloc_temp_reg()
+            
+            instructions.append((RegisterOpcode.LOAD_VAR_REG, r0, var1))
+            instructions.append((RegisterOpcode.LOAD_VAR_REG, r1, var2))
+            
+            reg_op = self._map_stack_op_to_register_op(operation)
+            instructions.append((reg_op, r2, r0, r1))
+            
+            instructions.append((RegisterOpcode.PUSH_REG, r2))
+        
+        return instructions
+    
+    def _map_stack_op_to_register_op(self, stack_op: Opcode) -> RegisterOpcode:
+        """Map stack opcode to register opcode"""
+        mapping = {
+            Opcode.ADD: RegisterOpcode.ADD_REG,
+            Opcode.SUB: RegisterOpcode.SUB_REG,
+            Opcode.MUL: RegisterOpcode.MUL_REG,
+            Opcode.DIV: RegisterOpcode.DIV_REG,
+            Opcode.MOD: RegisterOpcode.MOD_REG,
+            Opcode.POW: RegisterOpcode.POW_REG,
+            Opcode.NEG: RegisterOpcode.NEG_REG,
+            Opcode.EQ: RegisterOpcode.EQ_REG,
+            Opcode.NEQ: RegisterOpcode.NEQ_REG,
+            Opcode.LT: RegisterOpcode.LT_REG,
+            Opcode.GT: RegisterOpcode.GT_REG,
+            Opcode.LTE: RegisterOpcode.LTE_REG,
+            Opcode.GTE: RegisterOpcode.GTE_REG,
+            Opcode.AND: RegisterOpcode.AND_REG,
+            Opcode.OR: RegisterOpcode.OR_REG,
+            Opcode.NOT: RegisterOpcode.NOT_REG,
+        }
+        return mapping.get(stack_op, stack_op)
+    
+    def _alloc_temp_reg(self) -> int:
+        """Allocate next temporary register"""
+        reg = self.next_temp_reg
+        self.next_temp_reg = (self.next_temp_reg + 1) % self.num_registers
+        return reg
+    
+    def get_stats(self) -> Dict[str, Any]:
+        """Get conversion statistics"""
+        if self.stats['stack_instructions'] > 0:
+            reduction = ((self.stats['stack_instructions'] - self.stats['register_instructions']) /
+                        self.stats['stack_instructions']) * 100
+        else:
+            reduction = 0
+        
+        return {
+            **self.stats,
+            'reduction_pct': reduction,
+        }
+    
+    def __repr__(self) -> str:
+        return f"<BytecodeConverter regs={self.num_registers} conversions={self.stats['conversions']}>"