yosys2digitaljs 0.6.0 → 0.8.0

package/.github/workflows/nodejs.yml

@@ -1,6 +1,6 @@
 name: Node.js CI
 
-on: [push]
+on: [push, pull_request]
 
 jobs:
   build:
@@ -9,7 +9,7 @@ jobs:
 
     strategy:
       matrix:
-        node-version: [8.x, 10.x, 12.x]
+        node-version: [18.x]
 
     steps:
     - uses: actions/checkout@v2

package/ChangeLog.md

@@ -1,6 +1,13 @@
 # Changelog
 All notable changes to this project will be documented in this file.
 
+## [0.7.0] -- 2023-03-2023
+
+### Added
+
+- Support for `$lut` cells
+- Support for generating 7-segment display outputs
+
 ## [0.6.0] -- 2022-02-02
 
 ### Added

package/README.md

@@ -1,10 +1,10 @@
 # yosys2digitaljs
-This program converts JSON netlist output generated by [Yosys](http://www.clifford.at/yosys/)
-circuit synthesis software for use with the
+This program converts JSON netlist output generated by [Yosys](https://yosyshq.net/yosys/) 
+circuit synthesis software (Github repo [here](https://github.com/YosysHQ/yosys/)) for use with the
 [DigitalJS](http://github.com/tilk/digitaljs) graphical circuit simulator.
 
 # Usage
-You need to have [Yosys](http://www.clifford.at/yosys/) installed to run
+You need to have [Yosys](https://yosyshq.net/yosys/) installed to run
 yosys2digitaljs. For example, in Debian/Ubuntu, run:
 ```bash
 apt install yosys

package/dist/index.d.ts

@@ -54,8 +54,9 @@ declare namespace Digitaljs {
     };
 }
 declare namespace Yosys {
-    type BitChar = '0' | '1' | 'x';
-    type Bit = number | '0' | '1' | 'x';
+    const ConstChars: readonly ["0", "1", "x", "z"];
+    type BitChar = (typeof ConstChars)[number];
+    type Bit = number | BitChar;
     type BitVector = Bit[];
     type Port = {
         direction: 'input' | 'output' | 'inout';

package/dist/index.js

@@ -62,6 +62,7 @@ const gate_subst = new Map([
     ['$pmux', 'Mux1Hot'],
     ['$mem', 'Memory'],
     ['$mem_v2', 'Memory'],
+    ['$lut', 'Memory'],
     ['$fsm', 'FSM'],
     ['$clock', 'Clock'],
     ['$button', 'Button'],
@@ -114,6 +115,10 @@ const gate_negations = new Map([
     ['XnorReduce', 'XorReduce']
 ]);
 ;
+var Yosys;
+(function (Yosys) {
+    Yosys.ConstChars = ["0", "1", "x", "z"];
+})(Yosys || (Yosys = {}));
 ;
 function chunkArray(a, chunk_size) {
     let results = [];
@@ -214,7 +219,7 @@ function yosys_to_digitaljs(data, portmaps, options = {}) {
 }
 function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
     function constbit(bit) {
-        return bit == '0' || bit == '1' || bit == 'x';
+        return Yosys.ConstChars.includes(bit.toString());
     }
     const nets = new HashMap();
     const netnames = new HashMap();
@@ -245,8 +250,6 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
         const net = get_net(k);
         if (net.source !== undefined) {
             // multiple sources driving one net, disallowed in digitaljs
-            console.log(k);
-            console.log(net);
             throw Error('Multiple sources driving net: ' + net.name);
         }
         net.source = { id: d, port: p };
@@ -865,6 +868,23 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 }
                 break;
             }
+            case '$lut':
+                assert(cell.connections.A.length == decode_json_number(cell.parameters.WIDTH));
+                assert(cell.connections.Y.length == 1);
+                assert(cell.port_directions.A == 'input');
+                assert(cell.port_directions.Y == 'output');
+                dev.abits = cell.connections.A.length;
+                dev.bits = cell.connections.Y.length;
+                dev.rdports = [{}];
+                dev.wrports = [];
+                dev.memdata = cell.parameters.LUT.split('').reverse();
+                assert(dev.memdata.length == Math.pow(2, dev.abits));
+                // Rewrite cell connections to be $mem compatible for port mapping
+                cell.connections.RD_ADDR = cell.connections.A;
+                cell.connections.RD_DATA = cell.connections.Y;
+                delete cell.connections.A;
+                delete cell.connections.Y;
+                break;
             default:
         }
         if (dev.type == 'Dff') {
@@ -887,6 +907,8 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
             connect_mem(dname, cell, dev);
         else if (cell.type == '$mem_v2')
             connect_mem(dname, cell, dev);
+        else if (cell.type == '$lut')
+            connect_mem(dname, cell, dev);
         else
             throw Error('Invalid cell type: ' + cell.type);
     }
@@ -997,14 +1019,37 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
     }
     return mout;
 }
-function escape_filename(cmd) {
-    return '"' + cmd.replace(/(["\s'$`\\])/g, '\\$1') + '"';
+function ansi_c_escape_contents(cmd) {
+    function func(ch) {
+        if (ch == '\t')
+            return '\\t';
+        if (ch == '\r')
+            return '\\r';
+        if (ch == '\n')
+            return '\\n';
+        return '\\x' + ch.charCodeAt(0).toString(16).padStart(2, '0');
+    }
+    return cmd.replace(/(["'\\])/g, '\\$1')
+        .replace(/[\x00-\x1F\x7F-\x9F]/g, func);
+}
+function ansi_c_escape(cmd) {
+    return '"' + ansi_c_escape_contents(cmd) + '"';
+}
+function shell_escape_contents(cmd) {
+    return cmd.replace(/(["\r\n$`\\])/g, '\\$1');
+}
+function shell_escape(cmd) {
+    return '"' + shell_escape_contents(cmd) + '"';
+}
+function process_filename(filename) {
+    const flags = /\.sv$/.test(filename) ? " -sv" : "";
+    return "read_verilog" + flags + " " + ansi_c_escape(filename);
 }
 const verilator_re = /^%(Warning|Error)[^:]*: ([^:]*):([0-9]+):([0-9]+): (.*)$/;
 async function verilator_lint(filenames, dirname, options = {}) {
     try {
         const output = [];
-        const verilator_result = await (0, util_1.promisify)(child_process.exec)('verilator -lint-only -Wall -Wno-DECLFILENAME -Wno-UNOPT -Wno-UNOPTFLAT ' + filenames.map(escape_filename).join(' '), { maxBuffer: 1000000, cwd: dirname || null, timeout: options.timeout || 60000 })
+        const verilator_result = await (0, util_1.promisify)(child_process.exec)('timeout -k10s 40s verilator -lint-only -Wall -Wno-DECLFILENAME -Wno-UNOPT -Wno-UNOPTFLAT ' + filenames.map(shell_escape).join(' '), { maxBuffer: 1000000, cwd: dirname || null, timeout: options.timeout || 60000 })
             .catch(exc => exc);
         for (const line of verilator_result.stderr.split('\n')) {
             const result = line.match(verilator_re);
@@ -1046,8 +1091,9 @@ async function process(filenames, dirname, options = {}) {
             : "";
     const tmpjson = await tmp.tmpName({ postfix: '.json' });
     let obj = undefined;
-    const yosys_result = await (0, util_1.promisify)(child_process.exec)('yosys -p "hierarchy -auto-top; proc' + optimize_simp + fsmpass + '; memory -nomap; wreduce -memx' +
-        optimize + '" -o "' + tmpjson + '" ' + filenames.map(escape_filename).join(' '), { maxBuffer: 1000000, cwd: dirname || null, timeout: options.timeout || 60000 })
+    const yosys_result = await (0, util_1.promisify)(child_process.exec)('timeout -k10s 40s yosys -p "' + shell_escape_contents(filenames.map(process_filename).join('; ')) +
+        '; hierarchy -auto-top; proc' + optimize_simp + fsmpass + '; memory -nomap; wreduce -memx' +
+        optimize + '" -o "' + tmpjson + '"', { maxBuffer: 1000000, cwd: dirname || null, timeout: options.timeout || 60000 })
         .catch(exc => exc);
     try {
         if (yosys_result instanceof Error) {
@@ -1093,8 +1139,14 @@ function io_ui(output) {
         }
         if (dev.type == 'Input')
             dev.type = dev.bits == 1 ? 'Button' : 'NumEntry';
-        if (dev.type == 'Output')
-            dev.type = dev.bits == 1 ? 'Lamp' : 'NumDisplay';
+        if (dev.type == 'Output') {
+            if (dev.bits == 1)
+                dev.type = 'Lamp';
+            else if (dev.bits == 8 && (dev.label == 'display7' || dev.label.startsWith('display7_')))
+                dev.type = 'Display7';
+            else
+                dev.type = 'NumDisplay';
+        }
     }
 }
 exports.io_ui = io_ui;

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "yosys2digitaljs",
-  "version": "0.6.0",
+  "version": "0.8.0",
   "description": "Export Yosys netlists to a logic simulator",
   "main": "dist/index",
   "types": "dist/index.d.ts",
@@ -13,7 +13,7 @@
   "author": "Marek Materzok",
   "license": "BSD-2-Clause",
   "dependencies": {
-    "3vl": "^0.3.5",
+    "3vl": "^1.0.1",
     "big-integer": "^1.6.49",
     "hashmap": "^2.4.0",
     "minimist": "^1.2.5",

package/src/index.ts

@@ -61,6 +61,7 @@ const gate_subst = new Map([
     ['$pmux', 'Mux1Hot'],
     ['$mem', 'Memory'],
     ['$mem_v2', 'Memory'],
+    ['$lut', 'Memory'],
     ['$fsm', 'FSM'],
     ['$clock', 'Clock'],
     ['$button', 'Button'],
@@ -174,9 +175,11 @@ namespace Digitaljs {
 
 namespace Yosys {
 
-    export type BitChar = '0' | '1' | 'x';
+    export const ConstChars = ["0", "1", "x", "z"] as const;
 
-    export type Bit = number | '0' | '1' | 'x';
+    export type BitChar = (typeof ConstChars)[number];
+
+    export type Bit = number | BitChar;
 
     export type BitVector = Bit[];
 
@@ -403,7 +406,7 @@ function yosys_to_digitaljs(data: Yosys.Output, portmaps: Portmaps, options: Con
 
 function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portmaps, options: ConvertOptions = {}): Digitaljs.Module {
     function constbit(bit: Bit) {
-        return bit == '0' || bit == '1' || bit == 'x';
+        return (Yosys.ConstChars as readonly string[]).includes(bit.toString());
     }
     const nets = new HashMap<Net, NetInfo>();
     const netnames = new HashMap<Net, string[]>();
@@ -433,8 +436,6 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
         const net = get_net(k);
         if(net.source !== undefined) {
             // multiple sources driving one net, disallowed in digitaljs
-            console.log(k);
-            console.log(net);
             throw Error('Multiple sources driving net: ' + net.name);
         }
         net.source = { id: d, port: p };
@@ -1030,6 +1031,24 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 }
                 break;
             }
+            case '$lut':
+                assert(cell.connections.A.length == decode_json_number(cell.parameters.WIDTH));
+                assert(cell.connections.Y.length == 1);
+                assert(cell.port_directions.A == 'input');
+                assert(cell.port_directions.Y == 'output');
+                dev.abits = cell.connections.A.length;
+                dev.bits = cell.connections.Y.length;
+                dev.rdports = [{}];
+                dev.wrports = [];
+                dev.memdata = cell.parameters.LUT.split('').reverse();
+                assert(dev.memdata.length == Math.pow(2, dev.abits));
+
+                // Rewrite cell connections to be $mem compatible for port mapping
+                cell.connections.RD_ADDR = cell.connections.A;
+                cell.connections.RD_DATA = cell.connections.Y;
+                delete cell.connections.A;
+                delete cell.connections.Y;
+                break;
             default:
         }
         if (dev.type == 'Dff') {
@@ -1048,6 +1067,7 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
         else if (cell.type == '$pmux') connect_pmux(dname, cell);
         else if (cell.type == '$mem') connect_mem(dname, cell, dev);
         else if (cell.type == '$mem_v2') connect_mem(dname, cell, dev);
+        else if (cell.type == '$lut') connect_mem(dname, cell, dev);
         else throw Error('Invalid cell type: ' + cell.type);
     }
     // Group bits into nets for complex sources
@@ -1150,17 +1170,41 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
     return mout;
 }
 
-function escape_filename(cmd: string): string {
-    return '"' + cmd.replace(/(["\s'$`\\])/g,'\\$1') + '"';
+function ansi_c_escape_contents(cmd: string): string {
+    function func(ch: string) {
+        if (ch == '\t') return '\\t';
+        if (ch == '\r') return '\\r';
+        if (ch == '\n') return '\\n';
+        return '\\x' + ch.charCodeAt(0).toString(16).padStart(2, '0');
+    }
+    return cmd.replace(/(["'\\])/g,'\\$1')
+              .replace(/[\x00-\x1F\x7F-\x9F]/g, func);
+}
+
+function ansi_c_escape(cmd: string): string {
+    return '"' + ansi_c_escape_contents(cmd) + '"';
+}
+
+function shell_escape_contents(cmd: string): string {
+    return cmd.replace(/(["\r\n$`\\])/g,'\\$1');
+}
+
+function shell_escape(cmd: string): string {
+    return '"' + shell_escape_contents(cmd) + '"';
 }
-        
+
+function process_filename(filename: string): string {
+    const flags = /\.sv$/.test(filename) ? " -sv" : "";
+    return "read_verilog" + flags + " " + ansi_c_escape(filename);
+}
+
 const verilator_re = /^%(Warning|Error)[^:]*: ([^:]*):([0-9]+):([0-9]+): (.*)$/;
 
 export async function verilator_lint(filenames: string[], dirname?: string, options: Options = {}): Promise<LintMessage[]> {
     try {
         const output: LintMessage[] = [];
         const verilator_result: {stdout: string, stderr: string} = await promisify(child_process.exec)(
-            'verilator -lint-only -Wall -Wno-DECLFILENAME -Wno-UNOPT -Wno-UNOPTFLAT ' + filenames.map(escape_filename).join(' '),
+            'timeout -k10s 40s verilator -lint-only -Wall -Wno-DECLFILENAME -Wno-UNOPT -Wno-UNOPTFLAT ' + filenames.map(shell_escape).join(' '),
             {maxBuffer: 1000000, cwd: dirname || null, timeout: options.timeout || 60000})
             .catch(exc => exc);
         for (const line of verilator_result.stderr.split('\n')) {
@@ -1202,8 +1246,9 @@ export async function process(filenames: string[], dirname?: string, options: Op
     const tmpjson = await tmp.tmpName({ postfix: '.json' });
     let obj = undefined;
     const yosys_result: {stdout: string, stderr: string, killed?: boolean, code?: number} = await promisify(child_process.exec)(
-        'yosys -p "hierarchy -auto-top; proc' + optimize_simp + fsmpass + '; memory -nomap; wreduce -memx' + 
-        optimize + '" -o "' + tmpjson + '" ' + filenames.map(escape_filename).join(' '),
+        'timeout -k10s 40s yosys -p "' + shell_escape_contents(filenames.map(process_filename).join('; ')) +
+        '; hierarchy -auto-top; proc' + optimize_simp + fsmpass + '; memory -nomap; wreduce -memx' +
+        optimize + '" -o "' + tmpjson + '"',
         {maxBuffer: 1000000, cwd: dirname || null, timeout: options.timeout || 60000})
         .catch(exc => exc);
     try {
@@ -1248,8 +1293,14 @@ export function io_ui(output: Digitaljs.Module) {
         }
         if (dev.type == 'Input')
             dev.type = dev.bits == 1 ? 'Button' : 'NumEntry';
-        if (dev.type == 'Output')
-            dev.type = dev.bits == 1 ? 'Lamp' : 'NumDisplay';
+        if (dev.type == 'Output') {
+            if (dev.bits == 1)
+                dev.type = 'Lamp';
+            else if (dev.bits == 8 && (dev.label == 'display7' || dev.label.startsWith('display7_')))
+                dev.type = 'Display7';
+            else
+                dev.type = 'NumDisplay';
+        }
     }
 }
 

package/test.sv

@@ -0,0 +1,31 @@
+
+// Full adder
+module fulladder(
+  input a,
+  input b,
+  input d,
+  output o,
+  output c
+);
+
+  logic t, c1, c2;
+
+  halfadder ha1(a, b, t, c1);
+  halfadder ha2(t, d, o, c2);
+
+  assign c = c1 | c2;
+
+endmodule
+// Half adder
+module halfadder(
+  input a, 
+  input b,
+  output o,
+  output c
+);
+
+  assign o = a ^ b;
+  assign c = a & b;
+
+endmodule
+

package/test1.sv

@@ -0,0 +1,19 @@
+
+module m(
+  input a,
+  output b
+);
+
+  n x(a, b);
+
+endmodule
+
+module n(
+  input a,
+  output b
+);
+
+  assign b = !a;
+
+endmodule
+

package/test1.v

@@ -0,0 +1,19 @@
+
+module m(
+  input a,
+  output b
+);
+
+  n x(a, b);
+
+endmodule
+
+module n(
+  input a,
+  output b
+);
+
+  assign b = !a;
+
+endmodule
+

package/test2.v

@@ -0,0 +1,19 @@
+
+module n(
+  input a,
+  output b
+);
+
+  assign b = !a;
+
+endmodule
+
+module m(
+  input a,
+  output b
+);
+
+  n x(a, b);
+
+endmodule
+

package/test3.sv

@@ -0,0 +1,63 @@
+// Half adder
+module halfadder(
+  input a, 
+  input b,
+  output o,
+  output c
+);
+
+  assign o = a ^ b;
+  assign c = a & b;
+
+endmodule
+
+// Full adder
+module fulladder(
+  input a,
+  input b,
+  input d,
+  output o,
+  output c
+);
+
+  logic t, c1, c2;
+
+  halfadder ha1(a, b, t, c1);
+  halfadder ha2(t, d, o, c2);
+
+  assign c = c1 | c2;
+
+endmodule
+
+// Multibit serial adder
+module serialadder
+#(parameter WIDTH = 4)(
+   input [WIDTH-1:0] a,
+   input [WIDTH-1:0] b,
+   output [WIDTH:0]  o
+);
+   
+  logic [WIDTH:0]   c;
+  logic [WIDTH-1:0]   s;
+   
+  assign c[0] = 1'b0;    
+   
+  genvar       ii;
+  generate 
+    for (ii=0; ii<WIDTH; ii=ii+1) 
+      begin
+        fulladder fa(a[ii],b[ii],c[ii],s[ii],c[ii+1]);
+      end
+  endgenerate
+   
+  assign o = {c[WIDTH], s};
+ 
+endmodule
+
+module zzz(
+  input [3:0] a,
+  input [3:0] b,
+  output [4:0]  o
+);
+  serialadder z(a,b,o);
+endmodule

package/test3.v

@@ -0,0 +1,19 @@
+
+module m(
+  input a,
+  output b
+);
+
+  assign b = !a;
+
+endmodule
+
+module n(
+  input a,
+  output b
+);
+
+  m x(a, b);
+
+endmodule
+

package/test4.sv

@@ -0,0 +1,62 @@
+// Half adder
+module halfadder(
+  input a, 
+  input b,
+  output o,
+  output c
+);
+
+  assign o = a ^ b;
+  assign c = a & b;
+
+endmodule
+
+// Full adder
+module fulladder(
+  input a,
+  input b,
+  input d,
+  output o,
+  output c
+);
+
+  logic t, c1, c2;
+
+  halfadder ha1(a, b, t, c1);
+  halfadder ha2(t, d, o, c2);
+
+  assign c = c1 | c2;
+
+endmodule
+
+// Multibit serial adder
+module serialadder(
+   input [4-1:0] a,
+   input [4-1:0] b,
+   output [4:0]  o
+);
+   
+  logic [4:0]   c;
+  logic [4-1:0]   s;
+   
+  assign c[0] = 1'b0;    
+   
+  genvar       ii;
+  generate 
+    for (ii=0; ii<4; ii=ii+1) 
+      begin
+        fulladder fa(a[ii],b[ii],c[ii],s[ii],c[ii+1]);
+      end
+  endgenerate
+   
+  assign o = {c[4], s};
+ 
+endmodule
+
+module zzz(
+  input [3:0] a,
+  input [3:0] b,
+  output [4:0]  o
+);
+  serialadder z(a,b,o);
+endmodule

package/tests/ram.sv

@@ -1,5 +1,5 @@
 // Simple RAM
-module rom
+module ram
 #(parameter AWIDTH = 4, DWIDTH = 4)(
   input clk,
   input [AWIDTH-1:0] addr,

package/tests/z.sv

@@ -0,0 +1,7 @@
+// high impedance state
+module sourceZ(
+  output out
+);
+  assign out = 1'bZ;
+
+endmodule

package/yosyss

@@ -0,0 +1,4 @@
+#!/bin/bash
+
+kill -9 $$
+