yosys2digitaljs 0.5.0 → 0.7.0

package/.github/workflows/nodejs.yml

@@ -1,6 +1,6 @@
 name: Node.js CI
 
-on: [push]
+on: [push, pull_request]
 
 jobs:
   build:
@@ -9,7 +9,7 @@ jobs:
 
     strategy:
       matrix:
-        node-version: [8.x, 10.x, 12.x]
+        node-version: [12.x, 14.x, 16.x]
 
     steps:
     - uses: actions/checkout@v2

package/ChangeLog.md

@@ -1,6 +1,20 @@
 # Changelog
 All notable changes to this project will be documented in this file.
 
+## [0.7.0] -- 2023-03-2023
+
+### Added
+
+- Support for `$lut` cells
+- Support for generating 7-segment display outputs
+
+## [0.6.0] -- 2022-02-02
+
+### Added
+
+- Support for Yosys 0.11 cells `$aldff`, `$aldffe`
+- Added a function `yosys2digitaljs` for converting a Yosys JSON output obtained elsewhere, without running Yosys locally
+
 ## [0.5.0] -- 2021-10-06
 
 ### Added

package/README.md

@@ -1,11 +1,10 @@
-[![Build Status](https://travis-ci.org/tilk/yosys2digitaljs.svg?branch=master)](https://travis-ci.org/tilk/yosys2digitaljs)
 # yosys2digitaljs
-This program converts JSON netlist output generated by [Yosys](http://www.clifford.at/yosys/)
-circuit synthesis software for use with the
+This program converts JSON netlist output generated by [Yosys](https://yosyshq.net/yosys/) 
+circuit synthesis software (Github repo [here](https://github.com/YosysHQ/yosys/)) for use with the
 [DigitalJS](http://github.com/tilk/digitaljs) graphical circuit simulator.
 
 # Usage
-You need to have [Yosys](http://www.clifford.at/yosys/) installed to run
+You need to have [Yosys](https://yosyshq.net/yosys/) installed to run
 yosys2digitaljs. For example, in Debian/Ubuntu, run:
 ```bash
 apt install yosys
@@ -25,9 +24,10 @@ The generated JSON is printed on standard output.
 # API
 Yosys2digitaljs can be used as a library. The API is promise (or async/await) based. Available functions are:
 
- - `process_sv(sv_text)` - converts a single SystemVerilog source passed as a string.
- - `process_files(texts)` - converts multiple Verilog/SystemVerilog sources. The `texts` parameter is an object, with keys being file names, and corresponding values containing the file contents as strings. Example: `{ 'test.sv': 'module test; ...' }`.
- - `process(filenames, dirname)` - converts Verilog/SystemVerilog sources saved on the filesystem under names `filenames` in the directory `dirname`.
+ - `yosys2digitaljs(json, options)` - converts the Yosys JSON output `json` (passed as an JS object) to a DigitalJS representation of the same circuit.
+ - `process_sv(sv_text, options)` - converts a single SystemVerilog source passed as a string.
+ - `process_files(texts, options)` - converts multiple Verilog/SystemVerilog sources. The `texts` parameter is an object, with keys being file names, and corresponding values containing the file contents as strings. Example: `{ 'test.sv': 'module test; ...' }`.
+ - `process(filenames, dirname, options)` - converts Verilog/SystemVerilog sources saved on the filesystem under names `filenames` in the directory `dirname`.
 
 The functions return a promise, which fulfills with an object value with following keys:
 

package/dist/index.d.ts

@@ -53,8 +53,86 @@ declare namespace Digitaljs {
         };
     };
 }
-declare type Options = {
+declare namespace Yosys {
+    type BitChar = '0' | '1' | 'x';
+    type Bit = number | '0' | '1' | 'x';
+    type BitVector = Bit[];
+    type Port = {
+        direction: 'input' | 'output' | 'inout';
+        bits: any;
+    };
+    type Parameters = {
+        WIDTH?: JsonConstant;
+        A_WIDTH?: JsonConstant;
+        B_WIDTH?: JsonConstant;
+        S_WIDTH?: JsonConstant;
+        Y_WIDTH?: JsonConstant;
+        A_SIGNED?: JsonConstant;
+        B_SIGNED?: JsonConstant;
+        CLK_POLARITY?: JsonConstant;
+        EN_POLARITY?: JsonConstant;
+        ARST_POLARITY?: JsonConstant;
+        ARST_VALUE: JsonConstant;
+        CTRL_IN_WIDTH?: JsonConstant;
+        CTRL_OUT_WIDTH?: JsonConstant;
+        TRANS_NUM?: JsonConstant;
+        STATE_NUM?: JsonConstant;
+        STATE_NUM_LOG2?: JsonConstant;
+        STATE_RST?: JsonConstant;
+        RD_PORTS?: JsonConstant;
+        WR_PORTS?: JsonConstant;
+        RD_CLK_POLARITY?: JsonConstant;
+        RD_CLK_ENABLE?: JsonConstant;
+        RD_CLK_TRANSPARENT?: JsonConstant;
+        WR_CLK_POLARITY?: JsonConstant;
+        WR_CLK_ENABLE?: JsonConstant;
+        [key: string]: any;
+    };
+    type JsonConstant = number | string;
+    type Attributes = {
+        init: JsonConstant;
+        [key: string]: any;
+    };
+    type Cell = {
+        hide_name: 0 | 1;
+        type: string;
+        parameters: Parameters;
+        attributes: Attributes;
+        port_directions: {
+            [key: string]: 'input' | 'output';
+        };
+        connections: {
+            [key: string]: BitVector;
+        };
+    };
+    type Net = {
+        hide_name: 0 | 1;
+        bits: BitVector;
+        attributes: {
+            [key: string]: string;
+        };
+    };
+    type Module = {
+        ports: {
+            [key: string]: Port;
+        };
+        cells: {
+            [key: string]: Cell;
+        };
+        netnames: {
+            [key: string]: Net;
+        };
+    };
+    type Output = {
+        modules: {
+            [key: string]: Module;
+        };
+    };
+}
+declare type ConvertOptions = {
     propagation?: number;
+};
+declare type Options = ConvertOptions & {
     optimize?: boolean;
     fsmexpand?: boolean;
     fsm?: boolean | "nomap";
@@ -76,10 +154,11 @@ declare type LintMessage = {
     message: string;
 };
 export declare function verilator_lint(filenames: string[], dirname?: string, options?: Options): Promise<LintMessage[]>;
+export declare function yosys2digitaljs(obj: Yosys.Output, options?: ConvertOptions): Digitaljs.TopModule;
 export declare function process(filenames: string[], dirname?: string, options?: Options): Promise<Output>;
 export declare function io_ui(output: Digitaljs.Module): void;
 export declare function process_files(data: {
     [key: string]: string;
-}, options: Options): Promise<Output>;
-export declare function process_sv(text: string): Promise<Output>;
+}, options?: Options): Promise<Output>;
+export declare function process_sv(text: string, options?: Options): Promise<Output>;
 export {};

package/dist/index.js

@@ -1,7 +1,7 @@
 #!/usr/bin/env node
 "use strict";
 Object.defineProperty(exports, "__esModule", { value: true });
-exports.process_sv = exports.process_files = exports.io_ui = exports.process = exports.verilator_lint = void 0;
+exports.process_sv = exports.process_files = exports.io_ui = exports.process = exports.yosys2digitaljs = exports.verilator_lint = void 0;
 const tmp = require("tmp-promise");
 const child_process = require("child_process");
 const assert = require("assert");
@@ -62,6 +62,7 @@ const gate_subst = new Map([
     ['$pmux', 'Mux1Hot'],
     ['$mem', 'Memory'],
     ['$mem_v2', 'Memory'],
+    ['$lut', 'Memory'],
     ['$fsm', 'FSM'],
     ['$clock', 'Clock'],
     ['$button', 'Button'],
@@ -95,7 +96,9 @@ const gate_subst = new Map([
     ['$adlatch', 'Dff'],
     ['$sr', 'Dff'],
     ['$dffsr', 'Dff'],
-    ['$dffsre', 'Dff']
+    ['$dffsre', 'Dff'],
+    ['$aldff', 'Dff'],
+    ['$aldffe', 'Dff']
 ]);
 const gate_negations = new Map([
     ['And', 'Nand'],
@@ -149,6 +152,8 @@ function order_ports(data) {
         '$adlatch': { EN: 'en', ARST: 'arst', D: 'in', Q: 'out' },
         '$dffsr': { CLK: 'clk', SET: 'set', CLR: 'clr', D: 'in', Q: 'out' },
         '$dffsre': { CLK: 'clk', EN: 'en', SET: 'set', CLR: 'clr', D: 'in', Q: 'out' },
+        '$aldff': { CLK: 'clk', ALOAD: 'aload', AD: 'ain', D: 'in', Q: 'out' },
+        '$aldffe': { CLK: 'clk', EN: 'en', ALOAD: 'aload', AD: 'ain', D: 'in', Q: 'out' },
         '$sr': { SET: 'set', CLR: 'clr', Q: 'out' },
         '$fsm': { ARST: 'arst', CLK: 'clk', CTRL_IN: 'in', CTRL_OUT: 'out' }
     };
@@ -436,7 +441,7 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
             assert(cell.port_directions.B == 'input');
             assert(cell.port_directions.Y == 'output');
         }
-        if (['$dff', '$dffe', '$adff', '$adffe', '$sdff', '$sdffe', '$sdffce', '$dlatch', '$adlatch', '$dffsr', '$dffsre'].includes(cell.type)) {
+        if (['$dff', '$dffe', '$adff', '$adffe', '$sdff', '$sdffe', '$sdffce', '$dlatch', '$adlatch', '$dffsr', '$dffsre', '$aldff', '$aldffe'].includes(cell.type)) {
             assert(cell.connections.D.length == decode_json_number(cell.parameters.WIDTH));
             assert(cell.connections.Q.length == decode_json_number(cell.parameters.WIDTH));
             assert(cell.port_directions.D == 'input');
@@ -446,6 +451,18 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 assert(cell.port_directions.CLK == 'input');
             }
         }
+        if (['$dffe', '$adffe', '$sdffe', '$sdffce', '$dffsre', '$aldffe', '$dlatch', '$adlatch'].includes(cell.type)) {
+            assert(cell.connections.EN.length == 1);
+            assert(cell.port_directions.EN == 'input');
+        }
+        if (['$adff', '$adffe', '$adlatch'].includes(cell.type)) {
+            assert(cell.connections.ARST.length == 1);
+            assert(cell.port_directions.ARST == 'input');
+        }
+        if (['$sdff', '$sdffe', '$sdffce'].includes(cell.type)) {
+            assert(cell.connections.SRST.length == 1);
+            assert(cell.port_directions.SRST == 'input');
+        }
         if (['$dffsr', '$dffsre'].includes(cell.type)) {
             assert(cell.connections.SET.length == decode_json_number(cell.parameters.WIDTH));
             assert(cell.connections.CLR.length == decode_json_number(cell.parameters.WIDTH));
@@ -592,17 +609,28 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 };
                 break;
             case '$dffe':
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
                     enable: Boolean(decode_json_number(cell.parameters.EN_POLARITY))
                 };
                 break;
+            case '$aldff':
+                dev.bits = decode_json_number(cell.parameters.WIDTH);
+                dev.polarity = {
+                    clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
+                    aload: Boolean(decode_json_number(cell.parameters.ALOAD_POLARITY))
+                };
+                break;
+            case '$aldffe':
+                dev.bits = decode_json_number(cell.parameters.WIDTH);
+                dev.polarity = {
+                    clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
+                    enable: Boolean(decode_json_number(cell.parameters.EN_POLARITY)),
+                    aload: Boolean(decode_json_number(cell.parameters.ALOAD_POLARITY))
+                };
+                break;
             case '$adff':
-                assert(cell.connections.ARST.length == 1);
-                assert(cell.port_directions.ARST == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -611,8 +639,6 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 dev.arst_value = decode_json_constant(cell.parameters.ARST_VALUE, dev.bits);
                 break;
             case '$sdff':
-                assert(cell.connections.SRST.length == 1);
-                assert(cell.port_directions.SRST == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -621,10 +647,6 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 dev.srst_value = decode_json_constant(cell.parameters.SRST_VALUE, dev.bits);
                 break;
             case '$adffe':
-                assert(cell.connections.ARST.length == 1);
-                assert(cell.port_directions.ARST == 'input');
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -634,10 +656,6 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 dev.arst_value = decode_json_constant(cell.parameters.ARST_VALUE, dev.bits);
                 break;
             case '$sdffe':
-                assert(cell.connections.SRST.length == 1);
-                assert(cell.port_directions.SRST == 'input');
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -647,10 +665,6 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 dev.srst_value = decode_json_constant(cell.parameters.SRST_VALUE, dev.bits);
                 break;
             case '$sdffce':
-                assert(cell.connections.SRST.length == 1);
-                assert(cell.port_directions.SRST == 'input');
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -661,18 +675,12 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 dev.srst_value = decode_json_constant(cell.parameters.SRST_VALUE, dev.bits);
                 break;
             case '$dlatch':
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     enable: Boolean(decode_json_number(cell.parameters.EN_POLARITY))
                 };
                 break;
             case '$adlatch':
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
-                assert(cell.connections.ARST.length == 1);
-                assert(cell.port_directions.ARST == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     enable: Boolean(decode_json_number(cell.parameters.EN_POLARITY)),
@@ -689,8 +697,6 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 };
                 break;
             case '$dffsre':
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -860,6 +866,23 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
                 }
                 break;
             }
+            case '$lut':
+                assert(cell.connections.A.length == decode_json_number(cell.parameters.WIDTH));
+                assert(cell.connections.Y.length == 1);
+                assert(cell.port_directions.A == 'input');
+                assert(cell.port_directions.Y == 'output');
+                dev.abits = cell.connections.A.length;
+                dev.bits = cell.connections.Y.length;
+                dev.rdports = [{}];
+                dev.wrports = [];
+                dev.memdata = cell.parameters.LUT.split('').reverse();
+                assert(dev.memdata.length == Math.pow(2, dev.abits));
+                // Rewrite cell connections to be $mem compatible for port mapping
+                cell.connections.RD_ADDR = cell.connections.A;
+                cell.connections.RD_DATA = cell.connections.Y;
+                delete cell.connections.A;
+                delete cell.connections.Y;
+                break;
             default:
         }
         if (dev.type == 'Dff') {
@@ -882,6 +905,8 @@ function yosys_to_digitaljs_mod(name, mod, portmaps, options = {}) {
             connect_mem(dname, cell, dev);
         else if (cell.type == '$mem_v2')
             connect_mem(dname, cell, dev);
+        else if (cell.type == '$lut')
+            connect_mem(dname, cell, dev);
         else
             throw Error('Invalid cell type: ' + cell.type);
     }
@@ -1020,6 +1045,18 @@ async function verilator_lint(filenames, dirname, options = {}) {
     }
 }
 exports.verilator_lint = verilator_lint;
+function yosys2digitaljs(obj, options = {}) {
+    const portmaps = order_ports(obj);
+    const out = yosys_to_digitaljs(obj, portmaps, options);
+    const toporder = topsort(module_deps(obj));
+    toporder.pop();
+    const toplevel = toporder.pop();
+    const output = Object.assign({ subcircuits: {} }, out[toplevel]);
+    for (const x of toporder)
+        output.subcircuits[x] = out[x];
+    return output;
+}
+exports.yosys2digitaljs = yosys2digitaljs;
 async function process(filenames, dirname, options = {}) {
     const optimize_simp = options.optimize ? "; opt" : "; opt_clean";
     const optimize = options.optimize ? "; opt -full" : "; opt_clean";
@@ -1044,14 +1081,7 @@ async function process(filenames, dirname, options = {}) {
         }
         obj = JSON.parse(fs.readFileSync(tmpjson, 'utf8'));
         await (0, util_1.promisify)(fs.unlink)(tmpjson);
-        const portmaps = order_ports(obj);
-        const out = yosys_to_digitaljs(obj, portmaps, options);
-        const toporder = topsort(module_deps(obj));
-        toporder.pop();
-        const toplevel = toporder.pop();
-        const output = Object.assign({ subcircuits: {} }, out[toplevel]);
-        for (const x of toporder)
-            output.subcircuits[x] = out[x];
+        const output = yosys2digitaljs(obj, options);
         const ret = {
             output: output,
             yosys_output: obj,
@@ -1083,12 +1113,18 @@ function io_ui(output) {
         }
         if (dev.type == 'Input')
             dev.type = dev.bits == 1 ? 'Button' : 'NumEntry';
-        if (dev.type == 'Output')
-            dev.type = dev.bits == 1 ? 'Lamp' : 'NumDisplay';
+        if (dev.type == 'Output') {
+            if (dev.bits == 1)
+                dev.type = 'Lamp';
+            else if (dev.bits == 8 && (dev.label == 'display7' || dev.label.startsWith('display7_')))
+                dev.type = 'Display7';
+            else
+                dev.type = 'NumDisplay';
+        }
     }
 }
 exports.io_ui = io_ui;
-async function process_files(data, options) {
+async function process_files(data, options = {}) {
     const dir = await tmp.dir();
     const names = [];
     try {
@@ -1108,12 +1144,12 @@ async function process_files(data, options) {
     }
 }
 exports.process_files = process_files;
-async function process_sv(text) {
+async function process_sv(text, options = {}) {
     const tmpsv = await tmp.file({ postfix: '.sv' });
     try {
         await (0, util_1.promisify)(fs.write)(tmpsv.fd, text);
         await (0, util_1.promisify)(fs.close)(tmpsv.fd);
-        return await process([tmpsv.path]);
+        return await process([tmpsv.path], undefined, options);
     }
     finally {
         tmpsv.cleanup();

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "yosys2digitaljs",
-  "version": "0.5.0",
+  "version": "0.7.0",
   "description": "Export Yosys netlists to a logic simulator",
   "main": "dist/index",
   "types": "dist/index.d.ts",
@@ -13,7 +13,7 @@
   "author": "Marek Materzok",
   "license": "BSD-2-Clause",
   "dependencies": {
-    "3vl": "^0.3.5",
+    "3vl": "^1.0.1",
     "big-integer": "^1.6.49",
     "hashmap": "^2.4.0",
     "minimist": "^1.2.5",

package/result.json

@@ -0,0 +1,420 @@
+{
+  "creator": "Yosys 0.8 (git sha1 5706e90)",
+  "modules": {
+    "fsm": {
+      "attributes": {
+        "src": "tests/fsm.sv:1"
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "a": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "b": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "$auto$simplemap.cc:136:simplemap_reduce$41": {
+          "hide_name": 1,
+          "type": "$_OR_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 6 ],
+            "B": [ 7 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$auto$simplemap.cc:136:simplemap_reduce$61": {
+          "hide_name": 1,
+          "type": "$_OR_",
+          "parameters": {
+          },
+          "attributes": {
+            "src": "tests/fsm.sv:16"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 7 ],
+            "B": [ 9 ],
+            "Y": [ 10 ]
+          }
+        },
+        "$auto$simplemap.cc:136:simplemap_reduce$63": {
+          "hide_name": 1,
+          "type": "$_OR_",
+          "parameters": {
+          },
+          "attributes": {
+            "src": "tests/fsm.sv:16"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 6 ],
+            "B": [ 11 ],
+            "Y": [ 12 ]
+          }
+        },
+        "$auto$simplemap.cc:206:simplemap_lognot$52": {
+          "hide_name": 1,
+          "type": "$_NOT_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "A": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 13 ],
+            "Y": [ 14 ]
+          }
+        },
+        "$auto$simplemap.cc:206:simplemap_lognot$59": {
+          "hide_name": 1,
+          "type": "$_NOT_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "A": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 15 ],
+            "Y": [ 16 ]
+          }
+        },
+        "$auto$simplemap.cc:496:simplemap_adff$42": {
+          "hide_name": 1,
+          "type": "$_DFF_PP1_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 2 ],
+            "D": [ 11 ],
+            "Q": [ 6 ],
+            "R": [ 3 ]
+          }
+        },
+        "$auto$simplemap.cc:496:simplemap_adff$43": {
+          "hide_name": 1,
+          "type": "$_DFF_PP0_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 9 ],
+            "R": [ 3 ]
+          }
+        },
+        "$auto$simplemap.cc:496:simplemap_adff$44": {
+          "hide_name": 1,
+          "type": "$_DFF_PP0_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 2 ],
+            "D": [ 17 ],
+            "Q": [ 7 ],
+            "R": [ 3 ]
+          }
+        },
+        "$auto$simplemap.cc:496:simplemap_adff$45": {
+          "hide_name": 1,
+          "type": "$_DFF_PP0_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 2 ],
+            "D": [ 18 ],
+            "Q": [ 11 ],
+            "R": [ 3 ]
+          }
+        },
+        "$auto$simplemap.cc:85:simplemap_bitop$38": {
+          "hide_name": 1,
+          "type": "$_AND_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 14 ],
+            "B": [ 9 ],
+            "Y": [ 17 ]
+          }
+        },
+        "$auto$simplemap.cc:85:simplemap_bitop$39": {
+          "hide_name": 1,
+          "type": "$_AND_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 16 ],
+            "B": [ 9 ],
+            "Y": [ 18 ]
+          }
+        },
+        "$auto$simplemap.cc:85:simplemap_bitop$48": {
+          "hide_name": 1,
+          "type": "$_XOR_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 4 ],
+            "B": [ "0" ],
+            "Y": [ 13 ]
+          }
+        },
+        "$auto$simplemap.cc:85:simplemap_bitop$55": {
+          "hide_name": 1,
+          "type": "$_XOR_",
+          "parameters": {
+          },
+          "attributes": {
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 4 ],
+            "B": [ "1" ],
+            "Y": [ 15 ]
+          }
+        },
+        "$procmux$3": {
+          "hide_name": 1,
+          "type": "$pmux",
+          "parameters": {
+            "S_WIDTH": 2,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "tests/fsm.sv:16"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "S": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ "x" ],
+            "B": [ "1", "0" ],
+            "S": [ 10, 12 ],
+            "Y": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$auto$fsm_map.cc:118:implement_pattern_cache$31": {
+          "hide_name": 1,
+          "bits": [ 17 ],
+          "attributes": {
+          }
+        },
+        "$auto$fsm_map.cc:118:implement_pattern_cache$35": {
+          "hide_name": 1,
+          "bits": [ 18 ],
+          "attributes": {
+          }
+        },
+        "$auto$fsm_map.cc:170:map_fsm$24": {
+          "hide_name": 1,
+          "bits": [ 19, 8 ],
+          "attributes": {
+          }
+        },
+        "$auto$fsm_map.cc:74:implement_pattern_cache$29": {
+          "hide_name": 1,
+          "bits": [ 14 ],
+          "attributes": {
+          }
+        },
+        "$auto$fsm_map.cc:74:implement_pattern_cache$33": {
+          "hide_name": 1,
+          "bits": [ 16 ],
+          "attributes": {
+          }
+        },
+        "$auto$simplemap.cc:127:simplemap_reduce$40": {
+          "hide_name": 1,
+          "bits": [ 20 ],
+          "attributes": {
+          }
+        },
+        "$auto$simplemap.cc:127:simplemap_reduce$60": {
+          "hide_name": 1,
+          "bits": [ 21 ],
+          "attributes": {
+          }
+        },
+        "$auto$simplemap.cc:127:simplemap_reduce$62": {
+          "hide_name": 1,
+          "bits": [ 22 ],
+          "attributes": {
+          }
+        },
+        "$auto$simplemap.cc:250:simplemap_eqne$46": {
+          "hide_name": 1,
+          "bits": [ 13 ],
+          "attributes": {
+          }
+        },
+        "$auto$simplemap.cc:250:simplemap_eqne$53": {
+          "hide_name": 1,
+          "bits": [ 15 ],
+          "attributes": {
+          }
+        },
+        "$auto$simplemap.cc:256:simplemap_eqne$49": {
+          "hide_name": 1,
+          "bits": [ 13 ],
+          "attributes": {
+          }
+        },
+        "$auto$simplemap.cc:256:simplemap_eqne$56": {
+          "hide_name": 1,
+          "bits": [ 15 ],
+          "attributes": {
+          }
+        },
+        "$auto$wreduce.cc:347:run$37": {
+          "hide_name": 1,
+          "bits": [ 19, 8, 23, 24 ],
+          "attributes": {
+          }
+        },
+        "$procmux$4_CTRL": {
+          "hide_name": 1,
+          "bits": [ 10 ],
+          "attributes": {
+          }
+        },
+        "$procmux$5_CTRL": {
+          "hide_name": 1,
+          "bits": [ 12 ],
+          "attributes": {
+          }
+        },
+        "a": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "tests/fsm.sv:1"
+          }
+        },
+        "b": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "tests/fsm.sv:1"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "tests/fsm.sv:1"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "tests/fsm.sv:1"
+          }
+        },
+        "state": {
+          "hide_name": 0,
+          "bits": [ 6, 9, 7, 11 ],
+          "attributes": {
+            "onehot": 1
+          }
+        }
+      }
+    }
+  }
+}

package/src/index.ts

@@ -61,6 +61,7 @@ const gate_subst = new Map([
     ['$pmux', 'Mux1Hot'],
     ['$mem', 'Memory'],
     ['$mem_v2', 'Memory'],
+    ['$lut', 'Memory'],
     ['$fsm', 'FSM'],
     ['$clock', 'Clock'],
     ['$button', 'Button'],
@@ -94,7 +95,9 @@ const gate_subst = new Map([
     ['$adlatch', 'Dff'],
     ['$sr', 'Dff'],
     ['$dffsr', 'Dff'],
-    ['$dffsre', 'Dff']]);
+    ['$dffsre', 'Dff'],
+    ['$aldff', 'Dff'],
+    ['$aldffe', 'Dff']]);
 const gate_negations = new Map([
     ['And', 'Nand'],
     ['Nand', 'And'],
@@ -245,8 +248,11 @@ namespace Yosys {
 
 };
 
-type Options = {
+type ConvertOptions = {
     propagation?: number,
+};
+
+type Options = ConvertOptions & {
     optimize?: boolean,
     fsmexpand?: boolean,
     fsm?: boolean | "nomap",
@@ -330,6 +336,8 @@ function order_ports(data: Yosys.Output): Portmaps {
         '$adlatch': {EN: 'en', ARST: 'arst', D: 'in', Q: 'out'},
         '$dffsr': {CLK: 'clk', SET: 'set', CLR: 'clr', D: 'in', Q: 'out'},
         '$dffsre': {CLK: 'clk', EN: 'en', SET: 'set', CLR: 'clr', D: 'in', Q: 'out'},
+        '$aldff': {CLK: 'clk', ALOAD: 'aload', AD: 'ain', D: 'in', Q: 'out'},
+        '$aldffe': {CLK: 'clk', EN: 'en', ALOAD: 'aload', AD: 'ain', D: 'in', Q: 'out'},
         '$sr': {SET: 'set', CLR: 'clr', Q: 'out'},
         '$fsm': {ARST: 'arst', CLK: 'clk', CTRL_IN: 'in', CTRL_OUT: 'out'}
     };
@@ -386,7 +394,7 @@ function parse_source_positions(str: string): Digitaljs.SourcePosition[] {
     return ret;
 }
 
-function yosys_to_digitaljs(data: Yosys.Output, portmaps: Portmaps, options: Options = {}): {[key: string]: Digitaljs.Module} {
+function yosys_to_digitaljs(data: Yosys.Output, portmaps: Portmaps, options: ConvertOptions = {}): {[key: string]: Digitaljs.Module} {
     const out = {};
     for (const [name, mod] of Object.entries(data.modules)) {
         out[name] = yosys_to_digitaljs_mod(name, mod, portmaps, options);
@@ -394,7 +402,7 @@ function yosys_to_digitaljs(data: Yosys.Output, portmaps: Portmaps, options: Opt
     return out
 }
 
-function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portmaps, options: Options = {}): Digitaljs.Module {
+function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portmaps, options: ConvertOptions = {}): Digitaljs.Module {
     function constbit(bit: Bit) {
         return bit == '0' || bit == '1' || bit == 'x';
     }
@@ -624,7 +632,7 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 assert(cell.port_directions.B == 'input');
                 assert(cell.port_directions.Y == 'output');
         }
-        if (['$dff', '$dffe', '$adff', '$adffe', '$sdff', '$sdffe', '$sdffce', '$dlatch', '$adlatch', '$dffsr', '$dffsre'].includes(cell.type)) {
+        if (['$dff', '$dffe', '$adff', '$adffe', '$sdff', '$sdffe', '$sdffce', '$dlatch', '$adlatch', '$dffsr', '$dffsre', '$aldff', '$aldffe'].includes(cell.type)) {
             assert(cell.connections.D.length == decode_json_number(cell.parameters.WIDTH));
             assert(cell.connections.Q.length == decode_json_number(cell.parameters.WIDTH));
             assert(cell.port_directions.D == 'input');
@@ -634,6 +642,18 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 assert(cell.port_directions.CLK == 'input');
             }
         }
+        if (['$dffe', '$adffe', '$sdffe', '$sdffce', '$dffsre', '$aldffe', '$dlatch', '$adlatch'].includes(cell.type)) {
+            assert(cell.connections.EN.length == 1);
+            assert(cell.port_directions.EN == 'input');
+        }
+        if (['$adff', '$adffe', '$adlatch'].includes(cell.type)) {
+            assert(cell.connections.ARST.length == 1);
+            assert(cell.port_directions.ARST == 'input');
+        }
+        if (['$sdff', '$sdffe', '$sdffce'].includes(cell.type)) {
+            assert(cell.connections.SRST.length == 1);
+            assert(cell.port_directions.SRST == 'input');
+        }
         if (['$dffsr', '$dffsre'].includes(cell.type)) {
             assert(cell.connections.SET.length == decode_json_number(cell.parameters.WIDTH));
             assert(cell.connections.CLR.length == decode_json_number(cell.parameters.WIDTH));
@@ -756,17 +776,28 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 };
                 break;
             case '$dffe':
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
                     enable: Boolean(decode_json_number(cell.parameters.EN_POLARITY))
                 };
                 break;
+            case '$aldff':
+                dev.bits = decode_json_number(cell.parameters.WIDTH);
+                dev.polarity = {
+                    clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
+                    aload: Boolean(decode_json_number(cell.parameters.ALOAD_POLARITY))
+                };
+                break;
+            case '$aldffe':
+                dev.bits = decode_json_number(cell.parameters.WIDTH);
+                dev.polarity = {
+                    clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
+                    enable: Boolean(decode_json_number(cell.parameters.EN_POLARITY)),
+                    aload: Boolean(decode_json_number(cell.parameters.ALOAD_POLARITY))
+                };
+                break;
             case '$adff':
-                assert(cell.connections.ARST.length == 1);
-                assert(cell.port_directions.ARST == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -775,8 +806,6 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 dev.arst_value = decode_json_constant(cell.parameters.ARST_VALUE, dev.bits);
                 break;
             case '$sdff':
-                assert(cell.connections.SRST.length == 1);
-                assert(cell.port_directions.SRST == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -785,10 +814,6 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 dev.srst_value = decode_json_constant(cell.parameters.SRST_VALUE, dev.bits);
                 break;
             case '$adffe':
-                assert(cell.connections.ARST.length == 1);
-                assert(cell.port_directions.ARST == 'input');
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -798,10 +823,6 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 dev.arst_value = decode_json_constant(cell.parameters.ARST_VALUE, dev.bits);
                 break;
             case '$sdffe':
-                assert(cell.connections.SRST.length == 1);
-                assert(cell.port_directions.SRST == 'input');
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -811,10 +832,6 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 dev.srst_value = decode_json_constant(cell.parameters.SRST_VALUE, dev.bits);
                 break;
             case '$sdffce':
-                assert(cell.connections.SRST.length == 1);
-                assert(cell.port_directions.SRST == 'input');
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -825,18 +842,12 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 dev.srst_value = decode_json_constant(cell.parameters.SRST_VALUE, dev.bits);
                 break;
             case '$dlatch':
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     enable: Boolean(decode_json_number(cell.parameters.EN_POLARITY))
                 };
                 break;
             case '$adlatch':
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
-                assert(cell.connections.ARST.length == 1);
-                assert(cell.port_directions.ARST == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     enable: Boolean(decode_json_number(cell.parameters.EN_POLARITY)),
@@ -853,8 +864,6 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 };
                 break;
             case '$dffsre':
-                assert(cell.connections.EN.length == 1);
-                assert(cell.port_directions.EN == 'input');
                 dev.bits = decode_json_number(cell.parameters.WIDTH);
                 dev.polarity = {
                     clock: Boolean(decode_json_number(cell.parameters.CLK_POLARITY)),
@@ -1022,6 +1031,24 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
                 }
                 break;
             }
+            case '$lut':
+                assert(cell.connections.A.length == decode_json_number(cell.parameters.WIDTH));
+                assert(cell.connections.Y.length == 1);
+                assert(cell.port_directions.A == 'input');
+                assert(cell.port_directions.Y == 'output');
+                dev.abits = cell.connections.A.length;
+                dev.bits = cell.connections.Y.length;
+                dev.rdports = [{}];
+                dev.wrports = [];
+                dev.memdata = cell.parameters.LUT.split('').reverse();
+                assert(dev.memdata.length == Math.pow(2, dev.abits));
+
+                // Rewrite cell connections to be $mem compatible for port mapping
+                cell.connections.RD_ADDR = cell.connections.A;
+                cell.connections.RD_DATA = cell.connections.Y;
+                delete cell.connections.A;
+                delete cell.connections.Y;
+                break;
             default:
         }
         if (dev.type == 'Dff') {
@@ -1040,6 +1067,7 @@ function yosys_to_digitaljs_mod(name: string, mod: Yosys.Module, portmaps: Portm
         else if (cell.type == '$pmux') connect_pmux(dname, cell);
         else if (cell.type == '$mem') connect_mem(dname, cell, dev);
         else if (cell.type == '$mem_v2') connect_mem(dname, cell, dev);
+        else if (cell.type == '$lut') connect_mem(dname, cell, dev);
         else throw Error('Invalid cell type: ' + cell.type);
     }
     // Group bits into nets for complex sources
@@ -1172,6 +1200,18 @@ export async function verilator_lint(filenames: string[], dirname?: string, opti
     }
 }
 
+export function yosys2digitaljs(obj: Yosys.Output, options: ConvertOptions = {}): Digitaljs.TopModule {
+    const portmaps = order_ports(obj);
+    const out = yosys_to_digitaljs(obj, portmaps, options);
+    const toporder = topsort(module_deps(obj));
+    toporder.pop();
+    const toplevel = toporder.pop();
+    const output: Digitaljs.TopModule = { subcircuits: {}, ... out[toplevel] };
+    for (const x of toporder)
+        output.subcircuits[x] = out[x];
+    return output;
+}
+
 export async function process(filenames: string[], dirname?: string, options: Options = {}): Promise<Output> {
     const optimize_simp = options.optimize ? "; opt" : "; opt_clean";
     const optimize = options.optimize ? "; opt -full" : "; opt_clean";
@@ -1198,13 +1238,7 @@ export async function process(filenames: string[], dirname?: string, options: Op
         }
         obj = JSON.parse(fs.readFileSync(tmpjson, 'utf8'));
         await promisify(fs.unlink)(tmpjson);
-        const portmaps = order_ports(obj);
-        const out = yosys_to_digitaljs(obj, portmaps, options);
-        const toporder = topsort(module_deps(obj));
-        toporder.pop();
-        const toplevel = toporder.pop();
-        const output: Digitaljs.TopModule = { subcircuits: {}, ... out[toplevel] };
-        for (const x of toporder) output.subcircuits[x] = out[x];
+        const output = yosys2digitaljs(obj, options);
         const ret: Output = {
             output: output,
             yosys_output: obj,
@@ -1234,12 +1268,18 @@ export function io_ui(output: Digitaljs.Module) {
         }
         if (dev.type == 'Input')
             dev.type = dev.bits == 1 ? 'Button' : 'NumEntry';
-        if (dev.type == 'Output')
-            dev.type = dev.bits == 1 ? 'Lamp' : 'NumDisplay';
+        if (dev.type == 'Output') {
+            if (dev.bits == 1)
+                dev.type = 'Lamp';
+            else if (dev.bits == 8 && (dev.label == 'display7' || dev.label.startsWith('display7_')))
+                dev.type = 'Display7';
+            else
+                dev.type = 'NumDisplay';
+        }
     }
 }
 
-export async function process_files(data: {[key: string]: string}, options: Options): Promise<Output> {
+export async function process_files(data: {[key: string]: string}, options: Options = {}): Promise<Output> {
     const dir = await tmp.dir();
     const names = [];
     try {
@@ -1257,12 +1297,12 @@ export async function process_files(data: {[key: string]: string}, options: Opti
     }
 }
 
-export async function process_sv(text: string): Promise<Output> {
+export async function process_sv(text: string, options: Options = {}): Promise<Output> {
     const tmpsv = await tmp.file({ postfix: '.sv' });
     try {
         await promisify(fs.write)(tmpsv.fd, text);
         await promisify(fs.close)(tmpsv.fd);
-        return await process([tmpsv.path]);
+        return await process([tmpsv.path], undefined, options);
     } finally {
         tmpsv.cleanup();
     }

package/tests/ram.sv

@@ -1,5 +1,5 @@
 // Simple RAM
-module rom
+module ram
 #(parameter AWIDTH = 4, DWIDTH = 4)(
   input clk,
   input [AWIDTH-1:0] addr,

package/.travis.yml

@@ -1,8 +0,0 @@
-before_install:
-  - sudo add-apt-repository ppa:saltmakrell/ppa -y
-  - sudo apt-get update
-  - sudo apt-get install -y yosys
-
-language: node_js
-node_js:
-    - "8"