yencode 1.1.2 → 1.1.3

package/binding.gyp

@@ -64,7 +64,7 @@
   "targets": [
     {
       "target_name": "yencode",
-      "dependencies": ["crcutil", "yencode_sse2", "yencode_ssse3", "yencode_clmul", "yencode_avx", "yencode_avx2", "yencode_neon", "yencode_armcrc"],
+      "dependencies": ["crcutil", "yencode_sse2", "yencode_ssse3", "yencode_clmul", "yencode_clmul256", "yencode_avx", "yencode_avx2", "yencode_vbmi2", "yencode_neon", "yencode_armcrc"],
       "sources": [
         "src/yencode.cc",
         "src/platform.cc",
@@ -206,6 +206,70 @@
         }]
       ]
     },
+    {
+      "target_name": "yencode_clmul256",
+      "type": "static_library",
+      "sources": [
+        "src/crc_folding_256.cc"
+      ],
+      "cflags!": ["-fno-omit-frame-pointer", "-fno-tree-vrp", "-fno-strict-aliasing"],
+      "cxxflags!": ["-fno-omit-frame-pointer", "-fno-tree-vrp", "-fno-strict-aliasing"],
+      "xcode_settings": {
+        "OTHER_CFLAGS!": ["-fno-omit-frame-pointer", "-fno-tree-vrp", "-fno-strict-aliasing"],
+        "OTHER_CXXFLAGS!": ["-fno-omit-frame-pointer", "-fno-tree-vrp", "-fno-strict-aliasing"]
+      },
+      "msvs_settings": {"VCCLCompilerTool": {"BufferSecurityCheck": "false"}},
+      "conditions": [
+        ['target_arch in "ia32 x64" and OS!="win"', {
+          "variables": {"supports_vpclmul%": "<!(<!(echo ${CC_target:-${CC:-cc}}) -MM -E src/crc_folding_256.cc -mavx2 -mvpclmulqdq 2>/dev/null || true)"},
+          "conditions": [
+            ['supports_vpclmul!=""', {
+              "cflags": ["-mavx2", "-mvpclmulqdq", "-mpclmul"],
+              "cxxflags": ["-mavx2", "-mvpclmulqdq", "-mpclmul"],
+              "xcode_settings": {
+                "OTHER_CFLAGS": ["-mavx2", "-mvpclmulqdq", "-mpclmul"],
+                "OTHER_CXXFLAGS": ["-mavx2", "-mvpclmulqdq", "-mpclmul"],
+              }
+            }]
+          ]
+        }],
+        ['target_arch in "ia32 x64" and OS=="win"', {
+          "msvs_settings": {"VCCLCompilerTool": {"EnableEnhancedInstructionSet": "3"}}
+        }]
+      ]
+    },
+    {
+      "target_name": "yencode_vbmi2",
+      "type": "static_library",
+      "sources": [
+        "src/decoder_vbmi2.cc", "src/encoder_vbmi2.cc"
+      ],
+      "cflags!": ["-fno-omit-frame-pointer", "-fno-tree-vrp", "-fno-strict-aliasing"],
+      "cxxflags!": ["-fno-omit-frame-pointer", "-fno-tree-vrp", "-fno-strict-aliasing"],
+      "xcode_settings": {
+        "OTHER_CFLAGS!": ["-fno-omit-frame-pointer", "-fno-tree-vrp", "-fno-strict-aliasing"],
+        "OTHER_CXXFLAGS!": ["-fno-omit-frame-pointer", "-fno-tree-vrp", "-fno-strict-aliasing"]
+      },
+      "msvs_settings": {"VCCLCompilerTool": {"BufferSecurityCheck": "false"}},
+      "conditions": [
+        ['target_arch in "ia32 x64" and OS!="win"', {
+          "variables": {"supports_vbmi2%": "<!(<!(echo ${CC_target:-${CC:-cc}}) -MM -E src/encoder_vbmi2.cc -mavx512vl -mavx512vbmi2 2>/dev/null || true)"},
+          "conditions": [
+            ['supports_vbmi2!=""', {
+              "cflags": ["-mavx512vbmi2", "-mavx512vl", "-mavx512bw", "-mpopcnt", "-mbmi", "-mbmi2", "-mlzcnt"],
+              "cxxflags": ["-mavx512vbmi2", "-mavx512vl", "-mavx512bw", "-mpopcnt", "-mbmi", "-mbmi2", "-mlzcnt"],
+              "xcode_settings": {
+                "OTHER_CFLAGS": ["-mavx512vbmi2", "-mavx512vl", "-mavx512bw", "-mpopcnt", "-mbmi", "-mbmi2", "-mlzcnt"],
+                "OTHER_CXXFLAGS": ["-mavx512vbmi2", "-mavx512vl", "-mavx512bw", "-mpopcnt", "-mbmi", "-mbmi2", "-mlzcnt"],
+              }
+            }]
+          ]
+        }],
+        ['target_arch in "ia32 x64" and OS=="win"', {
+          "msvs_settings": {"VCCLCompilerTool": {"AdditionalOptions": ["/arch:AVX512"], "EnableEnhancedInstructionSet": "0"}}
+        }]
+      ]
+    },
     {
       "target_name": "yencode_neon",
       "type": "static_library",
@@ -260,6 +324,14 @@
             "OTHER_CFLAGS": ["-march=armv8-a+crc"],
             "OTHER_CXXFLAGS": ["-march=armv8-a+crc"],
           }
+        }],
+        ['OS!="win" and target_arch=="arm"', {
+          "cflags": ["-mfpu=fp-armv8"],
+          "cxxflags": ["-mfpu=fp-armv8"],
+          "xcode_settings": {
+            "OTHER_CFLAGS": ["-mfpu=fp-armv8"],
+            "OTHER_CXXFLAGS": ["-mfpu=fp-armv8"]
+          }
         }]
       ]
     },

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "yencode",
-  "version": "1.1.2",
+  "version": "1.1.3",
   "description": "SIMD accelerated yEnc encoder/decoder and CRC32 calculator",
   "keywords": [
     "yenc",

package/src/common.h

@@ -35,18 +35,22 @@
 #endif
 
 
+#include <stdlib.h>
 #if defined(_MSC_VER) || defined(__MINGW32__) || defined(__MINGW64__)
-	#include <stdlib.h> // MSVC ARM64 seems to need this
+	// MSVC doesn't support C11 aligned_alloc: https://stackoverflow.com/a/62963007
 	#define ALIGN_ALLOC(buf, len, align) *(void**)&(buf) = _aligned_malloc((len), align)
 	#define ALIGN_FREE _aligned_free
-#elif defined(__cplusplus) && __cplusplus >= 201100 && !(defined(_MSC_VER) && (defined(__clang__) || defined(_M_ARM64) || defined(_M_ARM))) && !defined(__APPLE__)
-	// C++11 method
+#elif defined(_ISOC11_SOURCE)
+	// C11 method
 	// len needs to be a multiple of alignment, although it sometimes works if it isn't...
-	#include <cstdlib>
 	#define ALIGN_ALLOC(buf, len, align) *(void**)&(buf) = aligned_alloc(align, ((len) + (align)-1) & ~((align)-1))
 	#define ALIGN_FREE free
+#elif defined(__cplusplus) && __cplusplus >= 201700
+	// C++17 method
+	#include <cstdlib>
+	#define ALIGN_ALLOC(buf, len, align) *(void**)&(buf) = std::aligned_alloc(align, ((len) + (align)-1) & ~((align)-1))
+	#define ALIGN_FREE free
 #else
-	#include <stdlib.h>
 	#define ALIGN_ALLOC(buf, len, align) if(posix_memalign((void**)&(buf), align, (len))) (buf) = NULL
 	#define ALIGN_FREE free
 #endif
@@ -217,9 +221,9 @@ enum YEncDecIsaLevel {
 	ISA_LEVEL_SSE41 = 0x300,
 	ISA_LEVEL_SSE4_POPCNT = 0x301,
 	ISA_LEVEL_AVX = 0x381, // same as above, just used as a differentiator for `cpu_supports_isa`
-	ISA_LEVEL_AVX2 = 0x383, // also includes BMI1/2 and LZCNT
-	ISA_LEVEL_AVX3 = 0x403, // SKX variant; AVX512VL + AVX512BW
-	ISA_LEVEL_VBMI2 = 0x503 // ICL
+	ISA_LEVEL_AVX2 = 0x403, // also includes BMI1/2 and LZCNT
+	ISA_LEVEL_AVX3 = 0x503, // SKX variant; AVX512VL + AVX512BW
+	ISA_LEVEL_VBMI2 = 0x603 // ICL
 };
 #ifdef _MSC_VER
 // native tuning not supported in MSVC
@@ -249,13 +253,6 @@ enum YEncDecIsaLevel {
 # endif
 #endif
 
-#ifdef _MSC_VER
-# define _cpuid1(ar) __cpuid(ar, 1)
-#else
-# include <cpuid.h>
-# define _cpuid1(ar) __cpuid(1, ar[0], ar[1], ar[2], ar[3])
-#endif
-
 int cpu_supports_isa();
 #endif // PLATFORM_X86
 
@@ -270,7 +267,7 @@ int cpu_supports_isa();
 
 
 // GCC 8/9/10(dev) fails to optimize cases where KNOT should be used, so use intrinsic explicitly; Clang 6+ has no issue, but Clang 6/7 doesn't have the intrinsic; MSVC 2019 also fails and lacks the intrinsic
-#if defined(__GNUC__) && __GNUC__ >= 7
+#if (defined(__GNUC__) && __GNUC__ >= 7) || (defined(_MSC_VER) && _MSC_VER >= 1924)
 # define KNOT16 _knot_mask16
 # define KNOT32 _knot_mask32
 #else

package/src/crc.cc

@@ -25,8 +25,13 @@ uint32_t do_crc32_zeros(uint32_t crc1, size_t len) {
 }
 
 void crc_clmul_set_funcs(crc_func*);
+void crc_clmul256_set_funcs(crc_func*);
 void crc_arm_set_funcs(crc_func*);
 
+#ifdef PLATFORM_X86
+int cpu_supports_crc_isa();
+#endif
+
 #if defined(PLATFORM_ARM) && defined(_WIN32)
 # define WIN32_LEAN_AND_MEAN
 # include <Windows.h>
@@ -58,9 +63,10 @@ void crc_init() {
 	// instance never deleted... oh well...
 	
 #ifdef PLATFORM_X86
-	int flags[4];
-	_cpuid1(flags);
-	if((flags[2] & 0x80202) == 0x80202) // SSE4.1 + SSSE3 + CLMUL
+	int support = cpu_supports_crc_isa();
+	if(support == 2)
+		crc_clmul256_set_funcs(&_do_crc32_incremental);
+	else if(support == 1)
 		crc_clmul_set_funcs(&_do_crc32_incremental);
 #endif
 #ifdef PLATFORM_ARM

package/src/crc_arm.cc

@@ -5,6 +5,18 @@
 HEDLEY_WARNING("CRC32 acceleration is not been enabled under ARM clang-cl by default; add `-march=armv8-a+crc` to additional compiler arguments to enable");
 #endif
 
+// disable CRC on GCC versions with broken arm_acle.h
+#if defined(__ARM_FEATURE_CRC32) && defined(HEDLEY_GCC_VERSION)
+# if !defined(__aarch64__) && HEDLEY_GCC_VERSION_CHECK(7,0,0) && !HEDLEY_GCC_VERSION_CHECK(8,1,1)
+#  undef __ARM_FEATURE_CRC32
+HEDLEY_WARNING("CRC32 acceleration has been disabled due to broken arm_acle.h shipped in GCC 7.0 - 8.1 [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81497]. If you need this feature, please use a different compiler or version of GCC");
+# endif
+# if defined(__aarch64__) && HEDLEY_GCC_VERSION_CHECK(9,4,0) && !HEDLEY_GCC_VERSION_CHECK(9,5,0)
+#  undef __ARM_FEATURE_CRC32
+HEDLEY_WARNING("CRC32 acceleration has been disabled due to broken arm_acle.h shipped in GCC 9.4 [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100985]. If you need this feature, please use a different compiler or version of GCC");
+# endif
+#endif
+
 #if defined(__ARM_FEATURE_CRC32) || (defined(_M_ARM64) && !defined(__clang__)) // MSVC doesn't support CRC for ARM32
 
 /* ARMv8 accelerated CRC */
@@ -14,14 +26,30 @@ HEDLEY_WARNING("CRC32 acceleration is not been enabled under ARM clang-cl by def
 #include <arm_acle.h>
 #endif
 
+
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+# ifdef __GNUC__
+#  define _LE16 __builtin_bswap16
+#  define _LE32 __builtin_bswap32
+#  define _LE64 __builtin_bswap64
+# else
+// currently not supported
+#  error No endian swap intrinsic defined
+# endif
+#else
+# define _LE16(x) (x)
+# define _LE32(x) (x)
+# define _LE64(x) (x)
+#endif
+
 #ifdef __aarch64__
 # define WORD_T uint64_t
 # define WORDSIZE_LOG 3  // sizeof(WORD_T) == 1<<WORDSIZE_LOG
-# define CRC_WORD __crc32d
+# define CRC_WORD(crc, data) __crc32d(crc, _LE64(data))
 #else
 # define WORD_T uint32_t
 # define WORDSIZE_LOG 2  // sizeof(WORD_T) == 1<<WORDSIZE_LOG
-# define CRC_WORD __crc32w
+# define CRC_WORD(crc, data) __crc32w(crc, _LE32(data))
 #endif
 
 
@@ -64,6 +92,7 @@ static const uint32_t crc_power[] = { // pre-computed 2^n, with first 3 entries
 #endif
 
 
+
 // inspired/stolen off https://github.com/jocover/crc32_armv8/blob/master/crc32_armv8.c
 static uint32_t arm_crc_calc(uint32_t crc, const unsigned char *src, long len) {
 	
@@ -75,13 +104,13 @@ static uint32_t arm_crc_calc(uint32_t crc, const unsigned char *src, long len) {
 			len--;
 		}
 		if ((uintptr_t)src & sizeof(uint16_t)) {
-			crc = __crc32h(crc, *((uint16_t *)src));
+			crc = __crc32h(crc, _LE16(*((uint16_t *)src)));
 			src += sizeof(uint16_t);
 			len -= sizeof(uint16_t);
 		}
 #ifdef __aarch64__
 		if ((uintptr_t)src & sizeof(uint32_t)) {
-			crc = __crc32w(crc, *((uint32_t *)src));
+			crc = __crc32w(crc, _LE32(*((uint32_t *)src)));
 			src += sizeof(uint32_t);
 			len -= sizeof(uint32_t);
 		}
@@ -147,12 +176,12 @@ static uint32_t arm_crc_calc(uint32_t crc, const unsigned char *src, long len) {
 	
 #ifdef __aarch64__
 	if (len & sizeof(uint32_t)) {
-		crc = __crc32w(crc, *((uint32_t *)src));
+		crc = __crc32w(crc, _LE32(*((uint32_t *)src)));
 		src += sizeof(uint32_t);
 	}
 #endif
 	if (len & sizeof(uint16_t)) {
-		crc = __crc32h(crc, *((uint16_t *)src));
+		crc = __crc32h(crc, _LE16(*((uint16_t *)src)));
 		src += sizeof(uint16_t);
 	}
 	if (len & sizeof(uint8_t))

package/src/crc_folding.cc

@@ -19,7 +19,7 @@
 
 #include "crc_common.h"
  
-#if (defined(__PCLMUL__) && defined(__SSSE3__) && defined(__SSE4_1__)) || (defined(_MSC_VER) && _MSC_VER >= 1600 && defined(PLATFORM_X86))
+#if (defined(__PCLMUL__) && defined(__SSSE3__) && defined(__SSE4_1__)) || (defined(_MSC_VER) && _MSC_VER >= 1600 && defined(PLATFORM_X86) && !defined(__clang__))
 #include <inttypes.h>
 #include <immintrin.h>
 #include <wmmintrin.h>
@@ -135,33 +135,6 @@ ALIGN_TO(16, static const unsigned crc_mask[4]) = {
     0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
 };
 
-static __m128i reverse_bits_epi8(__m128i src) {
-#if defined(__GFNI__) && defined(YENC_BUILD_NATIVE) && YENC_BUILD_NATIVE!=0
-    return _mm_gf2p8affine_epi64_epi8(src, _mm_set_epi32(
-      0x80402010, 0x08040201,
-      0x80402010, 0x08040201
-    ), 0);
-#else
-    __m128i xmm_t0 = _mm_and_si128(src, _mm_set1_epi8(0x0f));
-    __m128i xmm_t1 = _mm_and_si128(_mm_srli_epi16(src, 4), _mm_set1_epi8(0x0f));
-    xmm_t0 = _mm_shuffle_epi8(_mm_set_epi8(
-      -16, 112, -80, 48, -48, 80, -112, 16, -32, 96, -96, 32, -64, 64, -128, 0
-      //0xf0, 0x70, 0xb0, 0x30, 0xd0, 0x50, 0x90, 0x10, 0xe0, 0x60, 0xa0, 0x20, 0xc0, 0x40, 0x80, 0
-    ), xmm_t0);
-    xmm_t1 = _mm_shuffle_epi8(_mm_set_epi8(
-      15, 7, 11, 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, 8, 0
-    ), xmm_t1);
-    return _mm_or_si128(xmm_t0, xmm_t1);
-#endif
-}
-
-#ifdef _MSC_VER
-// because MSVC doesn't use BSWAP unless you specifically tell it to...
-# include <stdlib.h>
-# define BSWAP32 _byteswap_ulong
-#else
-# define BSWAP32(n) ((((n)&0xff)<<24) | (((n)&0xff00)<<8) | (((n)&0xff0000)>>8) | (((n)&0xff000000)>>24))
-#endif
 
 static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
     unsigned long algn_diff;
@@ -170,23 +143,17 @@ static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
     // TODO: consider calculating this via a LUT instead (probably faster)
     // info from https://www.reddit.com/r/ReverseEngineering/comments/2zwhl3/mystery_constant_0x9db42487_in_intels_crc32ieee/
     // firstly, calculate: xmm_crc0 = (intial * 0x487b9c8a) mod 0x104c11db7, where 0x487b9c8a = inverse(1<<512) mod 0x104c11db7
+    xmm_t0 = _mm_cvtsi32_si128(~initial);
     
-    // reverse input bits + load into XMM register
-    uint32_t init_t = BSWAP32(initial);
-    xmm_t0 = reverse_bits_epi8(_mm_cvtsi32_si128(~init_t));
-    
-    xmm_t0 = _mm_clmulepi64_si128(xmm_t0, _mm_cvtsi32_si128(0x487b9c8a), 0);
-    xmm_t1 = _mm_and_si128(xmm_t0, _mm_set_epi32(-1,-1,-1,0)); // shifted up by 32bits to avoid shifts by using clmul's capability to select top 64bits instead
+    xmm_t0 = _mm_clmulepi64_si128(xmm_t0, _mm_set_epi32(0, 0, 0xa273bc24, 0), 0);  // reverse(0x487b9c8a)<<1 == 0xa273bc24
     xmm_t2 = _mm_set_epi32( // polynomial reduction factors
-      0, 0x04c11db7, // G*
-      1, 0x04d101df  // Q+
+      1, 0xdb710640, // G* = 0x04c11db7
+      0, 0xf7011641  // Q+ = 0x04d101df  (+1 to save an additional xor operation)
     );
-    xmm_t1 = _mm_clmulepi64_si128(xmm_t1, xmm_t2, 0);
-    xmm_t1 = _mm_clmulepi64_si128(xmm_t1, xmm_t2, 0x11);
+    xmm_t1 = _mm_clmulepi64_si128(xmm_t0, xmm_t2, 0);
+    xmm_t1 = _mm_clmulepi64_si128(xmm_t1, xmm_t2, 0x10);
     
-    __m128i xmm_crc0 = _mm_xor_si128(xmm_t0, xmm_t1);
-    // reverse bits
-    xmm_crc0 = _mm_shuffle_epi8(reverse_bits_epi8(xmm_crc0), _mm_set_epi32(-1,-1,-1,0x00010203));
+    __m128i xmm_crc0 = _mm_srli_si128(_mm_xor_si128(xmm_t0, xmm_t1), 8);
     
     __m128i xmm_crc1 = _mm_setzero_si128();
     __m128i xmm_crc2 = _mm_setzero_si128();
@@ -196,7 +163,8 @@ static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
     if (len < 16) {
         if (len == 0)
             return initial;
-        xmm_crc_part = _mm_loadu_si128((__m128i *)src);
+        xmm_crc_part = _mm_setzero_si128();
+        memcpy(&xmm_crc_part, src, len);
         goto partial;
     }
 
@@ -211,7 +179,7 @@ static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
             &xmm_crc_part);
     }
 
-    while ((len -= 64) >= 0) {
+    while (len >= 64) {
         xmm_t0 = _mm_load_si128((__m128i *)src);
         xmm_t1 = _mm_load_si128((__m128i *)src + 1);
         xmm_t2 = _mm_load_si128((__m128i *)src + 2);
@@ -235,13 +203,11 @@ static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
 #endif
 
         src += 64;
+        len -= 64;
     }
 
-    /*
-     * len = num bytes left - 64
-     */
-    if (len + 16 >= 0) {
-        len += 16;
+    if (len >= 48) {
+        len -= 48;
 
         xmm_t0 = _mm_load_si128((__m128i *)src);
         xmm_t1 = _mm_load_si128((__m128i *)src + 1);
@@ -266,8 +232,8 @@ static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
             goto done;
 
         xmm_crc_part = _mm_load_si128((__m128i *)src + 3);
-    } else if (len + 32 >= 0) {
-        len += 32;
+    } else if (len >= 32) {
+        len -= 32;
 
         xmm_t0 = _mm_load_si128((__m128i *)src);
         xmm_t1 = _mm_load_si128((__m128i *)src + 1);
@@ -290,8 +256,8 @@ static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
             goto done;
 
         xmm_crc_part = _mm_load_si128((__m128i *)src + 2);
-    } else if (len + 48 >= 0) {
-        len += 48;
+    } else if (len >= 16) {
+        len -= 16;
 
         xmm_t0 = _mm_load_si128((__m128i *)src);
 
@@ -310,7 +276,6 @@ static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
 
         xmm_crc_part = _mm_load_si128((__m128i *)src + 1);
     } else {
-        len += 64;
         if (len == 0)
             goto done;
         xmm_crc_part = _mm_load_si128((__m128i *)src);

package/src/crc_folding_256.cc

@@ -0,0 +1,230 @@
+// 256-bit version of crc_folding
+
+#include "crc_common.h"
+ 
+#if !defined(YENC_DISABLE_AVX256) && ((defined(__VPCLMULQDQ__) && defined(__AVX2__) && defined(__PCLMUL__)) || (defined(_MSC_VER) && _MSC_VER >= 1920 && defined(PLATFORM_X86) && !defined(__clang__)))
+#include <inttypes.h>
+#include <immintrin.h>
+
+
+#if defined(__AVX512VL__) && defined(YENC_BUILD_NATIVE) && YENC_BUILD_NATIVE!=0
+# define ENABLE_AVX512 1
+#endif
+
+static __m256i do_one_fold(__m256i src, __m256i data) {
+	const __m256i fold4 = _mm256_set_epi32(
+		0x00000001, 0x54442bd4,
+		0x00000001, 0xc6e41596,
+		0x00000001, 0x54442bd4,
+		0x00000001, 0xc6e41596
+	);
+#ifdef ENABLE_AVX512
+	return _mm256_ternarylogic_epi32(
+	  _mm256_clmulepi64_epi128(src, fold4, 0x01),
+	  _mm256_clmulepi64_epi128(src, fold4, 0x10),
+	  data,
+	  0x96
+	);
+#else
+	return _mm256_xor_si256(data, _mm256_xor_si256(
+	  _mm256_clmulepi64_epi128(src, fold4, 0x01),
+	  _mm256_clmulepi64_epi128(src, fold4, 0x10)
+	));
+#endif
+}
+
+ALIGN_TO(32, static const uint8_t  pshufb_rot_table[]) = {
+	0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,
+	16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+};
+// _mm256_castsi128_si256, but upper is defined to be 0
+#if (defined(__clang__) && __clang_major__ >= 5 && (!defined(__APPLE__) || __clang_major__ >= 7)) || (defined(__GNUC__) && __GNUC__ >= 10)
+// intrinsic unsupported in GCC 9 and MSVC < 2017
+# define zext128_256 _mm256_zextsi128_si256
+#else
+// technically a cast is incorrect, due to upper 128 bits being undefined, but should usually work fine
+// alternative may be `_mm256_set_m128i(_mm_setzero_si128(), v)` but unsupported on GCC < 7, and most compilers generate a VINSERTF128 instruction for it
+# ifdef __OPTIMIZE__
+#  define zext128_256 _mm256_castsi128_si256
+# else
+#  define zext128_256(x) _mm256_inserti128_si256(_mm256_setzero_si256(), x, 0)
+# endif
+#endif
+
+#ifdef ENABLE_AVX512
+# define MM256_BLENDV(a, b, m) _mm256_ternarylogic_epi32(a, b, m, 0xd8)
+# define MM_2XOR(a, b, c) _mm_ternarylogic_epi32(a, b, c, 0x96)
+#else
+# define MM256_BLENDV _mm256_blendv_epi8
+# define MM_2XOR(a, b, c) _mm_xor_si128(_mm_xor_si128(a, b), c)
+#endif
+
+static void partial_fold(const size_t len, __m256i *crc0, __m256i *crc1, __m256i crc_part) {
+	__m256i shuf = _mm256_broadcastsi128_si256(_mm_loadu_si128((__m128i*)(pshufb_rot_table + (len&15))));
+	__m256i mask = _mm256_cmpgt_epi8(shuf, _mm256_set1_epi8(15));
+	
+	*crc0 = _mm256_shuffle_epi8(*crc0, shuf);
+	*crc1 = _mm256_shuffle_epi8(*crc1, shuf);
+	crc_part = _mm256_shuffle_epi8(crc_part, shuf);
+	
+	__m256i crc_out = _mm256_permute2x128_si256(*crc0, *crc0, 0x08);  // move bottom->top
+	__m256i crc01, crc1p;
+	if(len >= 16) {
+		crc_out = MM256_BLENDV(crc_out, *crc0, mask);
+		crc01 = *crc1;
+		crc1p = crc_part;
+		*crc0 = _mm256_permute2x128_si256(*crc0, *crc1, 0x21);
+		*crc1 = _mm256_permute2x128_si256(*crc1, crc_part, 0x21);
+		crc_part = zext128_256(_mm256_extracti128_si256(crc_part, 1));
+	} else {
+		crc_out = _mm256_and_si256(crc_out, mask);
+		crc01 = _mm256_permute2x128_si256(*crc0, *crc1, 0x21);
+		crc1p = _mm256_permute2x128_si256(*crc1, crc_part, 0x21);
+	}
+	
+	*crc0 = MM256_BLENDV(*crc0, crc01, mask);
+	*crc1 = MM256_BLENDV(*crc1, crc1p, mask);
+	
+	*crc1 = do_one_fold(crc_out, *crc1);
+}
+
+
+ALIGN_TO(16, static const unsigned crc_k[]) = {
+	0xccaa009e, 0x00000000, /* rk1 */
+	0x751997d0, 0x00000001, /* rk2 */
+	0xccaa009e, 0x00000000, /* rk5 */
+	0x63cd6124, 0x00000001, /* rk6 */
+	0xf7011641, 0x00000000, /* rk7 */
+	0xdb710640, 0x00000001  /* rk8 */
+};
+
+
+static uint32_t crc_fold(const unsigned char *src, long len, uint32_t initial) {
+	// info from https://www.reddit.com/r/ReverseEngineering/comments/2zwhl3/mystery_constant_0x9db42487_in_intels_crc32ieee/
+	// firstly, calculate: xmm_crc0 = (intial * 0x487b9c8a) mod 0x104c11db7, where 0x487b9c8a = inverse(1<<512) mod 0x104c11db7
+	__m128i xmm_t0 = _mm_cvtsi32_si128(~initial);
+	
+	xmm_t0 = _mm_clmulepi64_si128(xmm_t0, _mm_set_epi32(0, 0, 0xa273bc24, 0), 0);  // reverse(0x487b9c8a)<<1 == 0xa273bc24
+	__m128i reduction = _mm_set_epi32( // polynomial reduction factors
+	  1, 0xdb710640, // G* = 0x04c11db7
+	  0, 0xf7011641  // Q+ = 0x04d101df  (+1 to save an additional xor operation)
+	);
+	__m128i xmm_t1 = _mm_clmulepi64_si128(xmm_t0, reduction, 0);
+	xmm_t1 = _mm_clmulepi64_si128(xmm_t1, reduction, 0x10);
+	
+	xmm_t0 = _mm_srli_si128(_mm_xor_si128(xmm_t0, xmm_t1), 8);
+	__m256i crc0 = zext128_256(xmm_t0);
+	__m256i crc1 = _mm256_setzero_si256();
+	
+	if (len < 32) {
+		if (len == 0)
+			return initial;
+		__m256i crc_part = _mm256_setzero_si256();
+		memcpy(&crc_part, src, len);
+		partial_fold(len, &crc0, &crc1, crc_part);
+	} else {
+		uintptr_t algn_diff = (0 - (uintptr_t)src) & 0x1F;
+		if (algn_diff) {
+			partial_fold(algn_diff, &crc0, &crc1, _mm256_loadu_si256((__m256i *)src));
+			src += algn_diff;
+			len -= algn_diff;
+		}
+		
+		while (len >= 64) {
+			crc0 = do_one_fold(crc0, _mm256_load_si256((__m256i*)src));
+			crc1 = do_one_fold(crc1, _mm256_load_si256((__m256i*)src + 1));
+			src += 64;
+			len -= 64;
+		}
+		
+		if (len >= 32) {
+			__m256i old = crc1;
+			crc1 = do_one_fold(crc0, _mm256_load_si256((__m256i*)src));
+			crc0 = old;
+			
+			len -= 32;
+			src += 32;
+		}
+		
+		if(len != 0) {
+			partial_fold(len, &crc0, &crc1, _mm256_load_si256((__m256i *)src));
+		}
+	}
+	
+	const __m128i xmm_mask = _mm_set_epi32(-1,-1,-1,0);
+	__m128i x_tmp0, x_tmp1, x_tmp2, crc_fold;
+	
+	__m128i xmm_crc0 = _mm256_castsi256_si128(crc0);
+	__m128i xmm_crc1 = _mm256_extracti128_si256(crc0, 1);
+	__m128i xmm_crc2 = _mm256_castsi256_si128(crc1);
+	__m128i xmm_crc3 = _mm256_extracti128_si256(crc1, 1);
+
+	/*
+	 * k1
+	 */
+	crc_fold = _mm_load_si128((__m128i *)crc_k);
+
+	x_tmp0 = _mm_clmulepi64_si128(xmm_crc0, crc_fold, 0x10);
+	xmm_crc0 = _mm_clmulepi64_si128(xmm_crc0, crc_fold, 0x01);
+	xmm_crc1 = MM_2XOR(xmm_crc1, x_tmp0, xmm_crc0);
+
+	x_tmp1 = _mm_clmulepi64_si128(xmm_crc1, crc_fold, 0x10);
+	xmm_crc1 = _mm_clmulepi64_si128(xmm_crc1, crc_fold, 0x01);
+	xmm_crc2 = MM_2XOR(xmm_crc2, x_tmp1, xmm_crc1);
+
+	x_tmp2 = _mm_clmulepi64_si128(xmm_crc2, crc_fold, 0x10);
+	xmm_crc2 = _mm_clmulepi64_si128(xmm_crc2, crc_fold, 0x01);
+	xmm_crc3 = MM_2XOR(xmm_crc3, x_tmp2, xmm_crc2);
+
+	/*
+	 * k5
+	 */
+	crc_fold = _mm_load_si128((__m128i *)crc_k + 1);
+
+	xmm_crc0 = xmm_crc3;
+	xmm_crc3 = _mm_clmulepi64_si128(xmm_crc3, crc_fold, 0);
+	xmm_crc0 = _mm_srli_si128(xmm_crc0, 8);
+	xmm_crc3 = _mm_xor_si128(xmm_crc3, xmm_crc0);
+
+	xmm_crc0 = xmm_crc3;
+	xmm_crc3 = _mm_slli_si128(xmm_crc3, 4);
+	xmm_crc3 = _mm_clmulepi64_si128(xmm_crc3, crc_fold, 0x10);
+#ifdef ENABLE_AVX512
+	//xmm_crc3 = _mm_maskz_xor_epi32(14, xmm_crc3, xmm_crc0);
+	xmm_crc3 = _mm_ternarylogic_epi32(xmm_crc3, xmm_crc0, xmm_mask, 0x28);
+#else
+	xmm_crc0 = _mm_and_si128(xmm_crc0, xmm_mask);
+	xmm_crc3 = _mm_xor_si128(xmm_crc3, xmm_crc0);
+#endif
+
+	/*
+	 * k7
+	 */
+	xmm_crc1 = xmm_crc3;
+	crc_fold = _mm_load_si128((__m128i *)crc_k + 2);
+
+	xmm_crc3 = _mm_clmulepi64_si128(xmm_crc3, crc_fold, 0);
+	xmm_crc3 = _mm_clmulepi64_si128(xmm_crc3, crc_fold, 0x10);
+#ifdef ENABLE_AVX512
+	xmm_crc3 = _mm_ternarylogic_epi32(xmm_crc3, xmm_crc1, xmm_crc1, 0xC3); // NOT(xmm_crc3 ^ xmm_crc1)
+#else
+	xmm_crc1 = _mm_xor_si128(xmm_crc1, xmm_mask);
+	xmm_crc3 = _mm_xor_si128(xmm_crc3, xmm_crc1);
+#endif
+	return _mm_extract_epi32(xmm_crc3, 2);
+}
+
+static uint32_t do_crc32_incremental_clmul(const void* data, size_t length, uint32_t init) {
+	return crc_fold((const unsigned char*)data, (long)length, init);
+}
+
+void crc_clmul256_set_funcs(crc_func* _do_crc32_incremental) {
+	*_do_crc32_incremental = &do_crc32_incremental_clmul;
+}
+#else
+void crc_clmul_set_funcs(crc_func* _do_crc32_incremental);
+void crc_clmul256_set_funcs(crc_func* _do_crc32_incremental) {
+	crc_clmul_set_funcs(_do_crc32_incremental);
+}
+#endif
+

package/src/decoder.cc

@@ -13,6 +13,7 @@ void decoder_set_sse2_funcs();
 void decoder_set_ssse3_funcs();
 void decoder_set_avx_funcs();
 void decoder_set_avx2_funcs();
+void decoder_set_vbmi2_funcs();
 void decoder_set_neon_funcs();
 
 
@@ -44,7 +45,9 @@ void decoder_init() {
 	decoder_set_native_funcs();
 # else
 	int use_isa = cpu_supports_isa();
-	if(use_isa >= ISA_LEVEL_AVX2)
+	if(use_isa >= ISA_LEVEL_VBMI2)
+		decoder_set_vbmi2_funcs();
+	else if(use_isa >= ISA_LEVEL_AVX2)
 		decoder_set_avx2_funcs();
 	else if(use_isa >= ISA_LEVEL_AVX)
 		decoder_set_avx_funcs();

package/src/decoder_avx2_base.h

@@ -1,8 +1,8 @@
 
 #ifdef __AVX2__
 
-// GCC (ver 6-10(dev)) fails to optimize pure C version of mask testing, but has this intrinsic; Clang >= 7 optimizes C version fine
-#if defined(__GNUC__) && __GNUC__ >= 7
+// GCC (ver 6-10(dev)) fails to optimize pure C version of mask testing, but has this intrinsic; Clang >= 7 optimizes C version fine; functions added in Clang 8
+#if (defined(__GNUC__) && __GNUC__ >= 7) || (defined(_MSC_VER) && _MSC_VER >= 1924)
 # define KORTEST32(a, b) !_kortestz_mask32_u8((a), (b))
 # define KAND32(a, b) _kand_mask32((a), (b))
 # define KOR32(a, b) _kor_mask32((a), (b))
@@ -60,6 +60,17 @@ HEDLEY_ALWAYS_INLINE void do_decode_avx2(const uint8_t* HEDLEY_RESTRICT src, lon
 			'.','.','.','.','.','.','.','.','.','.','.','.','.','.',_nextMask==2?0:'.',_nextMask==1?0:'.'
 		);
 	}
+	
+	// for some reason, MSVC Win32 seems to crash when trying to compile _mm256_mask_cmpeq_epi8_mask
+	// the crash can be fixed by switching the order of the last two arguments, but it seems to generate wrong code
+	// so just disable the optimisation as it seems to be problematic there
+#if defined(__AVX512VL__) && defined(__AVX512BW__)
+# if defined(_MSC_VER) && !defined(PLATFORM_AMD64) && !defined(__clang__)
+	const bool useAVX3MaskCmp = false;
+# else
+	const bool useAVX3MaskCmp = (use_isa >= ISA_LEVEL_AVX3);
+# endif
+#endif
 	intptr_t i;
 	for(i = -len; i; i += sizeof(__m256i)*2) {
 		__m256i oDataA = _mm256_load_si256((__m256i *)(src+i));
@@ -126,7 +137,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_avx2(const uint8_t* HEDLEY_RESTRICT src, lon
 				__mmask32 match2EqMaskA, match2EqMaskB;
 				__mmask32 match0CrMaskA, match0CrMaskB;
 				__mmask32 match2CrXDtMaskA, match2CrXDtMaskB;
-				if(use_isa >= ISA_LEVEL_AVX3 && searchEnd) {
+				if(useAVX3MaskCmp && searchEnd) {
 					match2EqMaskA = _mm256_cmpeq_epi8_mask(_mm256_set1_epi8('='), tmpData2A);
 					match2EqMaskB = _mm256_cmpeq_epi8_mask(_mm256_set1_epi8('='), tmpData2B);
 				} else
@@ -142,7 +153,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_avx2(const uint8_t* HEDLEY_RESTRICT src, lon
 					// find patterns of \r_.
 					
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
-					if(use_isa >= ISA_LEVEL_AVX3) {
+					if(useAVX3MaskCmp) {
 						match0CrMaskA = _mm256_cmpeq_epi8_mask(oDataA, _mm256_set1_epi8('\r'));
 						match0CrMaskB = _mm256_cmpeq_epi8_mask(oDataB, _mm256_set1_epi8('\r'));
 						match2CrXDtMaskA = _mm256_mask_cmpeq_epi8_mask(match0CrMaskA, tmpData2A, _mm256_set1_epi8('.'));
@@ -172,7 +183,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_avx2(const uint8_t* HEDLEY_RESTRICT src, lon
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
 					__mmask32 match1NlMaskA, match1NlMaskB;
 					__mmask32 match2NlDotMaskA, match2NlDotMaskB;
-					if(use_isa >= ISA_LEVEL_AVX3) {
+					if(useAVX3MaskCmp) {
 						match1NlMaskA = _mm256_mask_cmpeq_epi8_mask(
 							match0CrMaskA,
 							_mm256_set1_epi8('\n'),
@@ -228,7 +239,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_avx2(const uint8_t* HEDLEY_RESTRICT src, lon
 						
 						int matchEnd;
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
-						if(use_isa >= ISA_LEVEL_AVX3) {
+						if(useAVX3MaskCmp) {
 							__mmask32 match3EqYMaskA = _mm256_mask_cmpeq_epi8_mask(
 								match2EqMaskA,
 								_mm256_set1_epi8('y'),
@@ -307,7 +318,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_avx2(const uint8_t* HEDLEY_RESTRICT src, lon
 						}
 					}
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
-					if(use_isa >= ISA_LEVEL_AVX3) {
+					if(useAVX3MaskCmp) {
 						mask |= (uint64_t)match2NlDotMaskA << 2;
 						mask |= (uint64_t)match2NlDotMaskB << 34;
 						minMask = _mm256_maskz_mov_epi8(~(match2NlDotMaskB>>30), _mm256_set1_epi8('.'));
@@ -325,7 +336,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_avx2(const uint8_t* HEDLEY_RESTRICT src, lon
 					__m256i match3EqYA, match3EqYB;
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
 					__mmask32 match3EqYMaskA, match3EqYMaskB;
-					if(use_isa >= ISA_LEVEL_AVX3) {
+					if(useAVX3MaskCmp) {
 						match3EqYMaskA = _mm256_mask_cmpeq_epi8_mask(
 							match2EqMaskA,
 							_mm256_set1_epi8('y'),
@@ -355,7 +366,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_avx2(const uint8_t* HEDLEY_RESTRICT src, lon
 					if(LIKELIHOOD(0.002, partialEndFound)) {
 						bool endFound;
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
-						if(use_isa >= ISA_LEVEL_AVX3) {
+						if(useAVX3MaskCmp) {
 							__mmask32 match3LfEqYMaskA = _mm256_mask_cmpeq_epi8_mask(
 								match3EqYMaskA,
 								_mm256_set1_epi8('\n'),

package/src/decoder_neon.cc

@@ -19,14 +19,14 @@
 #endif
 
 
-// for compilers that lack these functions
-#if defined(__clang__) || (defined(__GNUC__) && (defined(__aarch64__) && __GNUC__ >= 8))
+// for compilers that lack these functions (Clang armv7 9-12 seems to have issues with multi-vector loads)
+#if (defined(__clang__) && (defined(__aarch64__) || __clang_major__<9 || __clang_major__>12)) || (defined(__GNUC__) && (defined(__aarch64__) && __GNUC__ >= 8))
 # define vld1q_u8_x2_align(p, n) vld1q_u8_x2((uint8_t*)__builtin_assume_aligned(p, n))
 #else
 # define vld1q_u8_x2_align(p, n) vcreate2_u8(vld1q_u8_align(p, (n)/2), vld1q_u8_align((p)+16, (n)/2))
 #endif
 // Clang wrongly assumes alignment on vld1q_u8_x2, and ARMv7 GCC doesn't support the function, so effectively, it can only be used in ARMv8 compilers
-#if defined(__aarch64__) && (defined(__clang__) || (defined(__GNUC__) && __GNUC__ >= 9))
+#if defined(__aarch64__) && (defined(__clang__) || HEDLEY_GCC_VERSION_CHECK(8,5,0))
 # define vst1q_u8_x2_unaligned vst1q_u8_x2
 #else
 static HEDLEY_ALWAYS_INLINE void vst1q_u8_x2_unaligned(uint8_t* p, uint8x16x2_t data) {

package/src/decoder_neon64.cc

@@ -10,9 +10,9 @@ static struct { char bytes[16]; } ALIGN_TO(16, compactLUT[32768]);
 static uint8_t eqFixLUT[256];
 
 
-
-#if !defined(__clang__) && !defined(_MSC_VER) && (!defined(__aarch64__) || !HEDLEY_GCC_VERSION_CHECK(10,0,0))
-static HEDLEY_ALWAYS_INLINE uint8x16x4_t vld1q_u8_x4(const uint8_t* p) {
+// AArch64 GCC lacks these functions until 8.5, 9.4 and 10.1 (10.0 unknown)
+#if !defined(__clang__) && !defined(_MSC_VER) && (!defined(__aarch64__) || !(HEDLEY_GCC_VERSION_CHECK(9,4,0) || (!HEDLEY_GCC_VERSION_CHECK(9,0,0) && HEDLEY_GCC_VERSION_CHECK(8,5,0))))
+static HEDLEY_ALWAYS_INLINE uint8x16x4_t _vld1q_u8_x4(const uint8_t* p) {
 	uint8x16x4_t ret;
 	ret.val[0] = vld1q_u8(p);
 	ret.val[1] = vld1q_u8(p+16);
@@ -20,12 +20,15 @@ static HEDLEY_ALWAYS_INLINE uint8x16x4_t vld1q_u8_x4(const uint8_t* p) {
 	ret.val[3] = vld1q_u8(p+48);
 	return ret;
 }
-static HEDLEY_ALWAYS_INLINE void vst1q_u8_x4(uint8_t* p, uint8x16x4_t data) {
+static HEDLEY_ALWAYS_INLINE void _vst1q_u8_x4(uint8_t* p, uint8x16x4_t data) {
 	vst1q_u8(p, data.val[0]);
 	vst1q_u8(p+16, data.val[1]);
 	vst1q_u8(p+32, data.val[2]);
 	vst1q_u8(p+48, data.val[3]);
 }
+#else
+# define _vld1q_u8_x4 vld1q_u8_x4
+# define _vst1q_u8_x4 vst1q_u8_x4
 #endif
 
 
@@ -55,7 +58,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_neon(const uint8_t* HEDLEY_RESTRICT src, lon
 	uint8x16_t yencOffset = escFirst ? vmakeq_u8(42+64,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42) : vdupq_n_u8(42);
 	long i;
 	for(i = -len; i; i += sizeof(uint8x16_t)*4) {
-		uint8x16x4_t data = vld1q_u8_x4(src+i);
+		uint8x16x4_t data = _vld1q_u8_x4(src+i);
 		uint8x16_t dataA = data.val[0];
 		uint8x16_t dataB = data.val[1];
 		uint8x16_t dataC = data.val[2];
@@ -421,7 +424,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_neon(const uint8_t* HEDLEY_RESTRICT src, lon
 			dataB = vsubq_u8(dataB, vdupq_n_u8(42));
 			dataC = vsubq_u8(dataC, vdupq_n_u8(42));
 			dataD = vsubq_u8(dataD, vdupq_n_u8(42));
-			vst1q_u8_x4(p, vcreate4_u8(dataA, dataB, dataC, dataD));
+			_vst1q_u8_x4(p, vcreate4_u8(dataA, dataB, dataC, dataD));
 			p += sizeof(uint8x16_t)*4;
 			escFirst = 0;
 			yencOffset = vdupq_n_u8(42);

package/src/decoder_sse_base.h

@@ -8,7 +8,7 @@
 #endif
 
 // GCC (ver 6-10(dev)) fails to optimize pure C version of mask testing, but has this intrinsic; Clang >= 7 optimizes C version fine
-#if defined(__GNUC__) && __GNUC__ >= 7
+#if (defined(__GNUC__) && __GNUC__ >= 7) || (defined(_MSC_VER) && _MSC_VER >= 1924)
 # define KORTEST16(a, b) !_kortestz_mask16_u8((a), (b))
 # define KAND16(a, b) _kand_mask16((a), (b))
 # define KOR16(a, b) _kor_mask16((a), (b))
@@ -112,7 +112,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 		-42,-42,-42,-42,-42,-42,-42,-42,-42,-42,-42,-42,-42,-42,-42,-42-64
 	) : _mm_set1_epi8(-42);
 	
-#if defined(__SSSE3__) && !defined(__tune_atom__) && !defined(__tune_slm__) && !defined(__tune_btver1__)
+#if defined(__SSSE3__) && !defined(__tune_atom__) && !defined(__tune_slm__) && !defined(__tune_btver1__) && !defined(__tune_btver2__)
 	const bool _USING_FAST_MATCH = (use_isa >= ISA_LEVEL_SSSE3);
 #else
 	const bool _USING_FAST_MATCH = false;
@@ -121,6 +121,13 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 	const bool _USING_BLEND_ADD = (use_isa >= ISA_LEVEL_SSE41);
 #else
 	const bool _USING_BLEND_ADD = false;
+#endif
+#if defined(__AVX512VL__) && defined(__AVX512BW__)
+# if defined(_MSC_VER) && !defined(PLATFORM_AMD64) && !defined(__clang__)
+	const bool useAVX3MaskCmp = false;
+# else
+	const bool useAVX3MaskCmp = (use_isa >= ISA_LEVEL_AVX3);
+# endif
 #endif
 	
 	__m128i lfCompare = _mm_set1_epi8('\n');
@@ -214,7 +221,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 				__mmask16 match2EqMaskA, match2EqMaskB;
 				__mmask16 match0CrMaskA, match0CrMaskB;
 				__mmask16 match2CrXDtMaskA, match2CrXDtMaskB;
-				if(use_isa >= ISA_LEVEL_AVX3 && searchEnd) {
+				if(useAVX3MaskCmp && searchEnd) {
 					match2EqMaskA = _mm_cmpeq_epi8_mask(_mm_set1_epi8('='), tmpData2A);
 					match2EqMaskB = _mm_cmpeq_epi8_mask(_mm_set1_epi8('='), tmpData2B);
 				} else
@@ -230,7 +237,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 				__m128i match2CrXDtA, match2CrXDtB;
 				if(isRaw) {
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
-					if(use_isa >= ISA_LEVEL_AVX3) {
+					if(useAVX3MaskCmp) {
 						match0CrMaskA = _mm_cmpeq_epi8_mask(oDataA, _mm_set1_epi8('\r'));
 						match0CrMaskB = _mm_cmpeq_epi8_mask(oDataB, _mm_set1_epi8('\r'));
 						match2CrXDtMaskA = _mm_mask_cmpeq_epi8_mask(match0CrMaskA, tmpData2A, _mm_set1_epi8('.'));
@@ -256,7 +263,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
 					__mmask16 match1NlMaskA, match1NlMaskB;
 					__mmask16 match2NlDotMaskA, match2NlDotMaskB;
-					if(use_isa >= ISA_LEVEL_AVX3) {
+					if(useAVX3MaskCmp) {
 						match1NlMaskA = _mm_mask_cmpeq_epi8_mask(
 							match0CrMaskA,
 							_mm_set1_epi8('\n'),
@@ -299,7 +306,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 						
 						int matchEnd;
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
-						if(use_isa >= ISA_LEVEL_AVX3) {
+						if(useAVX3MaskCmp) {
 							__mmask16 match3EqYMaskA = _mm_mask_cmpeq_epi8_mask(
 								match2EqMaskA, _mm_set1_epi8('y'), tmpData3A
 							);
@@ -373,7 +380,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 						}
 					}
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
-					if(use_isa >= ISA_LEVEL_AVX3) {
+					if(useAVX3MaskCmp) {
 						mask |= match2NlDotMaskA << 2;
 						mask |= (match2NlDotMaskB << 18) & 0xffffffff;
 						minMask = _mm_maskz_mov_epi8(~(match2NlDotMaskB>>14), _mm_set1_epi8('.'));
@@ -398,7 +405,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 					__m128i match3EqYA, match3EqYB;
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
 					__mmask16 match3EqYMaskA, match3EqYMaskB;
-					if(use_isa >= ISA_LEVEL_AVX3) {
+					if(useAVX3MaskCmp) {
 						match3EqYMaskA = _mm_mask_cmpeq_epi8_mask(
 							match2EqMaskA,
 							_mm_set1_epi8('y'),
@@ -434,7 +441,7 @@ HEDLEY_ALWAYS_INLINE void do_decode_sse(const uint8_t* HEDLEY_RESTRICT src, long
 						bool endFound;
 						
 #if defined(__AVX512VL__) && defined(__AVX512BW__)
-						if(use_isa >= ISA_LEVEL_AVX3) {
+						if(useAVX3MaskCmp) {
 							__mmask16 match3LfEqYMaskA = _mm_mask_cmpeq_epi8_mask(
 								match3EqYMaskA,
 								_mm_set1_epi8('\n'),

package/src/decoder_vbmi2.cc

@@ -0,0 +1,30 @@
+#include "common.h"
+
+#if defined(__AVX512VL__) && defined(__AVX512VBMI2__) && defined(__AVX512BW__)
+# include "decoder_common.h"
+# ifndef YENC_DISABLE_AVX256
+#  include "decoder_avx2_base.h"
+void decoder_set_vbmi2_funcs() {
+	ALIGN_ALLOC(lookups, sizeof(*lookups), 16);
+	// TODO: consider removing compact LUT
+	decoder_init_lut(lookups->eqFix, lookups->compact);
+	_do_decode = &do_decode_simd<false, false, sizeof(__m256i)*2, do_decode_avx2<false, false, ISA_LEVEL_VBMI2> >;
+	_do_decode_raw = &do_decode_simd<true, false, sizeof(__m256i)*2, do_decode_avx2<true, false, ISA_LEVEL_VBMI2> >;
+	_do_decode_end_raw = &do_decode_simd<true, true, sizeof(__m256i)*2, do_decode_avx2<true, true, ISA_LEVEL_VBMI2> >;
+}
+# else
+#  include "decoder_sse_base.h"
+void decoder_set_vbmi2_funcs() {
+	decoder_sse_init();
+	decoder_init_lut(lookups->eqFix, lookups->compact);
+	_do_decode = &do_decode_simd<false, false, sizeof(__m128i)*2, do_decode_sse<false, false, ISA_LEVEL_VBMI2> >;
+	_do_decode_raw = &do_decode_simd<true, false, sizeof(__m128i)*2, do_decode_sse<true, false, ISA_LEVEL_VBMI2> >;
+	_do_decode_end_raw = &do_decode_simd<true, true, sizeof(__m128i)*2, do_decode_sse<true, true, ISA_LEVEL_VBMI2> >;
+}
+# endif
+#else
+void decoder_set_avx2_funcs();
+void decoder_set_vbmi2_funcs() {
+	decoder_set_avx2_funcs();
+}
+#endif

package/src/encoder.cc

@@ -128,6 +128,7 @@ void encoder_sse2_init();
 void encoder_ssse3_init();
 void encoder_avx_init();
 void encoder_avx2_init();
+void encoder_vbmi2_init();
 void encoder_neon_init();
 
 #if defined(PLATFORM_X86) && defined(YENC_BUILD_NATIVE) && YENC_BUILD_NATIVE!=0
@@ -153,7 +154,9 @@ void encoder_init() {
 	encoder_native_init();
 # else
 	int use_isa = cpu_supports_isa();
-	if(use_isa >= ISA_LEVEL_AVX2)
+	if(use_isa >= ISA_LEVEL_VBMI2)
+		encoder_vbmi2_init();
+	else if(use_isa >= ISA_LEVEL_AVX2)
 		encoder_avx2_init();
 	else if(use_isa >= ISA_LEVEL_AVX)
 		encoder_avx_init();

package/src/encoder_avx_base.h

@@ -6,7 +6,7 @@
 #include "encoder_common.h"
 #define YMM_SIZE 32
 
-#if defined(__GNUC__) && __GNUC__ >= 7
+#if (defined(__GNUC__) && __GNUC__ >= 7) || (defined(_MSC_VER) && _MSC_VER >= 1924)
 # define KLOAD32(a, offs) _load_mask32((__mmask32*)(a) + (offs))
 #else
 # define KLOAD32(a, offs) (((uint32_t*)(a))[(offs)])
@@ -293,7 +293,7 @@ HEDLEY_ALWAYS_INLINE void do_encode_avx2(int line_size, int* colOffset, const ui
 					asm(
 						"shrq $1, %[eqMask] \n"
 						"shrq %%cl, %[eqMask] \n"
-						"adcq %[col], %[p] \n"
+						"adcq %q[col], %q[p] \n"
 						: [eqMask]"+r"(eqMask), [p]"+r"(p)
 						: "c"(shiftAmt), [col]"r"(~col)
 					);

package/src/encoder_neon.cc

@@ -5,7 +5,7 @@
 #include "encoder_common.h"
 
 // Clang wrongly assumes alignment on vst1q_u8_x2, and ARMv7 GCC doesn't support the function, so effectively, it can only be used in ARMv8 compilers
-#if defined(__aarch64__) && (defined(__clang__) || (defined(__GNUC__) && __GNUC__ >= 9))
+#if defined(__aarch64__) && (defined(__clang__) || HEDLEY_GCC_VERSION_CHECK(8,5,0))
 # define vst1q_u8_x2_unaligned vst1q_u8_x2
 #else
 static HEDLEY_ALWAYS_INLINE void vst1q_u8_x2_unaligned(uint8_t* p, uint8x16x2_t data) {

package/src/encoder_sse_base.h

@@ -8,7 +8,7 @@
 # define _mm_mask_expand_epi8 _mm128_mask_expand_epi8
 #endif
 
-#if defined(__GNUC__) && __GNUC__ >= 7
+#if (defined(__GNUC__) && __GNUC__ >= 7) || (defined(_MSC_VER) && _MSC_VER >= 1924)
 # define KLOAD16(a, offs) _load_mask16((__mmask16*)(a) + (offs))
 #else
 # define KLOAD16(a, offs) (((uint16_t*)(a))[(offs)])
@@ -155,7 +155,7 @@ HEDLEY_ALWAYS_INLINE void do_encode_sse(int line_size, int* colOffset, const uin
 	if(len <= INPUT_OFFSET || line_size < XMM_SIZE) return;
 	
 	// slower CPUs prefer to branch as mispredict penalty is probably small relative to general execution
-#if defined(__tune_atom__) || defined(__tune_slm__) || defined(__tune_btver1__)
+#if defined(__tune_atom__) || defined(__tune_slm__) || defined(__tune_btver1__) || defined(__tune_btver2__)
 	const bool _PREFER_BRANCHING = true;
 #else
 	const bool _PREFER_BRANCHING = (use_isa < ISA_LEVEL_SSSE3);
@@ -412,8 +412,8 @@ HEDLEY_ALWAYS_INLINE void do_encode_sse(int line_size, int* colOffset, const uin
 						asm(
 							"shrl $1, %[eqMask] \n"
 							"shrl %%cl, %[eqMask] \n" // TODO: can use shrq to avoid above shift?
-# if defined(PLATFORM_AMD64)
-							"adcq %[col], %[p] \n"
+# if defined(PLATFORM_AMD64) && !defined(__ILP32__)
+							"adcq %q[col], %q[p] \n"
 # else
 							"adcl %[col], %[p] \n"
 # endif
@@ -539,7 +539,6 @@ HEDLEY_ALWAYS_INLINE void do_encode_sse(int line_size, int* colOffset, const uin
 					dataA = _mm_shuffle_epi8(dataA, shufMaskA);
 					
 # if defined(__SSE4_1__) && !defined(__tune_slm__) && !defined(__tune_goldmont__) && !defined(__tune_goldmont_plus__) && !defined(__tune_tremont__)
-					// unsure if worth on: Jaguar/Puma (3|2), Core2 (2|2)
 					if(use_isa >= ISA_LEVEL_SSE41) {
 						dataB = _mm_blendv_epi8(dataBShifted, dataB, mergeMaskB);
 					} else

package/src/encoder_vbmi2.cc

@@ -0,0 +1,23 @@
+#include "common.h"
+
+#if defined(__AVX512VL__) && defined(__AVX512VBMI2__) && defined(__AVX512BW__)
+# ifndef YENC_DISABLE_AVX256
+#  include "encoder_avx_base.h"
+
+void encoder_vbmi2_init() {
+	_do_encode = &do_encode_simd< do_encode_avx2<ISA_LEVEL_VBMI2> >;
+	encoder_avx2_lut<ISA_LEVEL_VBMI2>();
+}
+# else
+#  include "encoder_sse_base.h"
+void encoder_vbmi2_init() {
+	_do_encode = &do_encode_simd< do_encode_sse<ISA_LEVEL_VBMI2> >;
+	encoder_sse_lut<ISA_LEVEL_VBMI2>();
+}
+# endif
+#else
+void encoder_avx2_init();
+void encoder_vbmi2_init() {
+	encoder_avx2_init();
+}
+#endif

package/src/platform.cc

@@ -55,6 +55,7 @@ bool cpu_supports_neon() {
 
 #ifdef PLATFORM_X86
 #ifdef _MSC_VER
+# define _cpuid1(ar) __cpuid(ar, 1)
 # define _cpuid1x(ar) __cpuid(ar, 0x80000001)
 # if _MSC_VER >= 1600
 #  define _cpuidX __cpuidex
@@ -66,6 +67,8 @@ bool cpu_supports_neon() {
 #  define _GET_XCR() 0
 # endif
 #else
+# include <cpuid.h>
+# define _cpuid1(ar) __cpuid(1, ar[0], ar[1], ar[2], ar[3])
 # define _cpuid1x(ar) __cpuid(0x80000001, ar[0], ar[1], ar[2], ar[3])
 # define _cpuidX(ar, eax, ecx) __cpuid_count(eax, ecx, ar[0], ar[1], ar[2], ar[3])
 static inline int _GET_XCR() {
@@ -112,8 +115,6 @@ int cpu_supports_isa() {
 		// AMD Bobcat with slow SSSE3 instructions - pretend it doesn't exist
 		return ret | ISA_LEVEL_SSE2;
 	
-	// Jaguar/Puma performance unkown (slowish PSHUFB/PBLENDVB)
-	
 	if((flags[2] & 0x200) == 0x200) { // SSSE3
 		if(family == 6 && (model == 0x5c || model == 0x5f || model == 0x7a || model == 0x9c))
 			// Intel Goldmont/plus / Tremont with slow PBLENDVB
@@ -144,4 +145,24 @@ int cpu_supports_isa() {
 	return ret | ISA_LEVEL_SSE2;
 }
 
+int cpu_supports_crc_isa() {
+	int flags[4];
+	_cpuid1(flags);
+	
+	if((flags[2] & 0x80202) == 0x80202) { // SSE4.1 + SSSE3 + CLMUL
+		if((flags[2] & 0x18000000) == 0x18000000) { // OSXSAVE + AVX
+			int xcr = _GET_XCR() & 0xff; // ignore unused bits
+			if((xcr & 6) == 6) { // AVX enabled
+				int cpuInfo[4];
+				_cpuidX(cpuInfo, 7, 0);
+				if((cpuInfo[1] & 0x20) == 0x20 && (cpuInfo[2] & 0x400) == 0x400) { // AVX2 + VPCLMULQDQ
+					return 2;
+				}
+			}
+		}
+		return 1;
+	}
+	return 0;
+}
+
 #endif // PLATFORM_X86

package/test/testcrc.js

@@ -50,4 +50,18 @@ doTest('Random', 'crc32', 'fj[-oqijnw34-59n26 4345j8yn89032q78t9ab9gabh023quhoiB
 doTest('Random Continue', 'crc32', ['KZSHZ5EDOVAmDdakZZOrGSUGGKSpCJoWH7M0MHy6ohnSzvHY4DjpxXmyfWYJQoJ7tKdNhGcuRVUzrgXM', ycrc32('BdenbmoBgiB10ZkeUBjrsZV3dg2Da2fhHqU9TMdi69AHhLRck3Nk60YuFBXh6lvtefBpjdTxbeEmsaEm')], crc32('BdenbmoBgiB10ZkeUBjrsZV3dg2Da2fhHqU9TMdi69AHhLRck3Nk60YuFBXh6lvtefBpjdTxbeEmsaEmKZSHZ5EDOVAmDdakZZOrGSUGGKSpCJoWH7M0MHy6ohnSzvHY4DjpxXmyfWYJQoJ7tKdNhGcuRVUzrgXM'));
 
 
+// random tests
+for(var i=1; i<128; i++) {
+	var rand = require('crypto').pseudoRandomBytes(i);
+	doTest('Random Short Buffer', 'crc32', rand);
+}
+for(var i=0; i<32; i++) {
+	var rand = require('crypto').pseudoRandomBytes(100000);
+	doTest('Random Buffer', 'crc32', rand);
+	
+	var split = Math.random()*rand.length;
+	doTest('Random Continue Buffer', 'crc32', [rand.slice(split), ycrc32(rand.slice(0, split))], crc32(rand));
+}
+
+
 console.log('All tests passed');