webgpu-bench 0.2.0 → 0.3.0

package/README.md

@@ -16,17 +16,17 @@ bandwidth/FLOPS specs.
 
 | Benchmark                                          | What it tests                                                                                                                                                                                                                                           |
 | -------------------------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
-| `read-bandwidth`                                   | Streams a large buffer in via `vec4<f32>` loads folded with addition only (no multiply, one scalar written per thread) — a read-bandwidth-bound probe of peak storage-buffer read throughput                                                            |
-| `write-bandwidth`                                  | Streams computed `vec4<f32>` values out into a large buffer with no buffer reads at all — a write-bandwidth-bound probe of peak storage-buffer write throughput                                                                                         |
+| `read-bandwidth`                                   | Coalesced grid-stride loop (adjacent threads load adjacent `vec4<f32>`s, ~256K threads) folded with addition only, one scalar written per thread — a read-bandwidth-bound probe of peak storage-buffer read throughput                                  |
+| `write-bandwidth`                                  | The same coalesced grid-stride loop storing computed `vec4<f32>` values with no buffer reads at all — a write-bandwidth-bound probe of peak storage-buffer write throughput                                                                            |
 | `flops-f32-scalar`                                 | Raw fp32 FLOPS: eight _independent_ scalar FMA chains per thread, unrolled 4x, so the ALU always has work in flight (a single dependent chain would measure FMA latency + loop overhead, not throughput)                                                |
-| `flops-f32-vec4`                                   | One FMA chain held in a `vec4<f32>` register. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) that is 4 independent scalar FMAs per step — it measures 4-wide instruction-level parallelism, not a wider ALU                                                   |
+| `flops-f32-vec4`                                   | The same eight 4x-unrolled chains held in `vec4<f32>` registers. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) each step is 4 scalar FMAs, so this should match the scalar number; a gap means vector ops cost extra                                        |
 | `flops-f32-mat4`                                   | `x = m * x + c` chained with a `mat4x4<f32>` (a bounded contraction, so it stays numerically stable over any iteration count)                                                                                                                           |
 | `flops-f32-matvec`                                 | Register-resident matvec tile: a 4x8 f32 weight tile held in registers, applied to an 8-wide input every iteration via `dot()`, outputs feeding back as the next inputs. The dot-product-accumulate shape of a GEMV inner loop with zero buffer traffic |
 | `flops-f16-scalar` / `-vec4` / `-mat4` / `-matvec` | The same four shapes, entirely in `f16` (skipped if the device lacks `shader-f16`)                                                                                                                                                                      |
 | `flops-i8-scalar` / `-vec4` / `-mat4`              | The scalar / vec4 shapes on `i32` (WGSL has no first-class `i8` type), and a 4x4 integer matvec emulated as four `vec4<i32>` rows combined with `dot()` (WGSL has no `mat4x4<i32>`)                                                                     |
 | `flops-i8-matvec`                                  | The register-resident matvec tile with int8-range weights/inputs held unpacked as `vec4<i32>` and integer `dot()` accumulation — the no-extension int8 path                                                                                             |
 | `flops-i8-matvec-dp4a`                             | The same tile with weights/inputs kept packed four int8 lanes per `u32`, each 4-wide dot product a single `dot4I8Packed` (skipped without `packed_4x8_integer_dot_product`)                                                                             |
-| `flops-i8-dp4a`                                    | `dot4I8Packed` accumulated in a tight loop to isolate the instruction's peak throughput (skipped without the feature)                                                                                                                                   |
+| `flops-i8-dp4a`                                    | `dot4I8Packed` accumulated into eight independent accumulators in a tight loop to isolate the instruction's peak throughput (skipped without the feature)                                                                                              |
 
 The two bandwidth benchmarks stream the same deterministically-generated buffer (default 4096 &times;
 4096 f32, padded to a multiple of 4). The raw-FLOPS kernels' loop trip count and per-lane operands are

package/dist/benchmarks/flopsConvert.d.ts

@@ -5,14 +5,15 @@ import type { PreparedBenchmark } from './common.ts';
  * Bit-twiddling and type-conversion ops: what quantized/packed formats
  * actually cost to get in and out of, as opposed to the flops-i8-* kernels
  * (which measure compute once data is already unpacked into i32/u32
- * registers). "Ops/s" here again isn't IEEE FLOPs, same caveat as flopsMath.ts.
+ * registers). "Ops" here count only the conversions themselves, one per
+ * direction per lane (an unpack or pack of a whole u32 counts as one), not
+ * the FMA / shifts / masks around them: the compiler folds and fuses those,
+ * so a source-level op count would overstate what executes.
  */
-/** Manual (shift+mask) byte pack/unpack: no pack4x8 (or unpack4x8) builtin, just what those compile to. */
+/** Manual (shift+mask) byte pack/unpack: no pack4x8 (or unpack4x8) builtin, just what those compile to. 2 ops per lane step (unpack + pack). */
 export declare function prepareFlopsU32PackUnpack(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** i32<->f32 round-trip: convert, FMA, convert back — the delta against the fp32 scalar test isolates conversion cost. */
+/** i32<->f32 round-trip: convert, FMA, convert back — 2 ops per lane step (one convert each way). */
 export declare function prepareFlopsI32F32Convert(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** fp32<->fp16 round-trip via pack2x16float/unpack2x16float — no shader-f16 feature needed. */
+/** fp32<->fp16 round-trip via pack2x16float/unpack2x16float — no shader-f16 feature needed. Counted as 2 ops per lane round-trip (one convert each way). */
 export declare function prepareFlopsF32F16Convert(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** i32<->f16 round-trip, chained through f32 (there's no native int<->f16 builtin). */
-export declare function prepareFlopsI32F16Convert(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 //# sourceMappingURL=flopsConvert.d.ts.map

package/dist/benchmarks/flopsConvert.d.ts.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsConvert.js

@@ -2,46 +2,39 @@ import { prepareFlopsBenchmark } from "./flopsCommon.js";
 import { flopsU32PackUnpackWgsl } from "../shaders/flopsU32PackUnpack.js";
 import { flopsI32F32ConvertWgsl } from "../shaders/flopsI32F32Convert.js";
 import { flopsF32F16ConvertWgsl } from "../shaders/flopsF32F16Convert.js";
-import { flopsI32F16ConvertWgsl } from "../shaders/flopsI32F16Convert.js";
 /**
  * Bit-twiddling and type-conversion ops: what quantized/packed formats
  * actually cost to get in and out of, as opposed to the flops-i8-* kernels
  * (which measure compute once data is already unpacked into i32/u32
- * registers). "Ops/s" here again isn't IEEE FLOPs, same caveat as flopsMath.ts.
+ * registers). "Ops" here count only the conversions themselves, one per
+ * direction per lane (an unpack or pack of a whole u32 counts as one), not
+ * the FMA / shifts / masks around them: the compiler folds and fuses those,
+ * so a source-level op count would overstate what executes.
  */
-/** Manual (shift+mask) byte pack/unpack: no pack4x8 (or unpack4x8) builtin, just what those compile to. */
+/** Manual (shift+mask) byte pack/unpack: no pack4x8 (or unpack4x8) builtin, just what those compile to. 2 ops per lane step (unpack + pack). */
 export function prepareFlopsU32PackUnpack(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-u32-packunpack',
         wgsl: flopsU32PackUnpackWgsl,
-        flopsPerIteration: 200,
+        flopsPerIteration: 64,
         defaultIterations: 256,
     }, harness);
 }
-/** i32<->f32 round-trip: convert, FMA, convert back — the delta against the fp32 scalar test isolates conversion cost. */
+/** i32<->f32 round-trip: convert, FMA, convert back — 2 ops per lane step (one convert each way). */
 export function prepareFlopsI32F32Convert(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i32-f32-convert',
         wgsl: flopsI32F32ConvertWgsl,
-        flopsPerIteration: 128,
+        flopsPerIteration: 64,
         defaultIterations: 256,
     }, harness);
 }
-/** fp32<->fp16 round-trip via pack2x16float/unpack2x16float — no shader-f16 feature needed. */
+/** fp32<->fp16 round-trip via pack2x16float/unpack2x16float — no shader-f16 feature needed. Counted as 2 ops per lane round-trip (one convert each way). */
 export function prepareFlopsF32F16Convert(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-f16-convert',
         wgsl: flopsF32F16ConvertWgsl,
-        flopsPerIteration: 192,
-        defaultIterations: 256,
-    }, harness);
-}
-/** i32<->f16 round-trip, chained through f32 (there's no native int<->f16 builtin). */
-export function prepareFlopsI32F16Convert(ctx, harness = {}) {
-    return prepareFlopsBenchmark(ctx, {
-        id: 'flops-i32-f16-convert',
-        wgsl: flopsI32F16ConvertWgsl,
-        flopsPerIteration: 192,
+        flopsPerIteration: 128,
         defaultIterations: 256,
     }, harness);
 }

package/dist/benchmarks/flopsConvert.js.map

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package/dist/benchmarks/flopsF16.d.ts

@@ -3,7 +3,7 @@ import { type FlopsHarnessConfig } from './flopsCommon.ts';
 import type { PreparedBenchmark } from './common.ts';
 /** Raw fp16 FLOPS: eight independent scalar f16 FMA chains per thread, unrolled 4x. */
 export declare function prepareFlopsF16Scalar(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** fp16 vec4 FLOPS: one f16 FMA chain on a vec4<f16> register (4 independent lanes). */
+/** fp16 vec4 FLOPS: eight independent vec4<f16> FMA chains, unrolled 4x (same shape as scalar). */
 export declare function prepareFlopsF16Vec4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 /** fp16 mat4 FLOPS: x = m*x + c chained with a mat4x4<f16>. */
 export declare function prepareFlopsF16Mat4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;

package/dist/benchmarks/flopsF16.d.ts.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsF16.js

@@ -13,13 +13,13 @@ export function prepareFlopsF16Scalar(ctx, harness = {}) {
         requiresF16: true,
     }, harness);
 }
-/** fp16 vec4 FLOPS: one f16 FMA chain on a vec4<f16> register (4 independent lanes). */
+/** fp16 vec4 FLOPS: eight independent vec4<f16> FMA chains, unrolled 4x (same shape as scalar). */
 export function prepareFlopsF16Vec4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f16-vec4',
         wgsl: flopsF16Vec4Wgsl,
-        flopsPerIteration: 8,
-        defaultIterations: 1024,
+        flopsPerIteration: 256,
+        defaultIterations: 256,
         requiresF16: true,
     }, harness);
 }

package/dist/benchmarks/flopsF16.js.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsF32.d.ts

@@ -3,7 +3,7 @@ import { type FlopsHarnessConfig } from './flopsCommon.ts';
 import type { PreparedBenchmark } from './common.ts';
 /** Raw fp32 FLOPS: eight independent scalar FMA chains per thread, unrolled 4x. */
 export declare function prepareFlopsF32Scalar(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** fp32 vec4 FLOPS: one FMA chain on a vec4<f32> register (4 independent lanes). */
+/** fp32 vec4 FLOPS: eight independent vec4<f32> FMA chains, unrolled 4x (same shape as scalar). */
 export declare function prepareFlopsF32Vec4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 /** fp32 mat4 FLOPS: x = m*x + c chained with a mat4x4<f32>. */
 export declare function prepareFlopsF32Mat4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;

package/dist/benchmarks/flopsF32.d.ts.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsF32.js

@@ -12,13 +12,13 @@ export function prepareFlopsF32Scalar(ctx, harness = {}) {
         defaultIterations: 256,
     }, harness);
 }
-/** fp32 vec4 FLOPS: one FMA chain on a vec4<f32> register (4 independent lanes). */
+/** fp32 vec4 FLOPS: eight independent vec4<f32> FMA chains, unrolled 4x (same shape as scalar). */
 export function prepareFlopsF32Vec4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-f32-vec4',
         wgsl: flopsF32Vec4Wgsl,
-        flopsPerIteration: 8,
-        defaultIterations: 1024,
+        flopsPerIteration: 256,
+        defaultIterations: 256,
     }, harness);
 }
 /** fp32 mat4 FLOPS: x = m*x + c chained with a mat4x4<f32>. */

package/dist/benchmarks/flopsF32.js.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsI8.d.ts

@@ -3,7 +3,7 @@ import { type FlopsHarnessConfig } from './flopsCommon.ts';
 import type { PreparedBenchmark } from './common.ts';
 /** Raw int8-range FLOPS: eight independent scalar i32 multiply-add chains per thread, unrolled 4x. */
 export declare function prepareFlopsI8Scalar(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** int8-range vec4 FLOPS: one integer FMA chain on a vec4<i32> register (4 independent lanes). */
+/** int8-range vec4 FLOPS: eight independent vec4<i32> multiply-add chains, unrolled 4x (same shape as scalar). */
 export declare function prepareFlopsI8Vec4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 /** int8-range mat4 FLOPS: a 4x4 integer matvec emulated via four dot(vec4<i32>) calls (WGSL has no mat4x4<i32>). */
 export declare function prepareFlopsI8Mat4(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
@@ -11,6 +11,6 @@ export declare function prepareFlopsI8Mat4(ctx: GpuContext, harness?: FlopsHarne
 export declare function prepareFlopsI8Matvec(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 /** int8 register-resident matvec tile on packed u32 words, two dot4I8Packed calls per output row. */
 export declare function prepareFlopsI8MatvecDp4a(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
-/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop. */
+/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop over eight independent accumulators. */
 export declare function prepareFlopsI8Dp4a(ctx: GpuContext, harness?: FlopsHarnessConfig): Promise<PreparedBenchmark>;
 //# sourceMappingURL=flopsI8.d.ts.map

package/dist/benchmarks/flopsI8.d.ts.map

@@ -1 +1 @@
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package/dist/benchmarks/flopsI8.js

@@ -14,13 +14,13 @@ export function prepareFlopsI8Scalar(ctx, harness = {}) {
         defaultIterations: 256,
     }, harness);
 }
-/** int8-range vec4 FLOPS: one integer FMA chain on a vec4<i32> register (4 independent lanes). */
+/** int8-range vec4 FLOPS: eight independent vec4<i32> multiply-add chains, unrolled 4x (same shape as scalar). */
 export function prepareFlopsI8Vec4(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i8-vec4',
         wgsl: flopsI8Vec4Wgsl,
-        flopsPerIteration: 8,
-        defaultIterations: 1024,
+        flopsPerIteration: 256,
+        defaultIterations: 256,
     }, harness);
 }
 /** int8-range mat4 FLOPS: a 4x4 integer matvec emulated via four dot(vec4<i32>) calls (WGSL has no mat4x4<i32>). */
@@ -51,13 +51,13 @@ export function prepareFlopsI8MatvecDp4a(ctx, harness = {}) {
         requiresI8Dot: true,
     }, harness);
 }
-/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop. */
+/** int8 packed-dot-product FLOPS: dot4I8Packed from the packed_4x8_integer_dot_product extension, run in a tight accumulation loop over eight independent accumulators. */
 export function prepareFlopsI8Dp4a(ctx, harness = {}) {
     return prepareFlopsBenchmark(ctx, {
         id: 'flops-i8-dp4a',
         wgsl: flopsI8Dp4aWgsl,
-        flopsPerIteration: 8,
-        defaultIterations: 1024,
+        flopsPerIteration: 64,
+        defaultIterations: 256,
         requiresI8Dot: true,
     }, harness);
 }

package/dist/benchmarks/flopsI8.js.map

@@ -1 +1 @@
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package/dist/benchmarks/streamBandwidth.d.ts

@@ -3,15 +3,16 @@ import type { GeneratedData } from '../data/generate.ts';
 import { type HarnessConfig, type PreparedBenchmark } from './common.ts';
 /**
  * Read-bandwidth test: streams the (already-allocated, matrix-sized) input
- * buffer through each thread with nothing but addition, writing back a
- * single scalar per thread. Reads vastly outweigh writes, so `gbps` here is
- * a read-bandwidth-bound number close to the device's peak.
+ * buffer through a coalesced grid-stride loop with nothing but addition,
+ * writing back a single scalar per thread. Reads vastly outweigh writes, so
+ * `gbps` here is a read-bandwidth-bound number close to the device's peak.
  */
 export declare function prepareReadBandwidth(ctx: GpuContext, data: GeneratedData, harness?: HarnessConfig): Promise<PreparedBenchmark>;
 /**
  * Write-bandwidth test: streams computed values out into a matrix-sized
- * output buffer. No buffer reads at all, so `gbps` here is a
- * write-bandwidth-bound number close to the device's peak.
+ * output buffer through the same coalesced grid-stride loop. No buffer reads
+ * at all, so `gbps` here is a write-bandwidth-bound number close to the
+ * device's peak.
  */
 export declare function prepareWriteBandwidth(ctx: GpuContext, data: GeneratedData, harness?: HarnessConfig): Promise<PreparedBenchmark>;
 //# sourceMappingURL=streamBandwidth.d.ts.map

package/dist/benchmarks/streamBandwidth.d.ts.map

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package/dist/benchmarks/streamBandwidth.js

@@ -2,19 +2,35 @@ import { createUniformBuffer, createStorageBuffer, createEmptyStorageBuffer } fr
 import { createPipeline, prepareKernelBenchmark } from "./common.js";
 import { streamReadWgsl } from "../shaders/streamRead.js";
 import { streamWriteWgsl } from "../shaders/streamWrite.js";
+const WORKGROUP_SIZE = 256;
+/**
+ * vec4 loads/stores per thread. Threads are sized from the buffer, not the
+ * GPU: WebGPU limits say nothing about core count or memory bus, so instead
+ * every device gets a shape that's good everywhere — coalesced grid-stride
+ * access, a few independent accesses per thread to hide latency, and enough
+ * threads (256K for the default 64 MB buffer) to fill a wide discrete GPU,
+ * while a small mobile GPU just drains the same workgroups over more waves.
+ * On an M3 this is within a few percent of the best thread count in a sweep.
+ */
+const VEC4S_PER_THREAD = 16;
+function bandwidthShape(data) {
+    const count = data.matrix.length / 4;
+    const workgroups = Math.max(1, Math.ceil(count / VEC4S_PER_THREAD / WORKGROUP_SIZE));
+    return { count, threads: workgroups * WORKGROUP_SIZE, workgroups };
+}
 /**
  * Read-bandwidth test: streams the (already-allocated, matrix-sized) input
- * buffer through each thread with nothing but addition, writing back a
- * single scalar per thread. Reads vastly outweigh writes, so `gbps` here is
- * a read-bandwidth-bound number close to the device's peak.
+ * buffer through a coalesced grid-stride loop with nothing but addition,
+ * writing back a single scalar per thread. Reads vastly outweigh writes, so
+ * `gbps` here is a read-bandwidth-bound number close to the device's peak.
  */
 export async function prepareReadBandwidth(ctx, data, harness = {}) {
     const { device } = ctx;
-    const cols4 = data.cols / 4;
+    const { count, threads, workgroups } = bandwidthShape(data);
     const pipeline = await createPipeline(device, 'stream-read', streamReadWgsl);
-    const paramsBuf = createUniformBuffer(device, new Uint32Array([data.rows, cols4]), 'params');
+    const paramsBuf = createUniformBuffer(device, new Uint32Array([count, threads]), 'params');
     const dataBuf = createStorageBuffer(device, data.matrix, 'data');
-    const outBuf = createEmptyStorageBuffer(device, data.rows * 4, 'out');
+    const outBuf = createEmptyStorageBuffer(device, threads * 4, 'out');
     const bindGroup = device.createBindGroup({
         layout: pipeline.getBindGroupLayout(0),
         entries: [
@@ -30,7 +46,7 @@ export async function prepareReadBandwidth(ctx, data, harness = {}) {
         rows: data.rows,
         cols: data.cols,
         amountPerOp: data.matrix.byteLength,
-        workgroupsPerIteration: [Math.ceil(data.rows / 64), 1, 1],
+        workgroupsPerIteration: [workgroups, 1, 1],
         pipeline,
         bindGroup,
         ...harness,
@@ -38,14 +54,15 @@ export async function prepareReadBandwidth(ctx, data, harness = {}) {
 }
 /**
  * Write-bandwidth test: streams computed values out into a matrix-sized
- * output buffer. No buffer reads at all, so `gbps` here is a
- * write-bandwidth-bound number close to the device's peak.
+ * output buffer through the same coalesced grid-stride loop. No buffer reads
+ * at all, so `gbps` here is a write-bandwidth-bound number close to the
+ * device's peak.
  */
 export async function prepareWriteBandwidth(ctx, data, harness = {}) {
     const { device } = ctx;
-    const cols4 = data.cols / 4;
+    const { count, threads, workgroups } = bandwidthShape(data);
     const pipeline = await createPipeline(device, 'stream-write', streamWriteWgsl);
-    const paramsBuf = createUniformBuffer(device, new Uint32Array([data.rows, cols4]), 'params');
+    const paramsBuf = createUniformBuffer(device, new Uint32Array([count, threads]), 'params');
     const outBuf = createEmptyStorageBuffer(device, data.matrix.byteLength, 'out');
     const bindGroup = device.createBindGroup({
         layout: pipeline.getBindGroupLayout(0),
@@ -61,7 +78,7 @@ export async function prepareWriteBandwidth(ctx, data, harness = {}) {
         rows: data.rows,
         cols: data.cols,
         amountPerOp: data.matrix.byteLength,
-        workgroupsPerIteration: [Math.ceil(data.rows / 64), 1, 1],
+        workgroupsPerIteration: [workgroups, 1, 1],
         pipeline,
         bindGroup,
         ...harness,

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package/dist/catalog.d.ts.map

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package/dist/catalog.js

@@ -25,7 +25,6 @@ import { flopsF32LogWgsl } from "./shaders/flopsF32Log.js";
 import { flopsU32PackUnpackWgsl } from "./shaders/flopsU32PackUnpack.js";
 import { flopsI32F32ConvertWgsl } from "./shaders/flopsI32F32Convert.js";
 import { flopsF32F16ConvertWgsl } from "./shaders/flopsF32F16Convert.js";
-import { flopsI32F16ConvertWgsl } from "./shaders/flopsI32F16Convert.js";
 /**
  * Every benchmark `runSuite` can yield a row for, in the same order it
  * schedules them — so a UI can render the full results table (id, label,
@@ -43,7 +42,7 @@ export const BENCHMARK_CATALOG = [
     {
         id: 'read-bandwidth',
         label: 'Read bandwidth',
-        description: 'One thread per row; streams a large buffer in via vec4<f32> loads and addition only, writes one scalar. Read-bandwidth-bound.',
+        description: 'Coalesced grid-stride loop: adjacent threads load adjacent vec4<f32>s from a large buffer, folded with addition only, one scalar written per thread. Read-bandwidth-bound.',
         source: streamReadWgsl,
         category: 'bandwidth',
         metric: BYTES_METRIC,
@@ -51,7 +50,7 @@ export const BENCHMARK_CATALOG = [
     {
         id: 'write-bandwidth',
         label: 'Write bandwidth',
-        description: 'One thread per row; stores computed vec4<f32> values into a large buffer with no buffer reads. Write-bandwidth-bound.',
+        description: 'Coalesced grid-stride loop: adjacent threads store adjacent computed vec4<f32>s into a large buffer with no buffer reads. Write-bandwidth-bound.',
         source: streamWriteWgsl,
         category: 'bandwidth',
         metric: BYTES_METRIC,
@@ -67,7 +66,7 @@ export const BENCHMARK_CATALOG = [
     {
         id: 'flops-f32-vec4',
         label: 'fp32 vec4 FLOPS',
-        description: 'A single FMA chain held in a vec4<f32> register. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) this compiles to 4 independent scalar FMAs per step, so it measures how well 4-wide instruction-level parallelism hides latency, not a wider ALU.',
+        description: 'Eight independent FMA chains held in vec4<f32> registers, unrolled 4x: the fp32 scalar test with every chain 4 lanes wide. On scalar-SIMT GPUs (Apple, NVIDIA, AMD) each step is 4 scalar FMAs, so this should match the scalar number; a gap means vector ops cost extra.',
         source: flopsF32Vec4Wgsl,
         category: 'compute',
         metric: FLOPS_METRIC,
@@ -99,7 +98,7 @@ export const BENCHMARK_CATALOG = [
     {
         id: 'flops-f16-vec4',
         label: 'fp16 vec4 FLOPS',
-        description: 'Same single FMA chain as the fp32 vec4 test, but held in a vec4<f16> register: 4 independent half-precision lanes per step. Only GPUs with packed-half ALUs run this faster than fp32.',
+        description: 'Same eight 4x-unrolled vec4 FMA chains as the fp32 vec4 test, but in vec4<f16>. Only GPUs with packed-half ALUs run this faster than fp32.',
         source: flopsF16Vec4Wgsl,
         category: 'compute',
         metric: FLOPS_METRIC,
@@ -131,7 +130,7 @@ export const BENCHMARK_CATALOG = [
     {
         id: 'flops-i8-vec4',
         label: 'int8-range vec4 FLOPS',
-        description: 'Same single multiply-add chain as the fp32 vec4 test, but held in a vec4<i32> register: 4 independent integer lanes per step.',
+        description: 'Same eight 4x-unrolled vec4 multiply-add chains as the fp32 vec4 test, but in vec4<i32>.',
         source: flopsI8Vec4Wgsl,
         category: 'compute',
         metric: OPS_METRIC,
@@ -163,7 +162,7 @@ export const BENCHMARK_CATALOG = [
     {
         id: 'flops-i8-dp4a',
         label: 'int8 dot4I8Packed FLOPS',
-        description: "One thread per lane, accumulating dot4I8Packed(a, b) — the packed_4x8_integer_dot_product extension's 4-wide int8 dot-product instruction — in a tight loop to measure its peak throughput in isolation.",
+        description: "Eight independent accumulators per thread, each summing dot4I8Packed(a, b) — the packed_4x8_integer_dot_product extension's 4-wide int8 dot-product instruction — in a tight loop to measure its peak throughput in isolation.",
         source: flopsI8Dp4aWgsl,
         category: 'compute',
         metric: OPS_METRIC,
@@ -171,7 +170,7 @@ export const BENCHMARK_CATALOG = [
     {
         id: 'flops-f32-div',
         label: 'fp32 div FLOPS',
-        description: 'Eight independent scalar f32 divide-add chains per thread, unrolled 4x — the fp32 scalar FMA test with divide in place of multiply, so the gap between the two isolates the cost of division.',
+        description: 'Eight independent scalar f32 chains of x = a / x + b per thread, unrolled 4x — the fp32 scalar FMA test with divide in place of multiply, so the gap between the two isolates the cost of division. The loop-carried value is the divisor, so the compiler cannot hoist a reciprocal and turn it back into an FMA.',
         source: flopsF32DivWgsl,
         category: 'compute',
         metric: FLOPS_METRIC,
@@ -179,7 +178,7 @@ export const BENCHMARK_CATALOG = [
     {
         id: 'flops-i32-div',
         label: 'i32 div FLOPS',
-        description: 'Eight independent scalar i32 divide-add chains per thread, unrolled 4x — the int8-range scalar test with divide in place of multiply. Integer division is typically the slowest basic ALU op on a GPU.',
+        description: 'Eight independent scalar i32 chains of x = a / x + b per thread, unrolled 4x — the int8-range scalar test with divide in place of multiply, divisor loop-carried. Integer division is typically the slowest basic ALU op on a GPU.',
         source: flopsI32DivWgsl,
         category: 'compute',
         metric: OPS_METRIC,
@@ -226,35 +225,27 @@ export const BENCHMARK_CATALOG = [
     },
     {
         id: 'flops-u32-packunpack',
-        label: 'u32 byte pack/unpack ops',
-        description: 'Eight independent u32 lanes, each step unpacking 4 bytes via shift+mask, incrementing them, and repacking the same way — no pack4x8 (or unpack4x8) builtin, just the bit-twiddling those compile to. 25 ops/lane/step, no unrolling.',
+        label: 'u32 byte pack/unpack',
+        description: 'Eight independent u32 lanes, unrolled 4x, each step unpacking 4 bytes via shift+mask, incrementing them, and repacking — no pack4x8 (or unpack4x8) builtin, just the bit-twiddling those compile to. Counted as 2 ops per lane step (one unpack + one pack of a whole u32), since the compiler folds the individual shifts and masks.',
         source: flopsU32PackUnpackWgsl,
         category: 'compute',
         metric: OPS_METRIC,
     },
     {
         id: 'flops-i32-f32-convert',
-        label: 'i32<->f32 convert FLOPS',
-        description: 'Eight independent chains per thread, unrolled 4x: xi -> f32(xi)*a+b -> back to i32 each step. Same FMA as the fp32 scalar test plus a convert on each side, so the gap against that test isolates int<->float conversion cost.',
+        label: 'i32<->f32 convert',
+        description: 'Eight independent chains per thread, unrolled 4x: xi -> f32(xi)*a+b -> back to i32 each step. Counted as 2 ops per lane step (one convert each way; the FMA is not counted).',
         source: flopsI32F32ConvertWgsl,
         category: 'compute',
         metric: OPS_METRIC,
     },
     {
         id: 'flops-f32-f16-convert',
-        label: 'f32<->f16 convert FLOPS',
-        description: 'Eight independent vec2<f32> chains per thread, unrolled 4x: pack2x16float then unpack2x16float (round-trips through fp16 bits) plus a vec2 FMA to keep the chain moving. Unlike flops-f16-*, this needs no shader-f16 device feature — it measures the conversion, not f16 compute.',
+        label: 'f32<->f16 convert',
+        description: 'Eight independent vec2<f32> chains per thread, unrolled 4x: pack2x16float then unpack2x16float (round-trips through fp16 bits) plus a vec2 FMA to keep the chain moving. Counted as 2 ops per lane per step (one convert each way; the FMA is not counted). Unlike flops-f16-*, this needs no shader-f16 device feature — it measures the conversion, not f16 compute.',
         source: flopsF32F16ConvertWgsl,
         category: 'compute',
         metric: OPS_METRIC,
     },
-    {
-        id: 'flops-i32-f16-convert',
-        label: 'i32<->f16 convert FLOPS',
-        description: 'Eight independent i32 chains per thread, unrolled 4x: xi -> f32 -> pack2x16float -> unpack2x16float -> f32*a+b -> i32. There is no native int<->f16 conversion, so this is what the real path (through f32) costs.',
-        source: flopsI32F16ConvertWgsl,
-        category: 'compute',
-        metric: OPS_METRIC,
-    },
 ];
 //# sourceMappingURL=catalog.js.map

package/dist/catalog.js.map

@@ -1 +1 @@
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