virtual-machine 0.0.3 → 0.0.10
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/build/{chunk-GZ343GYI.mjs → chunk-MELUIZWO.mjs} +6 -104
- package/build/cli.js +591 -709
- package/build/index.d.ts +2 -11
- package/build/index.js +9 -107
- package/build/index.mjs +4 -4
- package/build/{riscv_vm-3CIEJ5K7.mjs → riscv_vm-JTPPWIT3.mjs} +1 -1
- package/package.json +12 -5
- package/.yarn/install-state.gz +0 -0
- package/.yarnrc.yml +0 -1
- package/Cargo.toml +0 -49
- package/build/chunk-LJUNPJTY.mjs +0 -670
- package/build/chunk-Q7TFYQ5G.mjs +0 -670
- package/build/riscv_vm-MHIWEZQY.mjs +0 -12
- package/build/riscv_vm-VNML57ES.mjs +0 -12
- package/build.sh +0 -25
- package/cli.ts +0 -268
- package/index.ts +0 -16
- package/src/bus.rs +0 -558
- package/src/clint.rs +0 -132
- package/src/console.rs +0 -83
- package/src/cpu.rs +0 -1913
- package/src/csr.rs +0 -67
- package/src/decoder.rs +0 -789
- package/src/dram.rs +0 -146
- package/src/emulator.rs +0 -603
- package/src/lib.rs +0 -270
- package/src/main.rs +0 -373
- package/src/mmu.rs +0 -331
- package/src/net.rs +0 -121
- package/src/net_tap.rs +0 -164
- package/src/net_webtransport.rs +0 -446
- package/src/net_ws.rs +0 -396
- package/src/plic.rs +0 -261
- package/src/uart.rs +0 -233
- package/src/virtio.rs +0 -1074
- package/tsconfig.json +0 -19
- package/tsup/index.ts +0 -79
- package/tsup/tsup.cli.ts +0 -8
- package/tsup/tsup.core.cjs.ts +0 -7
- package/tsup/tsup.core.esm.ts +0 -8
package/src/dram.rs
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use thiserror::Error;
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/// Base physical address of DRAM as seen by devices that work directly with
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/// physical addresses (VirtIO, etc.).
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///
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/// This matches the DRAM base used by the `SystemBus` in `bus.rs` and the
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/// Phase-0 virt memory map.
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pub const DRAM_BASE: u64 = 0x8000_0000;
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/// Device-local memory access errors.
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///
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/// These are mapped into architectural traps (`Trap`) by higher layers
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/// (e.g., the system bus) where appropriate.
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#[derive(Debug, Error)]
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pub enum MemoryError {
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#[error("Out-of-bounds memory access at {0:#x}")]
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OutOfBounds(u64),
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#[error("Invalid or misaligned access at {0:#x}")]
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InvalidAlignment(u64),
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}
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/// Simple byte-addressable DRAM backing store used by VirtIO-style devices.
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///
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/// Offsets passed to the load/store helpers are **physical offsets from
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/// `DRAM_BASE`**, not full guest physical addresses. Callers typically use
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/// `DRAM_BASE` and subtract it via a helper (see `virtio.rs`).
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pub struct Dram {
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pub base: u64,
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pub data: Vec<u8>,
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}
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impl Dram {
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/// Create a new DRAM image of `size` bytes, zero-initialised.
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pub fn new(base: u64, size: usize) -> Self {
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Self { base, data: vec![0; size] }
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}
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pub fn offset(&self, addr: u64) -> Option<usize> {
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if addr >= self.base {
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let off = (addr - self.base) as usize;
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if off < self.data.len() {
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return Some(off);
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}
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}
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None
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}
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pub fn load(&mut self, data: &[u8], offset: u64) -> Result<(), MemoryError> {
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self.write_bytes(offset, data)
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}
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pub fn zero_range(&mut self, offset: usize, len: usize) -> Result<(), MemoryError> {
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if offset + len > self.data.len() {
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return Err(MemoryError::OutOfBounds(offset as u64));
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}
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for i in 0..len {
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self.data[offset + i] = 0;
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}
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Ok(())
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}
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fn check_bounds(&self, offset: u64, size: usize) -> Result<usize, MemoryError> {
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let off = offset as usize;
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let end = off.checked_add(size).ok_or(MemoryError::OutOfBounds(offset))?;
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if end > self.data.len() {
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return Err(MemoryError::OutOfBounds(offset));
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}
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Ok(off)
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}
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pub fn load_8(&self, offset: u64) -> Result<u8, MemoryError> {
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let off = self.check_bounds(offset, 1)?;
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Ok(self.data[off])
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}
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pub fn load_16(&self, offset: u64) -> Result<u16, MemoryError> {
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if offset % 2 != 0 {
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return Err(MemoryError::InvalidAlignment(offset));
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}
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let off = self.check_bounds(offset, 2)?;
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let bytes: [u8; 2] = self.data[off..off + 2].try_into().unwrap();
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Ok(u16::from_le_bytes(bytes))
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}
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pub fn load_32(&self, offset: u64) -> Result<u32, MemoryError> {
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if offset % 4 != 0 {
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return Err(MemoryError::InvalidAlignment(offset));
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}
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let off = self.check_bounds(offset, 4)?;
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let bytes: [u8; 4] = self.data[off..off + 4].try_into().unwrap();
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Ok(u32::from_le_bytes(bytes))
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}
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pub fn load_64(&self, offset: u64) -> Result<u64, MemoryError> {
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if offset % 8 != 0 {
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return Err(MemoryError::InvalidAlignment(offset));
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}
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let off = self.check_bounds(offset, 8)?;
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let bytes: [u8; 8] = self.data[off..off + 8].try_into().unwrap();
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Ok(u64::from_le_bytes(bytes))
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}
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pub fn store_8(&mut self, offset: u64, value: u64) -> Result<(), MemoryError> {
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let off = self.check_bounds(offset, 1)?;
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self.data[off] = (value & 0xff) as u8;
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Ok(())
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}
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pub fn store_16(&mut self, offset: u64, value: u64) -> Result<(), MemoryError> {
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if offset % 2 != 0 {
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return Err(MemoryError::InvalidAlignment(offset));
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}
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let off = self.check_bounds(offset, 2)?;
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let bytes = (value as u16).to_le_bytes();
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self.data[off..off + 2].copy_from_slice(&bytes);
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Ok(())
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}
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pub fn store_32(&mut self, offset: u64, value: u64) -> Result<(), MemoryError> {
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if offset % 4 != 0 {
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return Err(MemoryError::InvalidAlignment(offset));
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}
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let off = self.check_bounds(offset, 4)?;
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let bytes = (value as u32).to_le_bytes();
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self.data[off..off + 4].copy_from_slice(&bytes);
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Ok(())
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}
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pub fn store_64(&mut self, offset: u64, value: u64) -> Result<(), MemoryError> {
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if offset % 8 != 0 {
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return Err(MemoryError::InvalidAlignment(offset));
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}
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let off = self.check_bounds(offset, 8)?;
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let bytes = value.to_le_bytes();
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self.data[off..off + 8].copy_from_slice(&bytes);
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Ok(())
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}
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/// Write an arbitrary slice into DRAM starting at `offset`.
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pub fn write_bytes(&mut self, offset: u64, data: &[u8]) -> Result<(), MemoryError> {
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let off = self.check_bounds(offset, data.len())?;
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self.data[off..off + data.len()].copy_from_slice(data);
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Ok(())
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}
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}
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