usearch 2.8.1 → 2.8.2

package/CITATION.cff

@@ -5,7 +5,7 @@ authors:
   given-names: "Ash"
   orcid: "https://orcid.org/0000-0002-4882-1815"
 title: "USearch by Unum Cloud"
-version: 2.8.1
+version: 2.8.2
 doi: 10.5281/zenodo.7949416
 date-released: 2023-10-22
 url: "https://github.com/unum-cloud/usearch"

package/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "usearch"
-version = "2.8.1"
+version = "2.8.2"
 authors = ["Ash Vardanian <1983160+ashvardanian@users.noreply.github.com>"]
 description = "Smaller & Faster Single-File Vector Search Engine from Unum"
 edition = "2021"

package/README.md

@@ -392,7 +392,7 @@ doi = {10.5281/zenodo.7949416},
 author = {Vardanian, Ash},
 title = {{USearch by Unum Cloud}},
 url = {https://github.com/unum-cloud/usearch},
-version = {2.8.1},
+version = {2.8.2},
 year = {2023},
 month = oct,
 }

package/conanfile.py

@@ -7,7 +7,7 @@ required_conan_version = ">=1.53.0"
 class USearchConan(ConanFile):
 
     name = "usearch"
-    version = '2.8.1'
+    version = '2.8.2'
     license = "Apache-2.0"
     description = "Smaller & Faster Single-File Vector Search Engine from Unum"
     homepage = "https://github.com/unum-cloud/usearch"

package/csharp/nuget/nuget-package.props

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="utf-8"?>
 <Project>
   <PropertyGroup>
-    <Version Condition="'$(Version)' == ''">2.8.1</Version>
+    <Version Condition="'$(Version)' == ''">2.8.2</Version>
 
     <Authors>Unum</Authors>
     <Company>Unum</Company>

package/include/usearch/index.hpp

@@ -11,7 +11,7 @@
 
 #define USEARCH_VERSION_MAJOR 2
 #define USEARCH_VERSION_MINOR 8
-#define USEARCH_VERSION_PATCH 1
+#define USEARCH_VERSION_PATCH 2
 
 // Inferring C++ version
 // https://stackoverflow.com/a/61552074

package/package.json

@@ -1,6 +1,6 @@
 {
     "name": "usearch",
-    "version": "2.8.1",
+    "version": "2.8.2",
     "description": "Smaller & Faster Single-File Vector Search Engine from Unum",
     "author": "Ash Vardanian (https://ashvardanian.com/)",
     "license": "Apache 2.0",

package/simsimd/.github/workflows/prerelease.yml

@@ -61,20 +61,29 @@ jobs:
 
   test_javascript:
     name: Test JavaScript
-    runs-on: ubuntu-latest
-    strategy:
-      matrix:
-        os: [ubuntu-22.04, macOS-11, windows-2022]
-        node-version: [18.x]
+    runs-on: ubuntu-22.04
+    env:
+      CC: gcc-12
+      CXX: g++-12
+
     steps:
       - uses: actions/checkout@v4
+        with:
+          ref: "main"
+      - run: git submodule update --init --recursive
+
+      - name: Update compilers
+        run: |
+          sudo apt update
+          sudo apt install -y cmake build-essential libjemalloc-dev libomp-dev gcc-12 g++-12
+
       - name: Set up Node.js
         uses: actions/setup-node@v3
         with:
-          node-version: "18.x"
+          node-version: 18
 
-      - name: Build locally
-        run: npm install
-
-      - name: Test
-        run: npm test
+      - name: Build and Test
+        run: |
+          npm install
+          npm ci
+          npm test

package/simsimd/.github/workflows/release.yml

@@ -18,18 +18,18 @@ permissions:
 jobs:
   versioning:
     name: Semantic Release
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
     steps:
       - uses: actions/checkout@v3
         with:
           persist-credentials: false
       - uses: actions/setup-node@v3
-      - run: npm install --save-dev @semantic-release/exec @semantic-release/git conventional-changelog-eslint semantic-release && npx semantic-release
+      - run: npm install --save-dev --prefix ./package-ci @semantic-release/exec @semantic-release/git conventional-changelog-eslint semantic-release && npx --prefix ./package-ci semantic-release
 
   rebase:
     name: Rebase Dev. Branch
     needs: versioning
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
     steps:
       - name: Checkout the latest code
         uses: actions/checkout@v3
@@ -109,17 +109,33 @@ jobs:
     name: Publish JavaScript
     needs: versioning
     runs-on: ubuntu-22.04
+    env:
+      CC: gcc-12
+      CXX: g++-12
+
     steps:
       - uses: actions/checkout@v3
         with:
           ref: "main"
       - run: git submodule update --init --recursive
-      - uses: actions/setup-node@v3
+
+      - name: Update compilers
+        run: |
+          sudo apt update
+          sudo apt install -y cmake build-essential libjemalloc-dev libomp-dev gcc-12 g++-12
+
+      - name: Set up Node.js
+        uses: actions/setup-node@v3
         with:
           node-version: 18
-      - run: npm install
-      - run: npm ci
-      - run: npm test
-      - uses: JS-DevTools/npm-publish@v2
+
+      - name: Build and Test
+        run: |
+          npm install
+          npm ci
+          npm test
+
+      - name: Publish
+        uses: JS-DevTools/npm-publish@v2
         with:
           token: ${{ secrets.NPM_TOKEN }}

package/simsimd/CMakeLists.txt

@@ -46,9 +46,9 @@ if(CMAKE_CXX_COMPILER_ID MATCHES "^(Apple)?Clang$")
   if(NOT APPLE)
     add_compile_options(-march=native)
   endif()
-  add_compile_options(-pedantic -ferror-limit=1 -ffast-math)
+  add_compile_options(-pedantic -ferror-limit=1)
 elseif(CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
-  add_compile_options(-march=native -pedantic -fmax-errors=1 -ffast-math)
+  add_compile_options(-march=native -pedantic -fmax-errors=1)
 elseif(CMAKE_CXX_COMPILER_ID STREQUAL "IntelLLVM")
   add_compile_options(-w -ferror-limit=1)
 endif()

package/simsimd/README.md

@@ -34,7 +34,7 @@ Given 1000 embeddings from OpenAI Ada API with 1536 dimensions, running on the A
 
 ### Intel Sapphire Rapids
 
-On the Intel Sapphire Rapids platform, SimSIMD was benchmarked against auto-vectorized code using GCC 12. GCC handles single-precision `float` and `int8_t` well. However, it fails on `_Float16` arrays, which has been part of the C language since 2011.
+On the Intel Sapphire Rapids platform, SimSIMD was benchmarked against auto-vectorized code using GCC 12. GCC handles single-precision `float`, but might not be the best choice for `int8` and `_Float16` arrays, which has been part of the C language since 2011.
 
 |                 | GCC 12 `f32` | GCC 12 `f16` | SimSIMD `f16` | `f16` improvement |
 | :-------------- | -----------: | -----------: | ------------: | ----------------: |

package/simsimd/cpp/bench.cxx

@@ -3,8 +3,8 @@
 
 #include <benchmark/benchmark.h>
 
-#define SIMSIMD_RSQRT sqrtf
-#define SIMSIMD_LOG logf
+#define SIMSIMD_RSQRT(x) (1 / sqrtf(x))
+#define SIMSIMD_LOG(x) (logf(x))
 #include <simsimd/simsimd.h>
 
 namespace bm = benchmark;
@@ -78,7 +78,7 @@ void register_(std::string name, metric_at* distance_func, metric_at* baseline_f
     using pair_bytes_t = vectors_pair_gt<scalar_at, 1536 / sizeof(scalar_at)>;
 
     std::size_t seconds = 10;
-    std::size_t threads = std::thread::hardware_concurrency(); // 1;
+    std::size_t threads = 1; // std::thread::hardware_concurrency(); // 1;
     std::string name_dims = name + "_" + std::to_string(pair_dims_t{}.dimensions()) + "d";
     std::string name_bytes = name + "_" + std::to_string(pair_bytes_t{}.size_bytes()) + "b";
 
@@ -95,7 +95,8 @@ int main(int argc, char** argv) {
     bool compiled_with_sve = false;
     bool compiled_with_neon = false;
     bool compiled_with_avx2 = false;
-    bool compiled_with_avx512popcnt = false;
+    bool compiled_with_avx512vpopcntdq = false;
+    bool compiled_with_avx512vnni = false;
 
 #if defined(__ARM_FEATURE_SVE)
     compiled_with_sve = true;
@@ -107,7 +108,10 @@ int main(int argc, char** argv) {
     compiled_with_avx2 = true;
 #endif
 #if defined(__AVX512VPOPCNTDQ__)
-    compiled_with_avx512popcnt = true;
+    compiled_with_avx512vpopcntdq = true;
+#endif
+#if defined(__AVX512VNNI__)
+    compiled_with_avx512vnni = true;
 #endif
 
     // Log supported functionality
@@ -117,7 +121,8 @@ int main(int argc, char** argv) {
     std::printf("- Arm NEON support enabled: %s\n", flags[compiled_with_neon]);
     std::printf("- Arm SVE support enabled: %s\n", flags[compiled_with_sve]);
     std::printf("- x86 AVX2 support enabled: %s\n", flags[compiled_with_avx2]);
-    std::printf("- x86 AVX512VPOPCNTDQ support enabled: %s\n", flags[compiled_with_avx512popcnt]);
+    std::printf("- x86 AVX512VPOPCNTDQ support enabled: %s\n", flags[compiled_with_avx512vpopcntdq]);
+    std::printf("- x86 AVX512VNNI support enabled: %s\n", flags[compiled_with_avx512vnni]);
     std::printf("\n");
 
     // Run the benchmarks

package/simsimd/include/simsimd/binary.h

@@ -133,41 +133,55 @@ simsimd_sve_b8_jaccard(simsimd_b8_t const* a, simsimd_b8_t const* b, simsimd_siz
 
 #if SIMSIMD_TARGET_X86_AVX512
 
-__attribute__((target("avx512vpopcntdq,avx512vl,avx512bw,avx512f"))) //
+__attribute__((target("avx512vpopcntdq,avx512vl,avx512bw,avx512f,bmi2"))) //
 inline static simsimd_f32_t
 simsimd_avx512_b8_hamming(simsimd_b8_t const* a, simsimd_b8_t const* b, simsimd_size_t n_words) {
     __m512i differences_vec = _mm512_setzero_si512();
-    for (simsimd_size_t i = 0; i < n_words; i += 64) {
-
-        // Compute mask for tail elements
-        __mmask64 mask = (i + 64 <= n_words) ? 0xFFFFFFFFFFFFFFFF : (((1ull << (n_words - i)) - 1ull));
-        __m512i a_vec = _mm512_maskz_loadu_epi8(mask, a + i);
-        __m512i b_vec = _mm512_maskz_loadu_epi8(mask, b + i);
-        __m512i xor_vec = _mm512_xor_si512(a_vec, b_vec);
-
-        differences_vec = _mm512_add_epi64(differences_vec, _mm512_popcnt_epi64(xor_vec));
+    __m512i a_vec, b_vec;
+
+simsimd_avx512_b8_hamming_cycle:
+    if (n_words < 64) {
+        __mmask64 mask = _bzhi_u64(0xFFFFFFFFFFFFFFFF, n_words);
+        a_vec = _mm512_maskz_loadu_epi8(mask, a);
+        b_vec = _mm512_maskz_loadu_epi8(mask, b);
+        n_words = 0;
+    } else {
+        a_vec = _mm512_loadu_epi8(a);
+        b_vec = _mm512_loadu_epi8(b);
+        a += 64, b += 64, n_words -= 64;
     }
+    __m512i xor_vec = _mm512_xor_si512(a_vec, b_vec);
+    differences_vec = _mm512_add_epi64(differences_vec, _mm512_popcnt_epi64(xor_vec));
+    if (n_words)
+        goto simsimd_avx512_b8_hamming_cycle;
 
     simsimd_size_t differences = _mm512_reduce_add_epi64(differences_vec);
     return (simsimd_f32_t)differences;
 }
 
-__attribute__((target("avx512vpopcntdq,avx512vl,avx512bw,avx512f"))) //
+__attribute__((target("avx512vpopcntdq,avx512vl,avx512bw,avx512f,bmi2"))) //
 inline static simsimd_f32_t
 simsimd_avx512_b8_jaccard(simsimd_b8_t const* a, simsimd_b8_t const* b, simsimd_size_t n_words) {
     __m512i intersection_vec = _mm512_setzero_si512(), union_vec = _mm512_setzero_si512();
-    for (simsimd_size_t i = 0; i < n_words; i += 64) {
-
-        // Compute mask for tail elements
-        __mmask64 mask = (i + 64 <= n_words) ? 0xFFFFFFFFFFFFFFFF : (((1ull << (n_words - i)) - 1ull));
-        __m512i a_vec = _mm512_maskz_loadu_epi8(mask, a + i);
-        __m512i b_vec = _mm512_maskz_loadu_epi8(mask, b + i);
-        __m512i and_vec = _mm512_and_si512(a_vec, b_vec);
-        __m512i or_vec = _mm512_or_si512(a_vec, b_vec);
-
-        intersection_vec = _mm512_add_epi64(intersection_vec, _mm512_popcnt_epi64(and_vec));
-        union_vec = _mm512_add_epi64(union_vec, _mm512_popcnt_epi64(or_vec));
+    __m512i a_vec, b_vec;
+
+simsimd_avx512_b8_jaccard_cycle:
+    if (n_words < 64) {
+        __mmask64 mask = _bzhi_u64(0xFFFFFFFFFFFFFFFF, n_words);
+        a_vec = _mm512_maskz_loadu_epi8(mask, a);
+        b_vec = _mm512_maskz_loadu_epi8(mask, b);
+        n_words = 0;
+    } else {
+        a_vec = _mm512_loadu_epi8(a);
+        b_vec = _mm512_loadu_epi8(b);
+        a += 64, b += 64, n_words -= 64;
     }
+    __m512i and_vec = _mm512_and_si512(a_vec, b_vec);
+    __m512i or_vec = _mm512_or_si512(a_vec, b_vec);
+    intersection_vec = _mm512_add_epi64(intersection_vec, _mm512_popcnt_epi64(and_vec));
+    union_vec = _mm512_add_epi64(union_vec, _mm512_popcnt_epi64(or_vec));
+    if (n_words)
+        goto simsimd_avx512_b8_jaccard_cycle;
 
     simsimd_size_t intersection = _mm512_reduce_add_epi64(intersection_vec),
                    union_ = _mm512_reduce_add_epi64(union_vec);

package/simsimd/include/simsimd/probability.h

@@ -370,58 +370,70 @@ simsimd_avx512_f32_log2(__m512 x) {
     return _mm512_add_ps(_mm512_mul_ps(p, _mm512_sub_ps(m, one)), e);
 }
 
-__attribute__((target("avx512f,avx512vl"))) //
+__attribute__((target("avx512f,avx512vl,bmi2"))) //
 inline static simsimd_f32_t
 simsimd_avx512_f32_kl(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n) {
     __m512 sum_vec = _mm512_set1_ps(0);
     simsimd_f32_t epsilon = 1e-6;
     __m512 epsilon_vec = _mm512_set1_ps(epsilon);
-    for (simsimd_size_t i = 0; i < n; i += 16) {
-        __mmask16 mask = n - i >= 16 ? 0xFFFF : ((1u << (n - i)) - 1u);
-        __m512 a_vec = _mm512_add_ps(_mm512_maskz_loadu_ps(mask, a + i), epsilon_vec);
-        __m512 b_vec = _mm512_add_ps(_mm512_maskz_loadu_ps(mask, b + i), epsilon_vec);
-        __m512 ratio_vec = _mm512_div_ps(a_vec, b_vec);
-        __m512 log_ratio_vec = simsimd_avx512_f32_log2(ratio_vec);
-        __m512 prod_vec = _mm512_mul_ps(a_vec, log_ratio_vec);
-        sum_vec = _mm512_maskz_add_ps(mask, sum_vec, prod_vec);
+    __m512 a_vec, b_vec;
+
+simsimd_avx512_f32_kl_cycle:
+    if (n < 16) {
+        __mmask16 mask = _bzhi_u32(0xFFFFFFFF, n);
+        a_vec = _mm512_add_ps(_mm512_maskz_loadu_ps(mask, a), epsilon_vec);
+        b_vec = _mm512_add_ps(_mm512_maskz_loadu_ps(mask, b), epsilon_vec);
+        n = 0;
+    } else {
+        a_vec = _mm512_add_ps(_mm512_loadu_ps(a), epsilon_vec);
+        b_vec = _mm512_add_ps(_mm512_loadu_ps(b), epsilon_vec);
+        a += 16, b += 16, n -= 16;
     }
+    __m512 ratio_vec = _mm512_div_ps(a_vec, b_vec);
+    __m512 log_ratio_vec = simsimd_avx512_f32_log2(ratio_vec);
+    __m512 prod_vec = _mm512_mul_ps(a_vec, log_ratio_vec);
+    sum_vec = _mm512_add_ps(sum_vec, prod_vec);
+    if (n)
+        goto simsimd_avx512_f32_kl_cycle;
+
     simsimd_f32_t log2_normalizer = 0.693147181f;
     return _mm512_reduce_add_ps(sum_vec) * log2_normalizer;
 }
 
-__attribute__((target("avx512f,avx512vl"))) //
+__attribute__((target("avx512f,avx512vl,bmi2"))) //
 inline static simsimd_f32_t
 simsimd_avx512_f32_js(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n) {
     __m512 sum_a_vec = _mm512_set1_ps(0);
     __m512 sum_b_vec = _mm512_set1_ps(0);
     simsimd_f32_t epsilon = 1e-6;
     __m512 epsilon_vec = _mm512_set1_ps(epsilon);
-    for (simsimd_size_t i = 0; i < n; i += 16) {
-        __mmask16 mask = n - i >= 16 ? 0xFFFF : ((1u << (n - i)) - 1u);
-        __m512 a_vec = _mm512_maskz_loadu_ps(mask, a + i);
-        __m512 b_vec = _mm512_maskz_loadu_ps(mask, b + i);
-        __m512 m_vec = _mm512_mul_ps(_mm512_add_ps(a_vec, b_vec), _mm512_set1_ps(0.5f)); // M = (P + Q) / 2
-
-        // Avoid division by zero problems from probabilities under zero down the road.
-        // Masking is a nicer way to do this, than adding the `epsilon` to every component.
-        __mmask16 nonzero_mask_a = _mm512_cmp_ps_mask(a_vec, epsilon_vec, _CMP_GE_OQ);
-        __mmask16 nonzero_mask_b = _mm512_cmp_ps_mask(b_vec, epsilon_vec, _CMP_GE_OQ);
-        __mmask16 nonzero_mask = nonzero_mask_a & nonzero_mask_b & mask;
-
-        // Division is an expensive operation. Instead of doing it twice,
-        // we can approximate the reciprocal of `m` and multiply instead.
-        __m512 m_recip_approx = _mm512_rcp14_ps(m_vec); // or `_mm512_rcp28_ps` for slightly better precision
-        __m512 ratio_a_vec = _mm512_mul_ps(a_vec, m_recip_approx);
-        __m512 ratio_b_vec = _mm512_mul_ps(b_vec, m_recip_approx);
-
-        // The natural logarithm is equivalent to `log2`, multiplied by the `loge(2)`
-        __m512 log_ratio_a_vec = simsimd_avx512_f32_log2(ratio_a_vec);
-        __m512 log_ratio_b_vec = simsimd_avx512_f32_log2(ratio_b_vec);
-
-        // Instead of separate multiplication and addition, invoke the FMA
-        sum_a_vec = _mm512_maskz_fmadd_ps(nonzero_mask, a_vec, log_ratio_a_vec, sum_a_vec);
-        sum_b_vec = _mm512_maskz_fmadd_ps(nonzero_mask, b_vec, log_ratio_b_vec, sum_b_vec);
+    __m512 a_vec, b_vec;
+
+simsimd_avx512_f32_js_cycle:
+    if (n < 16) {
+        __mmask16 mask = _bzhi_u32(0xFFFFFFFF, n);
+        a_vec = _mm512_maskz_loadu_ps(mask, a);
+        b_vec = _mm512_maskz_loadu_ps(mask, b);
+        n = 0;
+    } else {
+        a_vec = _mm512_loadu_ps(a);
+        b_vec = _mm512_loadu_ps(b);
+        a += 16, b += 16, n -= 16;
     }
+    __m512 m_vec = _mm512_mul_ps(_mm512_add_ps(a_vec, b_vec), _mm512_set1_ps(0.5f));
+    __mmask16 nonzero_mask_a = _mm512_cmp_ps_mask(a_vec, epsilon_vec, _CMP_GE_OQ);
+    __mmask16 nonzero_mask_b = _mm512_cmp_ps_mask(b_vec, epsilon_vec, _CMP_GE_OQ);
+    __mmask16 nonzero_mask = nonzero_mask_a & nonzero_mask_b;
+    __m512 m_recip_approx = _mm512_rcp14_ps(m_vec);
+    __m512 ratio_a_vec = _mm512_mul_ps(a_vec, m_recip_approx);
+    __m512 ratio_b_vec = _mm512_mul_ps(b_vec, m_recip_approx);
+    __m512 log_ratio_a_vec = simsimd_avx512_f32_log2(ratio_a_vec);
+    __m512 log_ratio_b_vec = simsimd_avx512_f32_log2(ratio_b_vec);
+    sum_a_vec = _mm512_maskz_fmadd_ps(nonzero_mask, a_vec, log_ratio_a_vec, sum_a_vec);
+    sum_b_vec = _mm512_maskz_fmadd_ps(nonzero_mask, b_vec, log_ratio_b_vec, sum_b_vec);
+    if (n)
+        goto simsimd_avx512_f32_js_cycle;
+
     simsimd_f32_t log2_normalizer = 0.693147181f;
     return _mm512_reduce_add_ps(_mm512_add_ps(sum_a_vec, sum_b_vec)) * 0.5f * log2_normalizer;
 }
@@ -456,56 +468,68 @@ simsimd_avx512_f16_log2(__m512h x) {
     return _mm512_add_ph(_mm512_mul_ph(p, _mm512_sub_ph(m, one)), e);
 }
 
-__attribute__((target("avx512f,avx512vl,avx512fp16"))) //
+__attribute__((target("avx512f,avx512vl,avx512fp16,bmi2"))) //
 inline static simsimd_f32_t
 simsimd_avx512_f16_kl(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n) {
     __m512h sum_vec = _mm512_set1_ph((_Float16)0);
     __m512h epsilon_vec = _mm512_set1_ph((_Float16)1e-6f);
-    for (simsimd_size_t i = 0; i < n; i += 32) {
-        __mmask32 mask = n - i >= 32 ? 0xFFFFFFFF : ((1u << (n - i)) - 1u);
-        __m512h a_vec = _mm512_add_ph(_mm512_castsi512_ph(_mm512_maskz_loadu_epi16(mask, a + i)), epsilon_vec);
-        __m512h b_vec = _mm512_add_ph(_mm512_castsi512_ph(_mm512_maskz_loadu_epi16(mask, b + i)), epsilon_vec);
-        __m512h ratio_vec = _mm512_div_ph(a_vec, b_vec);
-        __m512h log_ratio_vec = simsimd_avx512_f16_log2(ratio_vec);
-        __m512h prod_vec = _mm512_mul_ph(a_vec, log_ratio_vec);
-        sum_vec = _mm512_maskz_add_ph(mask, sum_vec, prod_vec);
+    __m512h a_vec, b_vec;
+
+simsimd_avx512_f16_kl_cycle:
+    if (n < 32) {
+        __mmask32 mask = _bzhi_u32(0xFFFFFFFF, n);
+        a_vec = _mm512_maskz_add_ph(mask, _mm512_castsi512_ph(_mm512_maskz_loadu_epi16(mask, a)), epsilon_vec);
+        b_vec = _mm512_maskz_add_ph(mask, _mm512_castsi512_ph(_mm512_maskz_loadu_epi16(mask, b)), epsilon_vec);
+        n = 0;
+    } else {
+        a_vec = _mm512_add_ph(_mm512_castsi512_ph(_mm512_loadu_epi16(a)), epsilon_vec);
+        b_vec = _mm512_add_ph(_mm512_castsi512_ph(_mm512_loadu_epi16(b)), epsilon_vec);
+        a += 32, b += 32, n -= 32;
     }
+    __m512h ratio_vec = _mm512_div_ph(a_vec, b_vec);
+    __m512h log_ratio_vec = simsimd_avx512_f16_log2(ratio_vec);
+    __m512h prod_vec = _mm512_mul_ph(a_vec, log_ratio_vec);
+    sum_vec = _mm512_add_ph(sum_vec, prod_vec);
+    if (n)
+        goto simsimd_avx512_f16_kl_cycle;
+
     simsimd_f32_t log2_normalizer = 0.693147181f;
     return _mm512_reduce_add_ph(sum_vec) * log2_normalizer;
 }
 
-__attribute__((target("avx512f,avx512vl,avx512fp16"))) //
+__attribute__((target("avx512f,avx512vl,avx512fp16,bmi2"))) //
 inline static simsimd_f32_t
 simsimd_avx512_f16_js(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n) {
     __m512h sum_a_vec = _mm512_set1_ph((_Float16)0);
     __m512h sum_b_vec = _mm512_set1_ph((_Float16)0);
     __m512h epsilon_vec = _mm512_set1_ph((_Float16)1e-6f);
-    for (simsimd_size_t i = 0; i < n; i += 32) {
-        __mmask32 mask = n - i >= 32 ? 0xFFFFFFFF : ((1u << (n - i)) - 1u);
-        __m512h a_vec = _mm512_castsi512_ph(_mm512_maskz_loadu_epi16(mask, a + i));
-        __m512h b_vec = _mm512_castsi512_ph(_mm512_maskz_loadu_epi16(mask, b + i));
-        __m512h m_vec = _mm512_mul_ph(_mm512_add_ph(a_vec, b_vec), _mm512_set1_ph((_Float16)0.5f)); // M = (P + Q) / 2
-
-        // Avoid division by zero problems from probabilities under zero down the road.
-        // Masking is a nicer way to do this, than adding the `epsilon` to every component.
-        __mmask32 nonzero_mask_a = _mm512_cmp_ph_mask(a_vec, epsilon_vec, _CMP_GE_OQ);
-        __mmask32 nonzero_mask_b = _mm512_cmp_ph_mask(b_vec, epsilon_vec, _CMP_GE_OQ);
-        __mmask32 nonzero_mask = nonzero_mask_a & nonzero_mask_b & mask;
-
-        // Division is an expensive operation. Instead of doing it twice,
-        // we can approximate the reciprocal of `m` and multiply instead.
-        __m512h m_recip_approx = _mm512_rcp_ph(m_vec);
-        __m512h ratio_a_vec = _mm512_mul_ph(a_vec, m_recip_approx);
-        __m512h ratio_b_vec = _mm512_mul_ph(b_vec, m_recip_approx);
-
-        // The natural logarithm is equivalent to `log2`, multiplied by the `loge(2)`
-        __m512h log_ratio_a_vec = simsimd_avx512_f16_log2(ratio_a_vec);
-        __m512h log_ratio_b_vec = simsimd_avx512_f16_log2(ratio_b_vec);
-
-        // Instead of separate multiplication and addition, invoke the FMA
-        sum_a_vec = _mm512_maskz_fmadd_ph(nonzero_mask, a_vec, log_ratio_a_vec, sum_a_vec);
-        sum_b_vec = _mm512_maskz_fmadd_ph(nonzero_mask, b_vec, log_ratio_b_vec, sum_b_vec);
+    __m512h a_vec, b_vec;
+
+simsimd_avx512_f16_js_cycle:
+    if (n < 32) {
+        __mmask32 mask = _bzhi_u32(0xFFFFFFFF, n);
+        a_vec = _mm512_castsi512_ph(_mm512_maskz_loadu_epi16(mask, a));
+        b_vec = _mm512_castsi512_ph(_mm512_maskz_loadu_epi16(mask, b));
+        n = 0;
+    } else {
+        a_vec = _mm512_castsi512_ph(_mm512_loadu_epi16(a));
+        b_vec = _mm512_castsi512_ph(_mm512_loadu_epi16(b));
+        a += 32, b += 32, n -= 32;
     }
+    __m512h m_vec = _mm512_mul_ph(_mm512_add_ph(a_vec, b_vec), _mm512_set1_ph((_Float16)0.5f));
+    __mmask32 nonzero_mask_a = _mm512_cmp_ph_mask(a_vec, epsilon_vec, _CMP_GE_OQ);
+    __mmask32 nonzero_mask_b = _mm512_cmp_ph_mask(b_vec, epsilon_vec, _CMP_GE_OQ);
+    __mmask32 nonzero_mask = nonzero_mask_a & nonzero_mask_b;
+    __m512h m_recip_approx = _mm512_rcp_ph(m_vec);
+    __m512h ratio_a_vec = _mm512_mul_ph(a_vec, m_recip_approx);
+    __m512h ratio_b_vec = _mm512_mul_ph(b_vec, m_recip_approx);
+    __m512h log_ratio_a_vec = simsimd_avx512_f16_log2(ratio_a_vec);
+    __m512h log_ratio_b_vec = simsimd_avx512_f16_log2(ratio_b_vec);
+    sum_a_vec = _mm512_maskz_fmadd_ph(nonzero_mask, a_vec, log_ratio_a_vec, sum_a_vec);
+    sum_b_vec = _mm512_maskz_fmadd_ph(nonzero_mask, b_vec, log_ratio_b_vec, sum_b_vec);
+    if (n)
+        goto simsimd_avx512_f16_js_cycle;
+
     simsimd_f32_t log2_normalizer = 0.693147181f;
     return _mm512_reduce_add_ph(_mm512_add_ph(sum_a_vec, sum_b_vec)) * 0.5f * log2_normalizer;
 }

package/simsimd/include/simsimd/simsimd.h

@@ -74,6 +74,7 @@ typedef enum {
     simsimd_cap_x86_avx2fp16_k = 1 << 22,        ///< x86 AVX2 with FP16 capability
     simsimd_cap_x86_avx512fp16_k = 1 << 23,      ///< x86 AVX512 with FP16 capability
     simsimd_cap_x86_avx512vpopcntdq_k = 1 << 24, ///< x86 AVX512 VPOPCNTDQ instruction capability
+    simsimd_cap_x86_avx512vnni_k = 1 << 25,      ///< x86 AVX512 VNNI instruction capability
 
 } simsimd_capability_t;
 
@@ -112,42 +113,50 @@ inline static simsimd_capability_t simsimd_capabilities() {
     /// The states of 4 registers populated for a specific "cpuid" assmebly call
     union four_registers_t {
         int array[4];
-        struct {
+        struct separate_t {
             unsigned eax, ebx, ecx, edx;
-        };
+        } named;
     } info1, info7;
 
 #ifdef _MSC_VER
     __cpuidex(info1.array, 1, 0);
     __cpuidex(info7.array, 7, 0);
 #else
-    __asm__ __volatile__("cpuid" : "=a"(info1.eax), "=b"(info1.ebx), "=c"(info1.ecx), "=d"(info1.edx) : "a"(1), "c"(0));
-    __asm__ __volatile__("cpuid" : "=a"(info7.eax), "=b"(info7.ebx), "=c"(info7.ecx), "=d"(info7.edx) : "a"(7), "c"(0));
+    __asm__ __volatile__("cpuid"
+                         : "=a"(info1.named.eax), "=b"(info1.named.ebx), "=c"(info1.named.ecx), "=d"(info1.named.edx)
+                         : "a"(1), "c"(0));
+    __asm__ __volatile__("cpuid"
+                         : "=a"(info7.named.eax), "=b"(info7.named.ebx), "=c"(info7.named.ecx), "=d"(info7.named.edx)
+                         : "a"(7), "c"(0));
 #endif
 
     // Check for AVX2 (Function ID 7, EBX register)
     // https://github.com/llvm/llvm-project/blob/50598f0ff44f3a4e75706f8c53f3380fe7faa896/clang/lib/Headers/cpuid.h#L148
-    unsigned supports_avx2 = (info7.ebx & 0x00000020) != 0;
+    unsigned supports_avx2 = (info7.named.ebx & 0x00000020) != 0;
     // Check for F16C (Function ID 1, ECX register)
     // https://github.com/llvm/llvm-project/blob/50598f0ff44f3a4e75706f8c53f3380fe7faa896/clang/lib/Headers/cpuid.h#L107
-    unsigned supports_f16c = (info1.ecx & 0x20000000) != 0;
+    unsigned supports_f16c = (info1.named.ecx & 0x20000000) != 0;
     // Check for AVX512F (Function ID 7, EBX register)
     // https://github.com/llvm/llvm-project/blob/50598f0ff44f3a4e75706f8c53f3380fe7faa896/clang/lib/Headers/cpuid.h#L155
-    unsigned supports_avx512f = (info7.ebx & 0x00010000) != 0;
+    unsigned supports_avx512f = (info7.named.ebx & 0x00010000) != 0;
     // Check for AVX512FP16 (Function ID 7, EDX register)
     // https://github.com/llvm/llvm-project/blob/50598f0ff44f3a4e75706f8c53f3380fe7faa896/clang/lib/Headers/cpuid.h#L198C9-L198C23
-    unsigned supports_avx512fp16 = (info7.edx & 0x00800000) != 0;
+    unsigned supports_avx512fp16 = (info7.named.edx & 0x00800000) != 0;
     // Check for VPOPCNTDQ (Function ID 1, ECX register)
     // https://github.com/llvm/llvm-project/blob/50598f0ff44f3a4e75706f8c53f3380fe7faa896/clang/lib/Headers/cpuid.h#L182C30-L182C40
-    unsigned supports_avx512vpopcntdq = (info1.ecx & 0x00004000) != 0;
-
-    return (simsimd_capability_t)(                                                                   //
-        (simsimd_cap_x86_avx2_k * supports_avx2) |                                                   //
-        (simsimd_cap_x86_avx512_k * supports_avx512f) |                                              //
-        (simsimd_cap_x86_avx2fp16_k * (supports_avx2 && supports_f16c)) |                            //
-        (simsimd_cap_x86_avx512fp16_k * (supports_avx512fp16 && supports_avx512f)) |                 //
-        (simsimd_cap_x86_avx512vpopcntdq_k * (supports_avx512vpopcntdq && supports_avx512vpopcntdq)) //
-        | (simsimd_cap_serial_k));
+    unsigned supports_avx512vpopcntdq = (info1.named.ecx & 0x00004000) != 0;
+    // Check for VNNI (Function ID 1, ECX register)
+    // https://github.com/llvm/llvm-project/blob/50598f0ff44f3a4e75706f8c53f3380fe7faa896/clang/lib/Headers/cpuid.h#L180
+    unsigned supports_avx512vnni = (info1.named.ecx & 0x00000800) != 0;
+
+    return (simsimd_capability_t)(                                                   //
+        (simsimd_cap_x86_avx2_k * supports_avx2) |                                   //
+        (simsimd_cap_x86_avx512_k * supports_avx512f) |                              //
+        (simsimd_cap_x86_avx2fp16_k * (supports_avx2 && supports_f16c)) |            //
+        (simsimd_cap_x86_avx512fp16_k * (supports_avx512fp16 && supports_avx512f)) | //
+        (simsimd_cap_x86_avx512vpopcntdq_k * (supports_avx512vpopcntdq)) |           //
+        (simsimd_cap_x86_avx512vnni_k * (supports_avx512vnni)) |                     //
+        (simsimd_cap_serial_k));
 
 #endif // SIMSIMD_TARGET_X86
 
@@ -319,11 +328,11 @@ inline static void simsimd_find_metric_punned( //
             }
     #endif
     #if SIMSIMD_TARGET_X86_AVX512
-        if (viable & simsimd_cap_x86_avx512_k)
+        if (viable & simsimd_cap_x86_avx512vnni_k)
             switch (kind) {
-            case simsimd_metric_ip_k: *m = (simsimd_metric_punned_t)&simsimd_avx512_i8_ip, *c = simsimd_cap_x86_avx512_k; return;
-            case simsimd_metric_cos_k: *m = (simsimd_metric_punned_t)&simsimd_avx512_i8_cos, *c = simsimd_cap_x86_avx512_k; return;
-            case simsimd_metric_l2sq_k: *m = (simsimd_metric_punned_t)&simsimd_avx512_i8_l2sq, *c = simsimd_cap_x86_avx512_k; return;
+            case simsimd_metric_ip_k: *m = (simsimd_metric_punned_t)&simsimd_avx512_i8_ip, *c = simsimd_cap_x86_avx512vnni_k; return;
+            case simsimd_metric_cos_k: *m = (simsimd_metric_punned_t)&simsimd_avx512_i8_cos, *c = simsimd_cap_x86_avx512vnni_k; return;
+            case simsimd_metric_l2sq_k: *m = (simsimd_metric_punned_t)&simsimd_avx512_i8_l2sq, *c = simsimd_cap_x86_avx512vnni_k; return;
             default: break;
             }
     #endif