usearch 2.15.3 → 2.16.1

package/simsimd/include/simsimd/types.h

@@ -6,18 +6,19 @@
  *
  *  Defines:
  *  - Sized aliases for numeric types, like: `simsimd_i32_t` and `simsimd_f64_t`.
- *  - Macros for compiler/hardware checks, like: `SIMSIMD_TARGET_NEON`
+ *  - Macros for internal compiler/hardware checks, like: `_SIMSIMD_TARGET_ARM`.
+ *  - Macros for feature controls, like: `SIMSIMD_TARGET_NEON`
  */
 #ifndef SIMSIMD_TYPES_H
 #define SIMSIMD_TYPES_H
 
 // Inferring target OS: Windows, MacOS, or Linux
 #if defined(WIN32) || defined(_WIN32) || defined(__WIN32__) || defined(__NT__)
-#define SIMSIMD_DEFINED_WINDOWS
+#define _SIMSIMD_DEFINED_WINDOWS 1
 #elif defined(__APPLE__) && defined(__MACH__)
-#define SIMSIMD_DEFINED_APPLE
+#define _SIMSIMD_DEFINED_APPLE 1
 #elif defined(__linux__)
-#define SIMSIMD_DEFINED_LINUX
+#define _SIMSIMD_DEFINED_LINUX 1
 #endif
 
 // Annotation for the public API symbols:
@@ -40,73 +41,113 @@
 #define SIMSIMD_INTERNAL inline static
 #endif
 
-// Compiling for Arm: SIMSIMD_TARGET_ARM
-#if !defined(SIMSIMD_TARGET_ARM)
+// Compiling for Arm: _SIMSIMD_TARGET_ARM
+#if !defined(_SIMSIMD_TARGET_ARM)
 #if defined(__aarch64__) || defined(_M_ARM64)
-#define SIMSIMD_TARGET_ARM 1
+#define _SIMSIMD_TARGET_ARM 1
 #else
-#define SIMSIMD_TARGET_ARM 0
+#define _SIMSIMD_TARGET_ARM 0
 #endif // defined(__aarch64__) || defined(_M_ARM64)
-#endif // !defined(SIMSIMD_TARGET_ARM)
+#endif // !defined(_SIMSIMD_TARGET_ARM)
 
-// Compiling for x86: SIMSIMD_TARGET_X86
-#if !defined(SIMSIMD_TARGET_X86)
+// Compiling for x86: _SIMSIMD_TARGET_X86
+#if !defined(_SIMSIMD_TARGET_X86)
 #if defined(__x86_64__) || defined(_M_X64)
-#define SIMSIMD_TARGET_X86 1
+#define _SIMSIMD_TARGET_X86 1
 #else
-#define SIMSIMD_TARGET_X86 0
+#define _SIMSIMD_TARGET_X86 0
 #endif // defined(__x86_64__) || defined(_M_X64)
-#endif // !defined(SIMSIMD_TARGET_X86)
+#endif // !defined(_SIMSIMD_TARGET_X86)
 
 // Compiling for Arm: SIMSIMD_TARGET_NEON
-#if !defined(SIMSIMD_TARGET_NEON) || (SIMSIMD_TARGET_NEON && !SIMSIMD_TARGET_ARM)
+#if !defined(SIMSIMD_TARGET_NEON) || (SIMSIMD_TARGET_NEON && !_SIMSIMD_TARGET_ARM)
 #if defined(__ARM_NEON)
-#define SIMSIMD_TARGET_NEON SIMSIMD_TARGET_ARM
+#define SIMSIMD_TARGET_NEON _SIMSIMD_TARGET_ARM
 #else
 #undef SIMSIMD_TARGET_NEON
 #define SIMSIMD_TARGET_NEON 0
 #endif // defined(__ARM_NEON)
-#endif // !defined(SIMSIMD_TARGET_NEON)
-
-#if !defined(SIMSIMD_TARGET_NEON_I8)
-#define SIMSIMD_TARGET_NEON_I8 SIMSIMD_TARGET_NEON
-#endif // !defined(SIMSIMD_TARGET_NEON_I8)
-#if !defined(SIMSIMD_TARGET_NEON_F16)
-#define SIMSIMD_TARGET_NEON_F16 SIMSIMD_TARGET_NEON
-#endif // !defined(SIMSIMD_TARGET_NEON_F16)
-#if !defined(SIMSIMD_TARGET_NEON_BF16)
-#define SIMSIMD_TARGET_NEON_BF16 SIMSIMD_TARGET_NEON
-#endif // !defined(SIMSIMD_TARGET_NEON_BF16)
+#endif // !defined(SIMSIMD_TARGET_NEON) || ...
+
+// Compiling for Arm: SIMSIMD_TARGET_NEON_I8
+#if !defined(SIMSIMD_TARGET_NEON_I8) || (SIMSIMD_TARGET_NEON_I8 && !_SIMSIMD_TARGET_ARM)
+#if defined(__ARM_NEON)
+#define SIMSIMD_TARGET_NEON_I8 _SIMSIMD_TARGET_ARM
+#else
+#undef SIMSIMD_TARGET_NEON_I8
+#define SIMSIMD_TARGET_NEON_I8 0
+#endif // defined(__ARM_NEON)
+#endif // !defined(SIMSIMD_TARGET_NEON_I8) || ...
+
+// Compiling for Arm: SIMSIMD_TARGET_NEON_F16
+#if !defined(SIMSIMD_TARGET_NEON_F16) || (SIMSIMD_TARGET_NEON_F16 && !_SIMSIMD_TARGET_ARM)
+#if defined(__ARM_NEON)
+#define SIMSIMD_TARGET_NEON_F16 _SIMSIMD_TARGET_ARM
+#else
+#undef SIMSIMD_TARGET_NEON_F16
+#define SIMSIMD_TARGET_NEON_F16 0
+#endif // defined(__ARM_NEON)
+#endif // !defined(SIMSIMD_TARGET_NEON_F16) || ...
+
+// Compiling for Arm: SIMSIMD_TARGET_NEON_BF16
+#if !defined(SIMSIMD_TARGET_NEON_BF16) || (SIMSIMD_TARGET_NEON_BF16 && !_SIMSIMD_TARGET_ARM)
+#if defined(__ARM_NEON)
+#define SIMSIMD_TARGET_NEON_BF16 _SIMSIMD_TARGET_ARM
+#else
+#undef SIMSIMD_TARGET_NEON_BF16
+#define SIMSIMD_TARGET_NEON_BF16 0
+#endif // defined(__ARM_NEON)
+#endif // !defined(SIMSIMD_TARGET_NEON_BF16) || ...
 
 // Compiling for Arm: SIMSIMD_TARGET_SVE
-#if !defined(SIMSIMD_TARGET_SVE) || (SIMSIMD_TARGET_SVE && !SIMSIMD_TARGET_ARM)
+#if !defined(SIMSIMD_TARGET_SVE) || (SIMSIMD_TARGET_SVE && !_SIMSIMD_TARGET_ARM)
 #if defined(__ARM_FEATURE_SVE)
-#define SIMSIMD_TARGET_SVE SIMSIMD_TARGET_ARM
+#define SIMSIMD_TARGET_SVE _SIMSIMD_TARGET_ARM
 #else
 #undef SIMSIMD_TARGET_SVE
 #define SIMSIMD_TARGET_SVE 0
 #endif // defined(__ARM_FEATURE_SVE)
-#endif // !defined(SIMSIMD_TARGET_SVE)
-
-#if !defined(SIMSIMD_TARGET_SVE_I8)
-#define SIMSIMD_TARGET_SVE_I8 SIMSIMD_TARGET_SVE
-#endif // !defined(SIMSIMD_TARGET_SVE_I8)
-#if !defined(SIMSIMD_TARGET_SVE_F16)
-#define SIMSIMD_TARGET_SVE_F16 SIMSIMD_TARGET_SVE
-#endif // !defined(SIMSIMD_TARGET_SVE_F16)
-#if !defined(SIMSIMD_TARGET_SVE_BF16)
-#define SIMSIMD_TARGET_SVE_BF16 SIMSIMD_TARGET_SVE
-#endif // !defined(SIMSIMD_TARGET_SVE_BF16)
+#endif // !defined(SIMSIMD_TARGET_SVE) || ...
+
+// Compiling for Arm: SIMSIMD_TARGET_SVE_I8
+#if !defined(SIMSIMD_TARGET_SVE_I8) || (SIMSIMD_TARGET_SVE_I8 && !_SIMSIMD_TARGET_ARM)
+#if defined(__ARM_FEATURE_SVE)
+#define SIMSIMD_TARGET_SVE_I8 _SIMSIMD_TARGET_ARM
+#else
+#undef SIMSIMD_TARGET_SVE_I8
+#define SIMSIMD_TARGET_SVE_I8 0
+#endif // defined(__ARM_FEATURE_SVE)
+#endif // !defined(SIMSIMD_TARGET_SVE_I8) || ...
+
+// Compiling for Arm: SIMSIMD_TARGET_SVE_F16
+#if !defined(SIMSIMD_TARGET_SVE_F16) || (SIMSIMD_TARGET_SVE_F16 && !_SIMSIMD_TARGET_ARM)
+#if defined(__ARM_FEATURE_SVE)
+#define SIMSIMD_TARGET_SVE_F16 _SIMSIMD_TARGET_ARM
+#else
+#undef SIMSIMD_TARGET_SVE_F16
+#define SIMSIMD_TARGET_SVE_F16 0
+#endif // defined(__ARM_FEATURE_SVE)
+#endif // !defined(SIMSIMD_TARGET_SVE_F16) || ...
+
+// Compiling for Arm: SIMSIMD_TARGET_SVE_BF16
+#if !defined(SIMSIMD_TARGET_SVE_BF16) || (SIMSIMD_TARGET_SVE_BF16 && !_SIMSIMD_TARGET_ARM)
+#if defined(__ARM_FEATURE_SVE)
+#define SIMSIMD_TARGET_SVE_BF16 _SIMSIMD_TARGET_ARM
+#else
+#undef SIMSIMD_TARGET_SVE_BF16
+#define SIMSIMD_TARGET_SVE_BF16 0
+#endif // defined(__ARM_FEATURE_SVE)
+#endif // !defined(SIMSIMD_TARGET_SVE_BF16) || ...
 
 // Compiling for Arm: SIMSIMD_TARGET_SVE2
-#if !defined(SIMSIMD_TARGET_SVE2) || (SIMSIMD_TARGET_SVE2 && !SIMSIMD_TARGET_ARM)
+#if !defined(SIMSIMD_TARGET_SVE2) || (SIMSIMD_TARGET_SVE2 && !_SIMSIMD_TARGET_ARM)
 #if defined(__ARM_FEATURE_SVE)
-#define SIMSIMD_TARGET_SVE2 SIMSIMD_TARGET_ARM
+#define SIMSIMD_TARGET_SVE2 _SIMSIMD_TARGET_ARM
 #else
 #undef SIMSIMD_TARGET_SVE2
 #define SIMSIMD_TARGET_SVE2 0
 #endif // defined(__ARM_FEATURE_SVE)
-#endif // !defined(SIMSIMD_TARGET_SVE2)
+#endif // !defined(SIMSIMD_TARGET_SVE2) || ...
 
 // Compiling for x86: SIMSIMD_TARGET_HASWELL
 //
@@ -115,55 +156,72 @@
 // are supported on all CPUs starting with Jaguar 2009.
 // Starting with Sandy Bridge, Intel adds basic AVX support in their CPUs and in 2013
 // extends it with AVX2 in the Haswell generation. Moreover, Haswell adds FMA support.
-#if !defined(SIMSIMD_TARGET_HASWELL) || (SIMSIMD_TARGET_HASWELL && !SIMSIMD_TARGET_X86)
+#if !defined(SIMSIMD_TARGET_HASWELL) || (SIMSIMD_TARGET_HASWELL && !_SIMSIMD_TARGET_X86)
 #if defined(__AVX2__) && defined(__FMA__) && defined(__F16C__)
 #define SIMSIMD_TARGET_HASWELL 1
 #else
 #undef SIMSIMD_TARGET_HASWELL
 #define SIMSIMD_TARGET_HASWELL 0
 #endif // defined(__AVX2__)
-#endif // !defined(SIMSIMD_TARGET_HASWELL)
+#endif // !defined(SIMSIMD_TARGET_HASWELL) || ...
 
-// Compiling for x86: SIMSIMD_TARGET_SKYLAKE, SIMSIMD_TARGET_ICE, SIMSIMD_TARGET_GENOA, SIMSIMD_TARGET_SAPPHIRE
+// Compiling for x86: SIMSIMD_TARGET_SKYLAKE, SIMSIMD_TARGET_ICE, SIMSIMD_TARGET_GENOA,
+// SIMSIMD_TARGET_SAPPHIRE, SIMSIMD_TARGET_TURIN, SIMSIMD_TARGET_SIERRA
 //
 // To list all available macros for x86, take a recent compiler, like GCC 12 and run:
 //      gcc-12 -march=sapphirerapids -dM -E - < /dev/null | egrep "SSE|AVX" | sort
 // On Arm machines you may want to check for other flags:
 //      gcc-12 -march=native -dM -E - < /dev/null | egrep "NEON|SVE|FP16|FMA" | sort
-#if !defined(SIMSIMD_TARGET_SKYLAKE) || (SIMSIMD_TARGET_SKYLAKE && !SIMSIMD_TARGET_X86)
-#if defined(__AVX512F__) && defined(__AVX512CD__) && defined(__AVX512VL__) && defined(__AVX512DQ__) &&                 \
+#if !defined(SIMSIMD_TARGET_SKYLAKE) || (SIMSIMD_TARGET_SKYLAKE && !_SIMSIMD_TARGET_X86)
+#if defined(__AVX512F__) && defined(__AVX512CD__) && defined(__AVX512VL__) && defined(__AVX512DQ__) && \
     defined(__AVX512BW__)
 #define SIMSIMD_TARGET_SKYLAKE 1
 #else
 #undef SIMSIMD_TARGET_SKYLAKE
 #define SIMSIMD_TARGET_SKYLAKE 0
 #endif
-#endif // !defined(SIMSIMD_TARGET_SKYLAKE)
-#if !defined(SIMSIMD_TARGET_ICE) || (SIMSIMD_TARGET_ICE && !SIMSIMD_TARGET_X86)
-#if defined(__AVX512VNNI__) && defined(__AVX512IFMA__) && defined(__AVX512BITALG__) && defined(__AVX512VBMI2__) &&     \
+#endif // !defined(SIMSIMD_TARGET_SKYLAKE) || ...
+#if !defined(SIMSIMD_TARGET_ICE) || (SIMSIMD_TARGET_ICE && !_SIMSIMD_TARGET_X86)
+#if defined(__AVX512VNNI__) && defined(__AVX512IFMA__) && defined(__AVX512BITALG__) && defined(__AVX512VBMI2__) && \
     defined(__AVX512VPOPCNTDQ__)
 #define SIMSIMD_TARGET_ICE 1
 #else
 #undef SIMSIMD_TARGET_ICE
 #define SIMSIMD_TARGET_ICE 0
 #endif
-#endif // !defined(SIMSIMD_TARGET_ICE)
-#if !defined(SIMSIMD_TARGET_GENOA) || (SIMSIMD_TARGET_GENOA && !SIMSIMD_TARGET_X86)
+#endif // !defined(SIMSIMD_TARGET_ICE) || ...
+#if !defined(SIMSIMD_TARGET_GENOA) || (SIMSIMD_TARGET_GENOA && !_SIMSIMD_TARGET_X86)
 #if defined(__AVX512BF16__)
 #define SIMSIMD_TARGET_GENOA 1
 #else
 #undef SIMSIMD_TARGET_GENOA
 #define SIMSIMD_TARGET_GENOA 0
 #endif
-#endif // !defined(SIMSIMD_TARGET_GENOA)
-#if !defined(SIMSIMD_TARGET_SAPPHIRE) || (SIMSIMD_TARGET_SAPPHIRE && !SIMSIMD_TARGET_X86)
+#endif // !defined(SIMSIMD_TARGET_GENOA) || ...
+#if !defined(SIMSIMD_TARGET_SAPPHIRE) || (SIMSIMD_TARGET_SAPPHIRE && !_SIMSIMD_TARGET_X86)
 #if defined(__AVX512FP16__)
 #define SIMSIMD_TARGET_SAPPHIRE 1
 #else
 #undef SIMSIMD_TARGET_SAPPHIRE
 #define SIMSIMD_TARGET_SAPPHIRE 0
 #endif
-#endif // !defined(SIMSIMD_TARGET_SAPPHIRE)
+#endif // !defined(SIMSIMD_TARGET_SAPPHIRE) || ...
+#if !defined(SIMSIMD_TARGET_TURIN) || (SIMSIMD_TARGET_TURIN && !_SIMSIMD_TARGET_X86)
+#if defined(__AVX512VP2INTERSECT__)
+#define SIMSIMD_TARGET_TURIN 1
+#else
+#undef SIMSIMD_TARGET_TURIN
+#define SIMSIMD_TARGET_TURIN 0
+#endif
+#endif // !defined(SIMSIMD_TARGET_TURIN) || ...
+#if !defined(SIMSIMD_TARGET_SIERRA) || (SIMSIMD_TARGET_SIERRA && !_SIMSIMD_TARGET_X86)
+#if defined(__AVX2_VNNI__)
+#define SIMSIMD_TARGET_SIERRA 1
+#else
+#undef SIMSIMD_TARGET_SIERRA
+#define SIMSIMD_TARGET_SIERRA 0
+#endif
+#endif // !defined(SIMSIMD_TARGET_SIERRA) || ...
 
 #ifdef _MSC_VER
 #include <intrin.h>
@@ -177,8 +235,8 @@
 #include <arm_sve.h>
 #endif
 
-#if SIMSIMD_TARGET_HASWELL || SIMSIMD_TARGET_SKYLAKE || SIMSIMD_TARGET_ICE || SIMSIMD_TARGET_GENOA ||                  \
-    SIMSIMD_TARGET_SAPPHIRE
+#if SIMSIMD_TARGET_HASWELL || SIMSIMD_TARGET_SKYLAKE || SIMSIMD_TARGET_ICE || SIMSIMD_TARGET_GENOA || \
+    SIMSIMD_TARGET_SAPPHIRE || SIMSIMD_TARGET_TURIN
 #include <immintrin.h>
 #endif
 
@@ -212,6 +270,7 @@ extern "C" {
 #endif
 
 typedef unsigned char simsimd_b8_t;
+typedef unsigned char simsimd_i4x2_t;
 
 typedef signed char simsimd_i8_t;
 typedef unsigned char simsimd_u8_t;
@@ -235,12 +294,12 @@ typedef simsimd_f64_t simsimd_distance_t;
  *  - Default: `unsigned short`.
  */
 #if !defined(SIMSIMD_NATIVE_F16) || SIMSIMD_NATIVE_F16
-#if (defined(__GNUC__) || defined(__clang__)) && (defined(__ARM_ARCH) || defined(__aarch64__)) &&                      \
+#if (defined(__GNUC__) || defined(__clang__)) && (defined(__ARM_ARCH) || defined(__aarch64__)) && \
     (defined(__ARM_FP16_FORMAT_IEEE))
 #undef SIMSIMD_NATIVE_F16
 #define SIMSIMD_NATIVE_F16 1
 typedef __fp16 simsimd_f16_t;
-#elif ((defined(__GNUC__) || defined(__clang__)) && (defined(__x86_64__) || defined(__i386__)) &&                      \
+#elif ((defined(__GNUC__) || defined(__clang__)) && (defined(__x86_64__) || defined(__i386__)) && \
        (defined(__AVX512FP16__)))
 typedef _Float16 simsimd_f16_t;
 #undef SIMSIMD_NATIVE_F16
@@ -283,12 +342,12 @@ typedef unsigned short simsimd_f16_t;
  *  https://forums.developer.apple.com/forums/thread/726201
  *  https://www.phoronix.com/news/GCC-LLVM-bf16-BFloat16-Type
  */
-#if (defined(__GNUC__) || defined(__clang__)) && (defined(__ARM_ARCH) || defined(__aarch64__)) &&                      \
+#if (defined(__GNUC__) || defined(__clang__)) && (defined(__ARM_ARCH) || defined(__aarch64__)) && \
     (defined(__ARM_BF16_FORMAT_ALTERNATIVE))
 #undef SIMSIMD_NATIVE_BF16
 #define SIMSIMD_NATIVE_BF16 1
 typedef __bf16 simsimd_bf16_t;
-#elif ((defined(__GNUC__) || defined(__clang__)) && (defined(__x86_64__) || defined(__i386__)) &&                      \
+#elif ((defined(__GNUC__) || defined(__clang__)) && (defined(__x86_64__) || defined(__i386__)) && \
        (defined(__AVX512BF16__)))
 typedef __bfloat16 simsimd_bf16_t;
 #undef SIMSIMD_NATIVE_BF16
@@ -315,7 +374,7 @@ typedef unsigned short simsimd_bf16_t;
  *  Some of those are defined as aliases, so we use `#define` preprocessor
  *  directives instead of `typedef` to avoid errors.
  */
-#if SIMSIMD_TARGET_ARM
+#if _SIMSIMD_TARGET_ARM
 #if defined(_MSC_VER)
 #define simsimd_f16_for_arm_simd_t simsimd_f16_t
 #define simsimd_bf16_for_arm_simd_t simsimd_bf16_t
@@ -330,6 +389,8 @@ typedef unsigned short simsimd_bf16_t;
  *  In C the `_Static_assert` is only available with C 11 and later.
  */
 #define SIMSIMD_STATIC_ASSERT(cond, msg) typedef char static_assertion_##msg[(cond) ? 1 : -1]
+SIMSIMD_STATIC_ASSERT(sizeof(simsimd_b8_t) == 1, simsimd_b8_t_must_be_1_byte);
+SIMSIMD_STATIC_ASSERT(sizeof(simsimd_i4x2_t) == 1, simsimd_i4x2_t_must_be_1_byte);
 SIMSIMD_STATIC_ASSERT(sizeof(simsimd_i8_t) == 1, simsimd_i8_t_must_be_1_byte);
 SIMSIMD_STATIC_ASSERT(sizeof(simsimd_u8_t) == 1, simsimd_u8_t_must_be_1_byte);
 SIMSIMD_STATIC_ASSERT(sizeof(simsimd_i16_t) == 2, simsimd_i16_t_must_be_2_bytes);
@@ -374,6 +435,19 @@ SIMSIMD_STATIC_ASSERT(sizeof(simsimd_bf16_t) == 2, simsimd_bf16_t_must_be_2_byte
 #endif
 #endif
 
+#if !defined(SIMSIMD_F32_TO_I8)
+#define SIMSIMD_F32_TO_I8(x, y) *(y) = (simsimd_i8_t)fminf(fmaxf(roundf(x), -128), 127)
+#endif
+#if !defined(SIMSIMD_F32_TO_U8)
+#define SIMSIMD_F32_TO_U8(x, y) *(y) = (simsimd_u8_t)fminf(fmaxf(roundf(x), 0), 255)
+#endif
+#if !defined(SIMSIMD_F64_TO_I8)
+#define SIMSIMD_F64_TO_I8(x, y) *(y) = (simsimd_i8_t)fmin(fmax(round(x), -128), 127)
+#endif
+#if !defined(SIMSIMD_F64_TO_U8)
+#define SIMSIMD_F64_TO_U8(x, y) *(y) = (simsimd_u8_t)fmin(fmax(round(x), 0), 255)
+#endif
+
 /** @brief  Convenience type for half-precision floating-point type conversions. */
 typedef union {
     unsigned i;
@@ -423,8 +497,8 @@ SIMSIMD_PUBLIC simsimd_f32_t simsimd_approximate_log(simsimd_f32_t number) {
  *  https://gist.github.com/milhidaka/95863906fe828198f47991c813dbe233
  *  https://github.com/OpenCyphal/libcanard/blob/636795f4bc395f56af8d2c61d3757b5e762bb9e5/canard.c#L811-L834
  */
-SIMSIMD_PUBLIC simsimd_f32_t simsimd_f16_to_f32(simsimd_f16_t const* x_ptr) {
-    unsigned short x = *(unsigned short const*)x_ptr;
+SIMSIMD_PUBLIC simsimd_f32_t simsimd_f16_to_f32(simsimd_f16_t const *x_ptr) {
+    unsigned short x = *(unsigned short const *)x_ptr;
     unsigned int exponent = (x & 0x7C00) >> 10;
     unsigned int mantissa = (x & 0x03FF) << 13;
     simsimd_f32i32_t mantissa_conv;
@@ -445,7 +519,7 @@ SIMSIMD_PUBLIC simsimd_f32_t simsimd_f16_to_f32(simsimd_f16_t const* x_ptr) {
  *  https://gist.github.com/milhidaka/95863906fe828198f47991c813dbe233
  *  https://github.com/OpenCyphal/libcanard/blob/636795f4bc395f56af8d2c61d3757b5e762bb9e5/canard.c#L811-L834
  */
-SIMSIMD_PUBLIC void simsimd_f32_to_f16(simsimd_f32_t x, simsimd_f16_t* result_ptr) {
+SIMSIMD_PUBLIC void simsimd_f32_to_f16(simsimd_f32_t x, simsimd_f16_t *result_ptr) {
     simsimd_f32i32_t conv;
     conv.f = x;
     unsigned int b = conv.i + 0x00001000;
@@ -454,7 +528,7 @@ SIMSIMD_PUBLIC void simsimd_f32_to_f16(simsimd_f32_t x, simsimd_f16_t* result_pt
     unsigned short result = ((b & 0x80000000) >> 16) | (e > 112) * ((((e - 112) << 10) & 0x7C00) | (m >> 13)) |
                             ((e < 113) & (e > 101)) * ((((0x007FF000 + m) >> (125 - e)) + 1) >> 1) |
                             ((e > 143) * 0x7FFF);
-    *(unsigned short*)result_ptr = result;
+    *(unsigned short *)result_ptr = result;
 }
 
 /**
@@ -464,8 +538,8 @@ SIMSIMD_PUBLIC void simsimd_f32_to_f16(simsimd_f32_t x, simsimd_f16_t* result_pt
  *  https://stackoverflow.com/questions/55253233/convert-fp32-to-bfloat16-in-c/55254307#55254307
  *  https://cloud.google.com/blog/products/ai-machine-learning/bfloat16-the-secret-to-high-performance-on-cloud-tpus
  */
-SIMSIMD_PUBLIC simsimd_f32_t simsimd_bf16_to_f32(simsimd_bf16_t const* x_ptr) {
-    unsigned short x = *(unsigned short const*)x_ptr;
+SIMSIMD_PUBLIC simsimd_f32_t simsimd_bf16_to_f32(simsimd_bf16_t const *x_ptr) {
+    unsigned short x = *(unsigned short const *)x_ptr;
     simsimd_f32i32_t conv;
     conv.i = x << 16; // Zero extends the mantissa
     return conv.f;
@@ -477,14 +551,14 @@ SIMSIMD_PUBLIC simsimd_f32_t simsimd_bf16_to_f32(simsimd_bf16_t const* x_ptr) {
  *  https://stackoverflow.com/questions/55253233/convert-fp32-to-bfloat16-in-c/55254307#55254307
  *  https://cloud.google.com/blog/products/ai-machine-learning/bfloat16-the-secret-to-high-performance-on-cloud-tpus
  */
-SIMSIMD_PUBLIC void simsimd_f32_to_bf16(simsimd_f32_t x, simsimd_bf16_t* result_ptr) {
+SIMSIMD_PUBLIC void simsimd_f32_to_bf16(simsimd_f32_t x, simsimd_bf16_t *result_ptr) {
     simsimd_f32i32_t conv;
     conv.f = x;
     conv.i += 0x8000; // Rounding is optional
     conv.i >>= 16;
     // The top 16 bits will be zeroed out anyways
     // conv.i &= 0xFFFF;
-    *(unsigned short*)result_ptr = (unsigned short)conv.i;
+    *(unsigned short *)result_ptr = (unsigned short)conv.i;
 }
 
 SIMSIMD_PUBLIC simsimd_u32_t simsimd_u32_rol(simsimd_u32_t x, int n) { return (x << n) | (x >> (32 - n)); }

package/simsimd/javascript/lib.c

@@ -67,8 +67,7 @@ napi_value runAPI(napi_env env, napi_callback_info info, simsimd_metric_kind_t m
     // Convert the result to a JavaScript number
     napi_value js_result;
     status = napi_create_double(env, result, &js_result);
-    if (status != napi_ok)
-        return NULL;
+    if (status != napi_ok) return NULL;
 
     return js_result;
 }

package/simsimd/package.json

@@ -1,7 +1,7 @@
 {
   "name": "simsimd",
-  "version": "5.6.4",
-  "description": "Fastest SIMD-Accelerated Vector Similarity Functions for x86 and Arm",
+  "version": "5.9.6",
+  "description": "Portable mixed-precision BLAS-like vector math library for x86 and ARM",
   "homepage": "https://github.com/ashvardanian/simsimd",
   "author": "Ash Vardanian",
   "license": "Apache 2.0",
@@ -27,8 +27,8 @@
     "prebuild-arm64": "prebuildify --arch arm64 --napi --strip --target=10.4.0",
     "prebuild-darwin-x64+arm64": "prebuildify --arch arm64+x64 --napi --strip --target=10.4.0",
     "build-js": "rm -fr javascript/dist/* && tsc -p javascript/tsconfig-esm.json && tsc -p javascript/tsconfig-cjs.json && cp javascript/dist-package-esm.json javascript/dist/esm/package.json && cp javascript/dist-package-cjs.json javascript/dist/cjs/package.json",
-    "test": "node --test ./javascript/test.mjs",
-    "bench": "node ./javascript/bench.js"
+    "test": "node --test ./scripts/test.mjs",
+    "bench": "node ./scripts/bench.js"
   },
   "main": "javascript/dist/cjs/simsimd.js",
   "module": "javascript/dist/esm/simsimd.js",

package/simsimd/rust/lib.rs

@@ -106,6 +106,8 @@ extern "C" {
     fn simsimd_uses_ice() -> i32;
     fn simsimd_uses_genoa() -> i32;
     fn simsimd_uses_sapphire() -> i32;
+    fn simsimd_uses_turin() -> i32;
+    fn simsimd_uses_sierra() -> i32;
 }
 
 /// A half-precision floating point number.
@@ -175,6 +177,14 @@ pub mod capabilities {
     pub fn uses_sapphire() -> bool {
         unsafe { crate::simsimd_uses_sapphire() != 0 }
     }
+
+    pub fn uses_turin() -> bool {
+        unsafe { crate::simsimd_uses_turin() != 0 }
+    }
+
+    pub fn uses_sierra() -> bool {
+        unsafe { crate::simsimd_uses_sierra() != 0 }
+    }
 }
 
 /// `SpatialSimilarity` provides a set of trait methods for computing similarity
@@ -710,7 +720,8 @@ mod tests {
             || capabilities::uses_skylake()
             || capabilities::uses_ice()
             || capabilities::uses_genoa()
-            || capabilities::uses_sapphire();
+            || capabilities::uses_sapphire()
+            || capabilities::uses_turin();
 
         // The CPU can't simultaneously support ARM and x86 SIMD extensions
         if uses_arm {
@@ -727,6 +738,8 @@ mod tests {
         println!("- uses_ice: {}", capabilities::uses_ice());
         println!("- uses_genoa: {}", capabilities::uses_genoa());
         println!("- uses_sapphire: {}", capabilities::uses_sapphire());
+        println!("- uses_turin: {}", capabilities::uses_turin());
+        println!("- uses_sierra: {}", capabilities::uses_sierra());
     }
 
     //