usearch 2.15.2 → 2.15.3

package/simsimd/include/simsimd/dot.h

@@ -16,8 +16,8 @@
  *  - 8-bit signed integers
  *
  *  For hardware architectures:
- *  - Arm (NEON, SVE?)
- *  - x86 (AVX2?, AVX512?)
+ *  - Arm (NEON, SVE)
+ *  - x86 (AVX2, AVX512)
  *
  *  x86 intrinsics: https://www.intel.com/content/www/us/en/docs/intrinsics-guide/
  *  Arm intrinsics: https://developer.arm.com/architectures/instruction-sets/intrinsics/
@@ -82,7 +82,11 @@ SIMSIMD_PUBLIC void simsimd_dot_f16_neon(simsimd_f16_t const* a, simsimd_f16_t c
 SIMSIMD_PUBLIC void simsimd_dot_f16c_neon(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n, simsimd_distance_t* results);
 SIMSIMD_PUBLIC void simsimd_vdot_f16c_neon(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n, simsimd_distance_t* results);
 
-SIMSIMD_PUBLIC void simsimd_dot_i8_serial(simsimd_i8_t const* a, simsimd_i8_t const* b, simsimd_size_t n, simsimd_distance_t* result);
+SIMSIMD_PUBLIC void simsimd_dot_i8_neon(simsimd_i8_t const* a, simsimd_i8_t const* b, simsimd_size_t n, simsimd_distance_t* result);
+
+SIMSIMD_PUBLIC void simsimd_dot_bf16_neon(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n, simsimd_distance_t* result);
+SIMSIMD_PUBLIC void simsimd_dot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n, simsimd_distance_t* results);
+SIMSIMD_PUBLIC void simsimd_vdot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n, simsimd_distance_t* results);
 
 /*  SIMD-powered backends for Arm SVE, mostly using 32-bit arithmetic over variable-length platform-defined word sizes.
  *  Designed for Arm Graviton 3, Microsoft Cobalt, as well as Nvidia Grace and newer Ampere Altra CPUs.
@@ -131,7 +135,7 @@ SIMSIMD_PUBLIC void simsimd_dot_f32_skylake(simsimd_f32_t const* a, simsimd_f32_
 SIMSIMD_PUBLIC void simsimd_dot_f32c_skylake(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n, simsimd_distance_t* result);
 SIMSIMD_PUBLIC void simsimd_vdot_f32c_skylake(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n, simsimd_distance_t* result);
 
-SIMSIMD_PUBLIC void simsimd_dot_i8_ice(simsimd_i8_t const* a, simsimd_i8_t const* b, simsimd_size_t n, simsimd_distance_t*);
+SIMSIMD_PUBLIC void simsimd_dot_i8_ice(simsimd_i8_t const* a, simsimd_i8_t const* b, simsimd_size_t n, simsimd_distance_t* result);
 
 SIMSIMD_PUBLIC void simsimd_dot_bf16_genoa(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n, simsimd_distance_t* result);
 SIMSIMD_PUBLIC void simsimd_dot_bf16c_genoa(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n, simsimd_distance_t* result);
@@ -142,29 +146,29 @@ SIMSIMD_PUBLIC void simsimd_dot_f16c_sapphire(simsimd_f16_t const* a, simsimd_f1
 SIMSIMD_PUBLIC void simsimd_vdot_f16c_sapphire(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n, simsimd_distance_t* result);
 // clang-format on
 
-#define SIMSIMD_MAKE_DOT(name, input_type, accumulator_type, converter)                                                \
+#define SIMSIMD_MAKE_DOT(name, input_type, accumulator_type, load_and_convert)                                         \
     SIMSIMD_PUBLIC void simsimd_dot_##input_type##_##name(simsimd_##input_type##_t const* a,                           \
                                                           simsimd_##input_type##_t const* b, simsimd_size_t n,         \
                                                           simsimd_distance_t* result) {                                \
         simsimd_##accumulator_type##_t ab = 0;                                                                         \
         for (simsimd_size_t i = 0; i != n; ++i) {                                                                      \
-            simsimd_##accumulator_type##_t ai = converter(a[i]);                                                       \
-            simsimd_##accumulator_type##_t bi = converter(b[i]);                                                       \
+            simsimd_##accumulator_type##_t ai = load_and_convert(a + i);                                               \
+            simsimd_##accumulator_type##_t bi = load_and_convert(b + i);                                               \
             ab += ai * bi;                                                                                             \
         }                                                                                                              \
         *result = ab;                                                                                                  \
     }
 
-#define SIMSIMD_MAKE_COMPLEX_DOT(name, input_type, accumulator_type, converter)                                        \
+#define SIMSIMD_MAKE_COMPLEX_DOT(name, input_type, accumulator_type, load_and_convert)                                 \
     SIMSIMD_PUBLIC void simsimd_dot_##input_type##c_##name(simsimd_##input_type##_t const* a,                          \
                                                            simsimd_##input_type##_t const* b, simsimd_size_t n,        \
                                                            simsimd_distance_t* results) {                              \
         simsimd_##accumulator_type##_t ab_real = 0, ab_imag = 0;                                                       \
         for (simsimd_size_t i = 0; i + 2 <= n; i += 2) {                                                               \
-            simsimd_##accumulator_type##_t ar = converter(a[i]);                                                       \
-            simsimd_##accumulator_type##_t br = converter(b[i]);                                                       \
-            simsimd_##accumulator_type##_t ai = converter(a[i + 1]);                                                   \
-            simsimd_##accumulator_type##_t bi = converter(b[i + 1]);                                                   \
+            simsimd_##accumulator_type##_t ar = load_and_convert(a + i);                                               \
+            simsimd_##accumulator_type##_t br = load_and_convert(b + i);                                               \
+            simsimd_##accumulator_type##_t ai = load_and_convert(a + i + 1);                                           \
+            simsimd_##accumulator_type##_t bi = load_and_convert(b + i + 1);                                           \
             ab_real += ar * br - ai * bi;                                                                              \
             ab_imag += ar * bi + ai * br;                                                                              \
         }                                                                                                              \
@@ -172,16 +176,16 @@ SIMSIMD_PUBLIC void simsimd_vdot_f16c_sapphire(simsimd_f16_t const* a, simsimd_f
         results[1] = ab_imag;                                                                                          \
     }
 
-#define SIMSIMD_MAKE_COMPLEX_VDOT(name, input_type, accumulator_type, converter)                                       \
+#define SIMSIMD_MAKE_COMPLEX_VDOT(name, input_type, accumulator_type, load_and_convert)                                \
     SIMSIMD_PUBLIC void simsimd_vdot_##input_type##c_##name(simsimd_##input_type##_t const* a,                         \
                                                             simsimd_##input_type##_t const* b, simsimd_size_t n,       \
                                                             simsimd_distance_t* results) {                             \
         simsimd_##accumulator_type##_t ab_real = 0, ab_imag = 0;                                                       \
         for (simsimd_size_t i = 0; i + 2 <= n; i += 2) {                                                               \
-            simsimd_##accumulator_type##_t ar = converter(a[i]);                                                       \
-            simsimd_##accumulator_type##_t br = converter(b[i]);                                                       \
-            simsimd_##accumulator_type##_t ai = converter(a[i + 1]);                                                   \
-            simsimd_##accumulator_type##_t bi = converter(b[i + 1]);                                                   \
+            simsimd_##accumulator_type##_t ar = load_and_convert(a + i);                                               \
+            simsimd_##accumulator_type##_t br = load_and_convert(b + i);                                               \
+            simsimd_##accumulator_type##_t ai = load_and_convert(a + i + 1);                                           \
+            simsimd_##accumulator_type##_t bi = load_and_convert(b + i + 1);                                           \
             ab_real += ar * br + ai * bi;                                                                              \
             ab_imag += ar * bi - ai * br;                                                                              \
         }                                                                                                              \
@@ -189,41 +193,54 @@ SIMSIMD_PUBLIC void simsimd_vdot_f16c_sapphire(simsimd_f16_t const* a, simsimd_f
         results[1] = ab_imag;                                                                                          \
     }
 
-SIMSIMD_MAKE_DOT(serial, f64, f64, SIMSIMD_IDENTIFY)          // simsimd_dot_f64_serial
-SIMSIMD_MAKE_COMPLEX_DOT(serial, f64, f64, SIMSIMD_IDENTIFY)  // simsimd_dot_f64c_serial
-SIMSIMD_MAKE_COMPLEX_VDOT(serial, f64, f64, SIMSIMD_IDENTIFY) // simsimd_vdot_f64c_serial
+SIMSIMD_MAKE_DOT(serial, f64, f64, SIMSIMD_DEREFERENCE)          // simsimd_dot_f64_serial
+SIMSIMD_MAKE_COMPLEX_DOT(serial, f64, f64, SIMSIMD_DEREFERENCE)  // simsimd_dot_f64c_serial
+SIMSIMD_MAKE_COMPLEX_VDOT(serial, f64, f64, SIMSIMD_DEREFERENCE) // simsimd_vdot_f64c_serial
 
-SIMSIMD_MAKE_DOT(serial, f32, f32, SIMSIMD_IDENTIFY)          // simsimd_dot_f32_serial
-SIMSIMD_MAKE_COMPLEX_DOT(serial, f32, f32, SIMSIMD_IDENTIFY)  // simsimd_dot_f32c_serial
-SIMSIMD_MAKE_COMPLEX_VDOT(serial, f32, f32, SIMSIMD_IDENTIFY) // simsimd_vdot_f32c_serial
+SIMSIMD_MAKE_DOT(serial, f32, f32, SIMSIMD_DEREFERENCE)          // simsimd_dot_f32_serial
+SIMSIMD_MAKE_COMPLEX_DOT(serial, f32, f32, SIMSIMD_DEREFERENCE)  // simsimd_dot_f32c_serial
+SIMSIMD_MAKE_COMPLEX_VDOT(serial, f32, f32, SIMSIMD_DEREFERENCE) // simsimd_vdot_f32c_serial
 
-SIMSIMD_MAKE_DOT(serial, f16, f32, SIMSIMD_UNCOMPRESS_F16)          // simsimd_dot_f16_serial
-SIMSIMD_MAKE_COMPLEX_DOT(serial, f16, f32, SIMSIMD_UNCOMPRESS_F16)  // simsimd_dot_f16c_serial
-SIMSIMD_MAKE_COMPLEX_VDOT(serial, f16, f32, SIMSIMD_UNCOMPRESS_F16) // simsimd_vdot_f16c_serial
+SIMSIMD_MAKE_DOT(serial, f16, f32, SIMSIMD_F16_TO_F32)          // simsimd_dot_f16_serial
+SIMSIMD_MAKE_COMPLEX_DOT(serial, f16, f32, SIMSIMD_F16_TO_F32)  // simsimd_dot_f16c_serial
+SIMSIMD_MAKE_COMPLEX_VDOT(serial, f16, f32, SIMSIMD_F16_TO_F32) // simsimd_vdot_f16c_serial
 
-SIMSIMD_MAKE_DOT(serial, bf16, f32, SIMSIMD_UNCOMPRESS_BF16)          // simsimd_dot_bf16_serial
-SIMSIMD_MAKE_COMPLEX_DOT(serial, bf16, f32, SIMSIMD_UNCOMPRESS_BF16)  // simsimd_dot_bf16c_serial
-SIMSIMD_MAKE_COMPLEX_VDOT(serial, bf16, f32, SIMSIMD_UNCOMPRESS_BF16) // simsimd_vdot_bf16c_serial
+SIMSIMD_MAKE_DOT(serial, bf16, f32, SIMSIMD_BF16_TO_F32)          // simsimd_dot_bf16_serial
+SIMSIMD_MAKE_COMPLEX_DOT(serial, bf16, f32, SIMSIMD_BF16_TO_F32)  // simsimd_dot_bf16c_serial
+SIMSIMD_MAKE_COMPLEX_VDOT(serial, bf16, f32, SIMSIMD_BF16_TO_F32) // simsimd_vdot_bf16c_serial
 
-SIMSIMD_MAKE_DOT(serial, i8, i64, SIMSIMD_IDENTIFY) // simsimd_dot_i8_serial
+SIMSIMD_MAKE_DOT(serial, i8, i64, SIMSIMD_DEREFERENCE) // simsimd_dot_i8_serial
 
-SIMSIMD_MAKE_DOT(accurate, f32, f64, SIMSIMD_IDENTIFY)          // simsimd_dot_f32_accurate
-SIMSIMD_MAKE_COMPLEX_DOT(accurate, f32, f64, SIMSIMD_IDENTIFY)  // simsimd_dot_f32c_accurate
-SIMSIMD_MAKE_COMPLEX_VDOT(accurate, f32, f64, SIMSIMD_IDENTIFY) // simsimd_vdot_f32c_accurate
+SIMSIMD_MAKE_DOT(accurate, f32, f64, SIMSIMD_DEREFERENCE)          // simsimd_dot_f32_accurate
+SIMSIMD_MAKE_COMPLEX_DOT(accurate, f32, f64, SIMSIMD_DEREFERENCE)  // simsimd_dot_f32c_accurate
+SIMSIMD_MAKE_COMPLEX_VDOT(accurate, f32, f64, SIMSIMD_DEREFERENCE) // simsimd_vdot_f32c_accurate
 
-SIMSIMD_MAKE_DOT(accurate, f16, f64, SIMSIMD_UNCOMPRESS_F16)          // simsimd_dot_f16_accurate
-SIMSIMD_MAKE_COMPLEX_DOT(accurate, f16, f64, SIMSIMD_UNCOMPRESS_F16)  // simsimd_dot_f16c_accurate
-SIMSIMD_MAKE_COMPLEX_VDOT(accurate, f16, f64, SIMSIMD_UNCOMPRESS_F16) // simsimd_vdot_f16c_accurate
+SIMSIMD_MAKE_DOT(accurate, f16, f64, SIMSIMD_F16_TO_F32)          // simsimd_dot_f16_accurate
+SIMSIMD_MAKE_COMPLEX_DOT(accurate, f16, f64, SIMSIMD_F16_TO_F32)  // simsimd_dot_f16c_accurate
+SIMSIMD_MAKE_COMPLEX_VDOT(accurate, f16, f64, SIMSIMD_F16_TO_F32) // simsimd_vdot_f16c_accurate
 
-SIMSIMD_MAKE_DOT(accurate, bf16, f64, SIMSIMD_UNCOMPRESS_BF16)          // simsimd_dot_bf16_accurate
-SIMSIMD_MAKE_COMPLEX_DOT(accurate, bf16, f64, SIMSIMD_UNCOMPRESS_BF16)  // simsimd_dot_bf16c_accurate
-SIMSIMD_MAKE_COMPLEX_VDOT(accurate, bf16, f64, SIMSIMD_UNCOMPRESS_BF16) // simsimd_vdot_bf16c_accurate
+SIMSIMD_MAKE_DOT(accurate, bf16, f64, SIMSIMD_BF16_TO_F32)          // simsimd_dot_bf16_accurate
+SIMSIMD_MAKE_COMPLEX_DOT(accurate, bf16, f64, SIMSIMD_BF16_TO_F32)  // simsimd_dot_bf16c_accurate
+SIMSIMD_MAKE_COMPLEX_VDOT(accurate, bf16, f64, SIMSIMD_BF16_TO_F32) // simsimd_vdot_bf16c_accurate
 
 #if SIMSIMD_TARGET_ARM
 #if SIMSIMD_TARGET_NEON
 #pragma GCC push_options
-#pragma GCC target("+simd")
-#pragma clang attribute push(__attribute__((target("+simd"))), apply_to = function)
+#pragma GCC target("arch=armv8.2-a+simd")
+#pragma clang attribute push(__attribute__((target("arch=armv8.2-a+simd"))), apply_to = function)
+
+SIMSIMD_INTERNAL float32x4_t _simsimd_partial_load_f32x4_neon(simsimd_f32_t const* a, simsimd_size_t n) {
+    union {
+        float32x4_t vec;
+        simsimd_f32_t scalars[4];
+    } result;
+    simsimd_size_t i = 0;
+    for (; i < n; ++i)
+        result.scalars[i] = a[i];
+    for (; i < 4; ++i)
+        result.scalars[i] = 0;
+    return result.vec;
+}
 
 SIMSIMD_PUBLIC void simsimd_dot_f32_neon(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n,
                                          simsimd_distance_t* result) {
@@ -349,36 +366,48 @@ SIMSIMD_PUBLIC void simsimd_dot_i8_neon(simsimd_i8_t const* a, simsimd_i8_t cons
 
 #pragma clang attribute pop
 #pragma GCC pop_options
+#endif
 
+#if SIMSIMD_TARGET_NEON_F16
 #pragma GCC push_options
-#pragma GCC target("+simd+fp16")
-#pragma clang attribute push(__attribute__((target("+simd+fp16"))), apply_to = function)
+#pragma GCC target("arch=armv8.2-a+simd+fp16")
+#pragma clang attribute push(__attribute__((target("arch=armv8.2-a+simd+fp16"))), apply_to = function)
+
+SIMSIMD_INTERNAL float16x4_t _simsimd_partial_load_f16x4_neon(simsimd_f16_t const* a, simsimd_size_t n) {
+    // In case the software emulation for `f16` scalars is enabled, the `simsimd_f16_to_f32`
+    // function will run. It is extremely slow, so even for the tail, let's combine serial
+    // loads and stores with vectorized math.
+    union {
+        float16x4_t vec;
+        simsimd_f16_t scalars[4];
+    } result;
+    simsimd_size_t i = 0;
+    for (; i < n; ++i)
+        result.scalars[i] = a[i];
+    for (; i < 4; ++i)
+        result.scalars[i] = 0;
+    return result.vec;
+}
 
 SIMSIMD_PUBLIC void simsimd_dot_f16_neon(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n,
                                          simsimd_distance_t* result) {
     float32x4_t ab_vec = vdupq_n_f32(0);
+    float32x4_t a_vec, b_vec;
     simsimd_size_t i = 0;
-    for (; i + 4 <= n; i += 4) {
-        float32x4_t a_vec = vcvt_f32_f16(vld1_f16((simsimd_f16_for_arm_simd_t const*)a + i));
-        float32x4_t b_vec = vcvt_f32_f16(vld1_f16((simsimd_f16_for_arm_simd_t const*)b + i));
-        ab_vec = vfmaq_f32(ab_vec, a_vec, b_vec);
-    }
 
-    // In case the software emulation for `f16` scalars is enabled, the `simsimd_uncompress_f16`
-    // function will run. It is extremely slow, so even for the tail, let's combine serial
-    // loads and stores with vectorized math.
-    if (i < n) {
-        union {
-            float16x4_t f16_vec;
-            simsimd_f16_t f16[4];
-        } a_padded_tail, b_padded_tail;
-        simsimd_size_t j = 0;
-        for (; i < n; ++i, ++j)
-            a_padded_tail.f16[j] = a[i], b_padded_tail.f16[j] = b[i];
-        for (; j < 4; ++j)
-            a_padded_tail.f16[j] = 0, b_padded_tail.f16[j] = 0;
-        ab_vec = vfmaq_f32(ab_vec, vcvt_f32_f16(a_padded_tail.f16_vec), vcvt_f32_f16(b_padded_tail.f16_vec));
+simsimd_dot_f16_neon_cycle:
+    if (n < 4) {
+        a_vec = vcvt_f32_f16(_simsimd_partial_load_f16x4_neon(a, n));
+        b_vec = vcvt_f32_f16(_simsimd_partial_load_f16x4_neon(b, n));
+        n = 0;
+    } else {
+        a_vec = vcvt_f32_f16(vld1_f16((simsimd_f16_for_arm_simd_t const*)a));
+        b_vec = vcvt_f32_f16(vld1_f16((simsimd_f16_for_arm_simd_t const*)b));
+        a += 4, b += 4, n -= 4;
     }
+    ab_vec = vfmaq_f32(ab_vec, a_vec, b_vec);
+    if (n)
+        goto simsimd_dot_f16_neon_cycle;
     *result = vaddvq_f32(ab_vec);
 }
 
@@ -390,13 +419,13 @@ SIMSIMD_PUBLIC void simsimd_dot_f16c_neon(simsimd_f16_t const* a, simsimd_f16_t
     // at once. That's how the original implementation worked, but compiling it was a nightmare :)
     float32x4_t ab_real_vec = vdupq_n_f32(0);
     float32x4_t ab_imag_vec = vdupq_n_f32(0);
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
+
+    while (n >= 8) {
         // Unpack the input arrays into real and imaginary parts.
         // MSVC sadly doesn't recognize the `vld2_f16`, so we load the  data as signed
         // integers of the same size and reinterpret with `vreinterpret_f16_s16` afterwards.
-        int16x4x2_t a_vec = vld2_s16((short*)a + i);
-        int16x4x2_t b_vec = vld2_s16((short*)b + i);
+        int16x4x2_t a_vec = vld2_s16((short*)a);
+        int16x4x2_t b_vec = vld2_s16((short*)b);
         float32x4_t a_real_vec = vcvt_f32_f16(vreinterpret_f16_s16(a_vec.val[0]));
         float32x4_t a_imag_vec = vcvt_f32_f16(vreinterpret_f16_s16(a_vec.val[1]));
         float32x4_t b_real_vec = vcvt_f32_f16(vreinterpret_f16_s16(b_vec.val[0]));
@@ -407,20 +436,14 @@ SIMSIMD_PUBLIC void simsimd_dot_f16c_neon(simsimd_f16_t const* a, simsimd_f16_t
         ab_real_vec = vfmsq_f32(ab_real_vec, a_imag_vec, b_imag_vec);
         ab_imag_vec = vfmaq_f32(ab_imag_vec, a_real_vec, b_imag_vec);
         ab_imag_vec = vfmaq_f32(ab_imag_vec, a_imag_vec, b_real_vec);
-    }
-
-    // Reduce horizontal sums:
-    simsimd_f32_t ab_real = vaddvq_f32(ab_real_vec);
-    simsimd_f32_t ab_imag = vaddvq_f32(ab_imag_vec);
 
-    // Handle the tail:
-    for (; i + 2 <= n; i += 2) {
-        simsimd_f32_t ar = a[i], ai = a[i + 1], br = b[i], bi = b[i + 1];
-        ab_real += ar * br - ai * bi;
-        ab_imag += ar * bi + ai * br;
+        n -= 8, a += 8, b += 8;
     }
-    results[0] = ab_real;
-    results[1] = ab_imag;
+
+    // Reduce horizontal sums and aggregate with the tail:
+    simsimd_dot_f16c_serial(a, b, n, results);
+    results[0] += vaddvq_f32(ab_real_vec);
+    results[1] += vaddvq_f32(ab_imag_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_vdot_f16c_neon(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n, //
@@ -431,13 +454,13 @@ SIMSIMD_PUBLIC void simsimd_vdot_f16c_neon(simsimd_f16_t const* a, simsimd_f16_t
     // at once. That's how the original implementation worked, but compiling it was a nightmare :)
     float32x4_t ab_real_vec = vdupq_n_f32(0);
     float32x4_t ab_imag_vec = vdupq_n_f32(0);
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
+
+    while (n >= 8) {
         // Unpack the input arrays into real and imaginary parts.
         // MSVC sadly doesn't recognize the `vld2_f16`, so we load the  data as signed
         // integers of the same size and reinterpret with `vreinterpret_f16_s16` afterwards.
-        int16x4x2_t a_vec = vld2_s16((short*)a + i);
-        int16x4x2_t b_vec = vld2_s16((short*)b + i);
+        int16x4x2_t a_vec = vld2_s16((short*)a);
+        int16x4x2_t b_vec = vld2_s16((short*)b);
         float32x4_t a_real_vec = vcvt_f32_f16(vreinterpret_f16_s16(a_vec.val[0]));
         float32x4_t a_imag_vec = vcvt_f32_f16(vreinterpret_f16_s16(a_vec.val[1]));
         float32x4_t b_real_vec = vcvt_f32_f16(vreinterpret_f16_s16(b_vec.val[0]));
@@ -448,62 +471,61 @@ SIMSIMD_PUBLIC void simsimd_vdot_f16c_neon(simsimd_f16_t const* a, simsimd_f16_t
         ab_real_vec = vfmaq_f32(ab_real_vec, a_imag_vec, b_imag_vec);
         ab_imag_vec = vfmaq_f32(ab_imag_vec, a_real_vec, b_imag_vec);
         ab_imag_vec = vfmsq_f32(ab_imag_vec, a_imag_vec, b_real_vec);
-    }
 
-    // Reduce horizontal sums:
-    simsimd_f32_t ab_real = vaddvq_f32(ab_real_vec);
-    simsimd_f32_t ab_imag = vaddvq_f32(ab_imag_vec);
-
-    // Handle the tail:
-    for (; i + 2 <= n; i += 2) {
-        simsimd_f32_t ar = a[i], ai = a[i + 1], br = b[i], bi = b[i + 1];
-        ab_real += ar * br + ai * bi;
-        ab_imag += ar * bi - ai * br;
+        n -= 8, a += 8, b += 8;
     }
-    results[0] = ab_real;
-    results[1] = ab_imag;
+
+    // Reduce horizontal sums and aggregate with the tail:
+    simsimd_vdot_f16c_serial(a, b, n, results);
+    results[0] += vaddvq_f32(ab_real_vec);
+    results[1] += vaddvq_f32(ab_imag_vec);
 }
 
 #pragma clang attribute pop
 #pragma GCC pop_options
-#endif // SIMSIMD_TARGET_NEON
+#endif // SIMSIMD_TARGET_NEON_F16
 
 #if SIMSIMD_TARGET_NEON_BF16
 #pragma GCC push_options
 #pragma GCC target("arch=armv8.6-a+simd+bf16")
 #pragma clang attribute push(__attribute__((target("arch=armv8.6-a+simd+bf16"))), apply_to = function)
 
+SIMSIMD_INTERNAL bfloat16x8_t _simsimd_partial_load_bf16x8_neon(simsimd_bf16_t const* a, simsimd_size_t n) {
+    union {
+        bfloat16x8_t vec;
+        simsimd_bf16_t scalars[8];
+    } result;
+    simsimd_size_t i = 0;
+    for (; i < n; ++i)
+        result.scalars[i] = a[i];
+    for (; i < 8; ++i)
+        result.scalars[i] = 0;
+    return result.vec;
+}
+
 SIMSIMD_PUBLIC void simsimd_dot_bf16_neon(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n,
                                           simsimd_distance_t* result) {
-    float32x4_t ab_high_vec = vdupq_n_f32(0), ab_low_vec = vdupq_n_f32(0);
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
-        bfloat16x8_t a_vec = vld1q_bf16((simsimd_bf16_for_arm_simd_t const*)a + i);
-        bfloat16x8_t b_vec = vld1q_bf16((simsimd_bf16_for_arm_simd_t const*)b + i);
-        ab_high_vec = vbfmlaltq_f32(ab_high_vec, a_vec, b_vec);
-        ab_low_vec = vbfmlalbq_f32(ab_low_vec, a_vec, b_vec);
-    }
+    float32x4_t ab_vec = vdupq_n_f32(0);
+    bfloat16x8_t a_vec, b_vec;
 
-    // In case the software emulation for `bf16` scalars is enabled, the `simsimd_uncompress_bf16`
-    // function will run. It is extremely slow, so even for the tail, let's combine serial
-    // loads and stores with vectorized math.
-    if (i < n) {
-        union {
-            bfloat16x8_t bf16_vec;
-            simsimd_bf16_t bf16[8];
-        } a_padded_tail, b_padded_tail;
-        simsimd_size_t j = 0;
-        for (; i < n; ++i, ++j)
-            a_padded_tail.bf16[j] = a[i], b_padded_tail.bf16[j] = b[i];
-        for (; j < 8; ++j)
-            a_padded_tail.bf16[j] = 0, b_padded_tail.bf16[j] = 0;
-        ab_high_vec = vbfmlaltq_f32(ab_high_vec, a_padded_tail.bf16_vec, b_padded_tail.bf16_vec);
-        ab_low_vec = vbfmlalbq_f32(ab_low_vec, a_padded_tail.bf16_vec, b_padded_tail.bf16_vec);
+simsimd_dot_bf16_neon_cycle:
+    if (n < 8) {
+        a_vec = _simsimd_partial_load_bf16x8_neon(a, n);
+        b_vec = _simsimd_partial_load_bf16x8_neon(b, n);
+        n = 0;
+    } else {
+        a_vec = vld1q_bf16((simsimd_bf16_for_arm_simd_t const*)a);
+        b_vec = vld1q_bf16((simsimd_bf16_for_arm_simd_t const*)b);
+        a += 8, b += 8, n -= 8;
     }
-    *result = vaddvq_f32(ab_high_vec) + vaddvq_f32(ab_low_vec);
+    ab_vec = vbfdotq_f32(ab_vec, a_vec, b_vec);
+    if (n)
+        goto simsimd_dot_bf16_neon_cycle;
+
+    *result = vaddvq_f32(ab_vec);
 }
 
-SIMSIMD_PUBLIC void simsimd_dot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n, //
+SIMSIMD_PUBLIC void simsimd_dot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n,
                                            simsimd_distance_t* results) {
 
     // A nicer approach is to use `bf16` arithmetic for the dot product, but that requires
@@ -511,13 +533,13 @@ SIMSIMD_PUBLIC void simsimd_dot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf16
     // at once. That's how the original implementation worked, but compiling it was a nightmare :)
     float32x4_t ab_real_vec = vdupq_n_f32(0);
     float32x4_t ab_imag_vec = vdupq_n_f32(0);
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
+
+    while (n >= 8) {
         // Unpack the input arrays into real and imaginary parts.
         // MSVC sadly doesn't recognize the `vld2_bf16`, so we load the  data as signed
         // integers of the same size and reinterpret with `vreinterpret_bf16_s16` afterwards.
-        int16x4x2_t a_vec = vld2_s16((short*)a + i);
-        int16x4x2_t b_vec = vld2_s16((short*)b + i);
+        int16x4x2_t a_vec = vld2_s16((short*)a);
+        int16x4x2_t b_vec = vld2_s16((short*)b);
         float32x4_t a_real_vec = vcvt_f32_bf16(vreinterpret_bf16_s16(a_vec.val[0]));
         float32x4_t a_imag_vec = vcvt_f32_bf16(vreinterpret_bf16_s16(a_vec.val[1]));
         float32x4_t b_real_vec = vcvt_f32_bf16(vreinterpret_bf16_s16(b_vec.val[0]));
@@ -528,20 +550,14 @@ SIMSIMD_PUBLIC void simsimd_dot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf16
         ab_real_vec = vfmsq_f32(ab_real_vec, a_imag_vec, b_imag_vec);
         ab_imag_vec = vfmaq_f32(ab_imag_vec, a_real_vec, b_imag_vec);
         ab_imag_vec = vfmaq_f32(ab_imag_vec, a_imag_vec, b_real_vec);
-    }
-
-    // Reduce horizontal sums:
-    simsimd_f32_t ab_real = vaddvq_f32(ab_real_vec);
-    simsimd_f32_t ab_imag = vaddvq_f32(ab_imag_vec);
 
-    // Handle the tail:
-    for (; i + 2 <= n; i += 2) {
-        simsimd_f32_t ar = a[i], ai = a[i + 1], br = b[i], bi = b[i + 1];
-        ab_real += ar * br - ai * bi;
-        ab_imag += ar * bi + ai * br;
+        n -= 8, a += 8, b += 8;
     }
-    results[0] = ab_real;
-    results[1] = ab_imag;
+
+    // Reduce horizontal sums and aggregate with the tail:
+    simsimd_dot_bf16c_serial(a, b, n, results);
+    results[0] += vaddvq_f32(ab_real_vec);
+    results[1] += vaddvq_f32(ab_imag_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_vdot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n, //
@@ -552,13 +568,13 @@ SIMSIMD_PUBLIC void simsimd_vdot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf1
     // at once. That's how the original implementation worked, but compiling it was a nightmare :)
     float32x4_t ab_real_vec = vdupq_n_f32(0);
     float32x4_t ab_imag_vec = vdupq_n_f32(0);
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
+
+    while (n >= 8) {
         // Unpack the input arrays into real and imaginary parts.
         // MSVC sadly doesn't recognize the `vld2_bf16`, so we load the  data as signed
         // integers of the same size and reinterpret with `vreinterpret_bf16_s16` afterwards.
-        int16x4x2_t a_vec = vld2_s16((short*)a + i);
-        int16x4x2_t b_vec = vld2_s16((short*)b + i);
+        int16x4x2_t a_vec = vld2_s16((short*)a);
+        int16x4x2_t b_vec = vld2_s16((short*)b);
         float32x4_t a_real_vec = vcvt_f32_bf16(vreinterpret_bf16_s16(a_vec.val[0]));
         float32x4_t a_imag_vec = vcvt_f32_bf16(vreinterpret_bf16_s16(a_vec.val[1]));
         float32x4_t b_real_vec = vcvt_f32_bf16(vreinterpret_bf16_s16(b_vec.val[0]));
@@ -569,20 +585,14 @@ SIMSIMD_PUBLIC void simsimd_vdot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf1
         ab_real_vec = vfmaq_f32(ab_real_vec, a_imag_vec, b_imag_vec);
         ab_imag_vec = vfmaq_f32(ab_imag_vec, a_real_vec, b_imag_vec);
         ab_imag_vec = vfmsq_f32(ab_imag_vec, a_imag_vec, b_real_vec);
-    }
 
-    // Reduce horizontal sums:
-    simsimd_f32_t ab_real = vaddvq_f32(ab_real_vec);
-    simsimd_f32_t ab_imag = vaddvq_f32(ab_imag_vec);
-
-    // Handle the tail:
-    for (; i + 2 <= n; i += 2) {
-        simsimd_f32_t ar = a[i], ai = a[i + 1], br = b[i], bi = b[i + 1];
-        ab_real += ar * br + ai * bi;
-        ab_imag += ar * bi - ai * br;
+        n -= 8, a += 8, b += 8;
     }
-    results[0] = ab_real;
-    results[1] = ab_imag;
+
+    // Reduce horizontal sums and aggregate with the tail:
+    simsimd_vdot_bf16c_serial(a, b, n, results);
+    results[0] += vaddvq_f32(ab_real_vec);
+    results[1] += vaddvq_f32(ab_imag_vec);
 }
 
 #pragma clang attribute pop
@@ -592,8 +602,8 @@ SIMSIMD_PUBLIC void simsimd_vdot_bf16c_neon(simsimd_bf16_t const* a, simsimd_bf1
 #if SIMSIMD_TARGET_SVE
 
 #pragma GCC push_options
-#pragma GCC target("+sve")
-#pragma clang attribute push(__attribute__((target("+sve"))), apply_to = function)
+#pragma GCC target("arch=armv8.2-a+sve")
+#pragma clang attribute push(__attribute__((target("arch=armv8.2-a+sve"))), apply_to = function)
 
 SIMSIMD_PUBLIC void simsimd_dot_f32_sve(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n,
                                         simsimd_distance_t* result) {
@@ -719,8 +729,8 @@ SIMSIMD_PUBLIC void simsimd_vdot_f64c_sve(simsimd_f64_t const* a, simsimd_f64_t
 #pragma GCC pop_options
 
 #pragma GCC push_options
-#pragma GCC target("+sve+fp16")
-#pragma clang attribute push(__attribute__((target("+sve+fp16"))), apply_to = function)
+#pragma GCC target("arch=armv8.2-a+sve+fp16")
+#pragma clang attribute push(__attribute__((target("arch=armv8.2-a+sve+fp16"))), apply_to = function)
 
 SIMSIMD_PUBLIC void simsimd_dot_f16_sve(simsimd_f16_t const* a_enum, simsimd_f16_t const* b_enum, simsimd_size_t n,
                                         simsimd_distance_t* result) {
@@ -796,44 +806,7 @@ SIMSIMD_PUBLIC void simsimd_vdot_f16c_sve(simsimd_f16_t const* a, simsimd_f16_t
 #pragma GCC target("avx2", "f16c", "fma")
 #pragma clang attribute push(__attribute__((target("avx2,f16c,fma"))), apply_to = function)
 
-SIMSIMD_PUBLIC void simsimd_dot_f16_haswell(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n,
-                                            simsimd_distance_t* result) {
-    __m256 ab_vec = _mm256_setzero_ps();
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
-        __m256 a_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)(a + i)));
-        __m256 b_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)(b + i)));
-        ab_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_vec);
-    }
-
-    // In case the software emulation for `f16` scalars is enabled, the `simsimd_uncompress_f16`
-    // function will run. It is extremely slow, so even for the tail, let's combine serial
-    // loads and stores with vectorized math.
-    if (i < n) {
-        union {
-            __m128i f16_vec;
-            simsimd_f16_t f16[8];
-        } a_padded_tail, b_padded_tail;
-        simsimd_size_t j = 0;
-        for (; i < n; ++i, ++j)
-            a_padded_tail.f16[j] = a[i], b_padded_tail.f16[j] = b[i];
-        for (; j < 8; ++j)
-            a_padded_tail.f16[j] = 0, b_padded_tail.f16[j] = 0;
-        __m256 a_vec = _mm256_cvtph_ps(a_padded_tail.f16_vec);
-        __m256 b_vec = _mm256_cvtph_ps(b_padded_tail.f16_vec);
-        ab_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_vec);
-    }
-
-    ab_vec = _mm256_add_ps(_mm256_permute2f128_ps(ab_vec, ab_vec, 1), ab_vec);
-    ab_vec = _mm256_hadd_ps(ab_vec, ab_vec);
-    ab_vec = _mm256_hadd_ps(ab_vec, ab_vec);
-
-    simsimd_f32_t f32_result;
-    _mm_store_ss(&f32_result, _mm256_castps256_ps128(ab_vec));
-    *result = f32_result;
-}
-
-inline simsimd_f64_t _mm256_reduce_add_ps_dbl(__m256 vec) {
+SIMSIMD_INTERNAL simsimd_f64_t _simsimd_reduce_f32x8_haswell(__m256 vec) {
     // Convert the lower and higher 128-bit lanes of the input vector to double precision
     __m128 low_f32 = _mm256_castps256_ps128(vec);
     __m128 high_f32 = _mm256_extractf128_ps(vec, 1);
@@ -868,7 +841,7 @@ SIMSIMD_PUBLIC void simsimd_dot_f32_haswell(simsimd_f32_t const* a, simsimd_f32_
         __m256 b_vec = _mm256_loadu_ps(b + i);
         ab_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_vec);
     }
-    simsimd_f64_t ab = _mm256_reduce_add_ps_dbl(ab_vec);
+    simsimd_f64_t ab = _simsimd_reduce_f32x8_haswell(ab_vec);
     for (; i < n; ++i)
         ab += a[i] * b[i];
     *results = ab;
@@ -903,7 +876,7 @@ SIMSIMD_PUBLIC void simsimd_dot_f32c_haswell(simsimd_f32_t const* a, simsimd_f32
     // To multiply a floating-point value by -1, we can use the `XOR` instruction to flip the sign bit.
     // This way we can avoid the shuffling and the need for separate real and imaginary parts.
     // For the imaginary part of the product, we would need to swap the real and imaginary parts of
-    // one of the vectors.
+    // one of the vectors. Moreover, `XOR` can be placed after the primary loop.
     // Both operations are quite cheap, and the throughput doubles from 2.5 GB/s to 5 GB/s.
     __m256 ab_real_vec = _mm256_setzero_ps();
     __m256 ab_imag_vec = _mm256_setzero_ps();
@@ -922,15 +895,17 @@ SIMSIMD_PUBLIC void simsimd_dot_f32c_haswell(simsimd_f32_t const* a, simsimd_f32
     for (; i + 8 <= n; i += 8) {
         __m256 a_vec = _mm256_loadu_ps(a + i);
         __m256 b_vec = _mm256_loadu_ps(b + i);
-        __m256 b_flipped_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(b_vec), sign_flip_vec));
         __m256 b_swapped_vec = _mm256_castsi256_ps(_mm256_shuffle_epi8(_mm256_castps_si256(b_vec), swap_adjacent_vec));
-        ab_real_vec = _mm256_fmadd_ps(a_vec, b_flipped_vec, ab_real_vec);
+        ab_real_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_real_vec);
         ab_imag_vec = _mm256_fmadd_ps(a_vec, b_swapped_vec, ab_imag_vec);
     }
 
+    // Flip the sign bit in every second scalar before accumulation:
+    ab_real_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(ab_real_vec), sign_flip_vec));
+
     // Reduce horizontal sums:
-    simsimd_distance_t ab_real = _mm256_reduce_add_ps_dbl(ab_real_vec);
-    simsimd_distance_t ab_imag = _mm256_reduce_add_ps_dbl(ab_imag_vec);
+    simsimd_distance_t ab_real = _simsimd_reduce_f32x8_haswell(ab_real_vec);
+    simsimd_distance_t ab_imag = _simsimd_reduce_f32x8_haswell(ab_imag_vec);
 
     // Handle the tail:
     for (; i + 2 <= n; i += 2) {
@@ -963,14 +938,16 @@ SIMSIMD_PUBLIC void simsimd_vdot_f32c_haswell(simsimd_f32_t const* a, simsimd_f3
         __m256 a_vec = _mm256_loadu_ps(a + i);
         __m256 b_vec = _mm256_loadu_ps(b + i);
         ab_real_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_real_vec);
-        a_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(a_vec), sign_flip_vec));
         b_vec = _mm256_castsi256_ps(_mm256_shuffle_epi8(_mm256_castps_si256(b_vec), swap_adjacent_vec));
         ab_imag_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_imag_vec);
     }
 
+    // Flip the sign bit in every second scalar before accumulation:
+    ab_imag_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(ab_imag_vec), sign_flip_vec));
+
     // Reduce horizontal sums:
-    simsimd_distance_t ab_real = _mm256_reduce_add_ps_dbl(ab_real_vec);
-    simsimd_distance_t ab_imag = _mm256_reduce_add_ps_dbl(ab_imag_vec);
+    simsimd_distance_t ab_real = _simsimd_reduce_f32x8_haswell(ab_real_vec);
+    simsimd_distance_t ab_imag = _simsimd_reduce_f32x8_haswell(ab_imag_vec);
 
     // Handle the tail:
     for (; i + 2 <= n; i += 2) {
@@ -982,6 +959,44 @@ SIMSIMD_PUBLIC void simsimd_vdot_f32c_haswell(simsimd_f32_t const* a, simsimd_f3
     results[1] = ab_imag;
 }
 
+SIMSIMD_INTERNAL __m256 _simsimd_partial_load_f16x8_haswell(simsimd_f16_t const* a, simsimd_size_t n) {
+    // In case the software emulation for `f16` scalars is enabled, the `simsimd_f16_to_f32`
+    // function will run. It is extremely slow, so even for the tail, let's combine serial
+    // loads and stores with vectorized math.
+    union {
+        __m128i vec;
+        simsimd_f16_t scalars[8];
+    } result;
+    simsimd_size_t i = 0;
+    for (; i < n; ++i)
+        result.scalars[i] = a[i];
+    for (; i < 8; ++i)
+        result.scalars[i] = 0;
+    return _mm256_cvtph_ps(result.vec);
+}
+
+SIMSIMD_PUBLIC void simsimd_dot_f16_haswell(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n,
+                                            simsimd_distance_t* result) {
+    __m256 a_vec, b_vec;
+    __m256 ab_vec = _mm256_setzero_ps();
+
+simsimd_dot_f16_haswell_cycle:
+    if (n < 8) {
+        a_vec = _simsimd_partial_load_f16x8_haswell(a, n);
+        b_vec = _simsimd_partial_load_f16x8_haswell(b, n);
+        n = 0;
+    } else {
+        a_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)a));
+        b_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)b));
+        n -= 8, a += 8, b += 8;
+    }
+    ab_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_vec);
+    if (n)
+        goto simsimd_dot_f16_haswell_cycle;
+
+    *result = _simsimd_reduce_f32x8_haswell(ab_vec);
+}
+
 SIMSIMD_PUBLIC void simsimd_dot_f16c_haswell(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n,
                                              simsimd_distance_t* results) {
     // Ideally the implementation would load 256 bits worth of vector data at a time,
@@ -1004,40 +1019,24 @@ SIMSIMD_PUBLIC void simsimd_dot_f16c_haswell(simsimd_f16_t const* a, simsimd_f16
         3, 2, 1, 0,                              // Points to the first f32 in 128-bit lane
         7, 6, 5, 4                               // Points to the second f32 in 128-bit lane
     );
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
-        __m256 a_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)(a + i)));
-        __m256 b_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)(b + i)));
-        __m256 b_flipped_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(b_vec), sign_flip_vec));
-        __m256 b_swapped_vec = _mm256_castsi256_ps(_mm256_shuffle_epi8(_mm256_castps_si256(b_vec), swap_adjacent_vec));
-        ab_real_vec = _mm256_fmadd_ps(a_vec, b_flipped_vec, ab_real_vec);
-        ab_imag_vec = _mm256_fmadd_ps(a_vec, b_swapped_vec, ab_imag_vec);
-    }
 
-    // In case the software emulation for `f16` scalars is enabled, the `simsimd_uncompress_f16`
-    // function will run. It is extremely slow, so even for the tail, let's combine serial
-    // loads and stores with vectorized math.
-    if (i < n) {
-        union {
-            __m128i f16_vec;
-            simsimd_f16_t f16[8];
-        } a_padded_tail, b_padded_tail;
-        simsimd_size_t j = 0;
-        for (; i < n; ++i, ++j)
-            a_padded_tail.f16[j] = a[i], b_padded_tail.f16[j] = b[i];
-        for (; j < 8; ++j)
-            a_padded_tail.f16[j] = 0, b_padded_tail.f16[j] = 0;
-        __m256 a_vec = _mm256_cvtph_ps(a_padded_tail.f16_vec);
-        __m256 b_vec = _mm256_cvtph_ps(b_padded_tail.f16_vec);
-        __m256 b_flipped_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(b_vec), sign_flip_vec));
+    while (n >= 8) {
+        __m256 a_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)a));
+        __m256 b_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)b));
         __m256 b_swapped_vec = _mm256_castsi256_ps(_mm256_shuffle_epi8(_mm256_castps_si256(b_vec), swap_adjacent_vec));
-        ab_real_vec = _mm256_fmadd_ps(a_vec, b_flipped_vec, ab_real_vec);
+        ab_real_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_real_vec);
         ab_imag_vec = _mm256_fmadd_ps(a_vec, b_swapped_vec, ab_imag_vec);
+
+        n -= 8, a += 8, b += 8;
     }
 
-    // Reduce horizontal sums:
-    results[0] = _mm256_reduce_add_ps_dbl(ab_real_vec);
-    results[1] = _mm256_reduce_add_ps_dbl(ab_imag_vec);
+    // Flip the sign bit in every second scalar before accumulation:
+    ab_real_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(ab_real_vec), sign_flip_vec));
+
+    // Reduce horizontal sums and aggregate with the tail:
+    simsimd_dot_f16c_serial(a, b, n, results);
+    results[0] += _simsimd_reduce_f32x8_haswell(ab_real_vec);
+    results[1] += _simsimd_reduce_f32x8_haswell(ab_imag_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_vdot_f16c_haswell(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n,
@@ -1056,40 +1055,24 @@ SIMSIMD_PUBLIC void simsimd_vdot_f16c_haswell(simsimd_f16_t const* a, simsimd_f1
         3, 2, 1, 0,                              // Points to the first f32 in 128-bit lane
         7, 6, 5, 4                               // Points to the second f32 in 128-bit lane
     );
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
-        __m256 a_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)(a + i)));
-        __m256 b_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)(b + i)));
-        ab_real_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_real_vec);
-        a_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(a_vec), sign_flip_vec));
-        b_vec = _mm256_castsi256_ps(_mm256_shuffle_epi8(_mm256_castps_si256(b_vec), swap_adjacent_vec));
-        ab_imag_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_imag_vec);
-    }
 
-    // In case the software emulation for `f16` scalars is enabled, the `simsimd_uncompress_f16`
-    // function will run. It is extremely slow, so even for the tail, let's combine serial
-    // loads and stores with vectorized math.
-    if (i < n) {
-        union {
-            __m128i f16_vec;
-            simsimd_f16_t f16[8];
-        } a_padded_tail, b_padded_tail;
-        simsimd_size_t j = 0;
-        for (; i < n; ++i, ++j)
-            a_padded_tail.f16[j] = a[i], b_padded_tail.f16[j] = b[i];
-        for (; j < 8; ++j)
-            a_padded_tail.f16[j] = 0, b_padded_tail.f16[j] = 0;
-        __m256 a_vec = _mm256_cvtph_ps(a_padded_tail.f16_vec);
-        __m256 b_vec = _mm256_cvtph_ps(b_padded_tail.f16_vec);
+    while (n >= 8) {
+        __m256 a_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)a));
+        __m256 b_vec = _mm256_cvtph_ps(_mm_loadu_si128((__m128i const*)b));
         ab_real_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_real_vec);
-        a_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(a_vec), sign_flip_vec));
         b_vec = _mm256_castsi256_ps(_mm256_shuffle_epi8(_mm256_castps_si256(b_vec), swap_adjacent_vec));
         ab_imag_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_imag_vec);
+
+        n -= 8, a += 8, b += 8;
     }
 
-    // Reduce horizontal sums:
-    results[0] = _mm256_reduce_add_ps_dbl(ab_real_vec);
-    results[1] = _mm256_reduce_add_ps_dbl(ab_imag_vec);
+    // Flip the sign bit in every second scalar before accumulation:
+    ab_imag_vec = _mm256_castsi256_ps(_mm256_xor_si256(_mm256_castps_si256(ab_imag_vec), sign_flip_vec));
+
+    // Reduce horizontal sums and aggregate with the tail:
+    simsimd_dot_f16c_serial(a, b, n, results);
+    results[0] += _simsimd_reduce_f32x8_haswell(ab_real_vec);
+    results[1] += _simsimd_reduce_f32x8_haswell(ab_imag_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_dot_i8_haswell(simsimd_i8_t const* a, simsimd_i8_t const* b, simsimd_size_t n,
@@ -1123,49 +1106,51 @@ SIMSIMD_PUBLIC void simsimd_dot_i8_haswell(simsimd_i8_t const* a, simsimd_i8_t c
     // Take care of the tail:
     int ab = _mm_extract_epi32(ab_sum, 0);
     for (; i < n; ++i)
-        ab += a[i] * b[i];
+        ab += (int)(a[i]) * b[i];
     *result = ab;
 }
 
+SIMSIMD_INTERNAL __m256 _simsimd_bf16x8_to_f32x8_haswell(__m128i a) {
+    // Upcasting from `bf16` to `f32` is done by shifting the `bf16` values by 16 bits to the left, like:
+    return _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_cvtepu16_epi32(a), 16));
+}
+
+SIMSIMD_INTERNAL __m128i _simsimd_partial_load_bf16x8_haswell(simsimd_bf16_t const* a, simsimd_size_t n) {
+    // In case the software emulation for `bf16` scalars is enabled, the `simsimd_bf16_to_f32`
+    // function will run. It is extremely slow, so even for the tail, let's combine serial
+    // loads and stores with vectorized math.
+    union {
+        __m128i vec;
+        simsimd_bf16_t scalars[8];
+    } result;
+    simsimd_size_t i = 0;
+    for (; i < n; ++i)
+        result.scalars[i] = a[i];
+    for (; i < 8; ++i)
+        result.scalars[i] = 0;
+    return result.vec;
+}
+
 SIMSIMD_PUBLIC void simsimd_dot_bf16_haswell(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n,
                                              simsimd_distance_t* result) {
+    __m128i a_vec, b_vec;
     __m256 ab_vec = _mm256_setzero_ps();
-    simsimd_size_t i = 0;
-    for (; i + 8 <= n; i += 8) {
-        // Upcasting from `bf16` to `f32` is done by shifting the `bf16` values by 16 bits to the left, like:
-        // x = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_cvtepu16_epi32(x), 16))
-        __m256 a_vec =
-            _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_cvtepu16_epi32(_mm_loadu_si128((__m128i const*)(a + i))), 16));
-        __m256 b_vec =
-            _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_cvtepu16_epi32(_mm_loadu_si128((__m128i const*)(b + i))), 16));
-        ab_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_vec);
-    }
 
-    // In case the software emulation for `bf16` scalars is enabled, the `simsimd_uncompress_bf16`
-    // function will run. It is extremely slow, so even for the tail, let's combine serial
-    // loads and stores with vectorized math.
-    if (i < n) {
-        union {
-            __m128i bf16_vec;
-            simsimd_bf16_t bf16[8];
-        } a_padded_tail, b_padded_tail;
-        simsimd_size_t j = 0;
-        for (; i < n; ++i, ++j)
-            a_padded_tail.bf16[j] = a[i], b_padded_tail.bf16[j] = b[i];
-        for (; j < 8; ++j)
-            a_padded_tail.bf16[j] = 0, b_padded_tail.bf16[j] = 0;
-        __m256 a_vec = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_cvtepu16_epi32(a_padded_tail.bf16_vec), 16));
-        __m256 b_vec = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_cvtepu16_epi32(b_padded_tail.bf16_vec), 16));
-        ab_vec = _mm256_fmadd_ps(a_vec, b_vec, ab_vec);
+simsimd_dot_bf16_haswell_cycle:
+    if (n < 8) {
+        a_vec = _simsimd_partial_load_bf16x8_haswell(a, n);
+        b_vec = _simsimd_partial_load_bf16x8_haswell(b, n);
+        n = 0;
+    } else {
+        a_vec = _mm_loadu_si128((__m128i const*)a);
+        b_vec = _mm_loadu_si128((__m128i const*)b);
+        a += 8, b += 8, n -= 8;
     }
+    ab_vec = _mm256_fmadd_ps(_simsimd_bf16x8_to_f32x8_haswell(a_vec), _simsimd_bf16x8_to_f32x8_haswell(b_vec), ab_vec);
+    if (n)
+        goto simsimd_dot_bf16_haswell_cycle;
 
-    ab_vec = _mm256_add_ps(_mm256_permute2f128_ps(ab_vec, ab_vec, 1), ab_vec);
-    ab_vec = _mm256_hadd_ps(ab_vec, ab_vec);
-    ab_vec = _mm256_hadd_ps(ab_vec, ab_vec);
-
-    simsimd_f32_t f32_result;
-    _mm_store_ss(&f32_result, _mm256_castps256_ps128(ab_vec));
-    *result = f32_result;
+    *result = _simsimd_reduce_f32x8_haswell(ab_vec);
 }
 
 #pragma clang attribute pop
@@ -1174,8 +1159,15 @@ SIMSIMD_PUBLIC void simsimd_dot_bf16_haswell(simsimd_bf16_t const* a, simsimd_bf
 
 #if SIMSIMD_TARGET_SKYLAKE
 #pragma GCC push_options
-#pragma GCC target("avx512f", "avx512vl", "avx512bw", "bmi2")
-#pragma clang attribute push(__attribute__((target("avx512f,avx512vl,avx512bw,bmi2"))), apply_to = function)
+#pragma GCC target("avx2", "avx512f", "avx512vl", "avx512bw", "bmi2")
+#pragma clang attribute push(__attribute__((target("avx2,avx512f,avx512vl,avx512bw,bmi2"))), apply_to = function)
+
+SIMSIMD_INTERNAL simsimd_f64_t _simsimd_reduce_f32x16_skylake(__m512 a) {
+    __m512 x = _mm512_add_ps(a, _mm512_shuffle_f32x4(a, a, _MM_SHUFFLE(0, 0, 3, 2)));
+    __m128 r = _mm512_castps512_ps128(_mm512_add_ps(x, _mm512_shuffle_f32x4(x, x, _MM_SHUFFLE(0, 0, 0, 1))));
+    r = _mm_hadd_ps(r, r);
+    return _mm_cvtss_f32(_mm_hadd_ps(r, r));
+}
 
 SIMSIMD_PUBLIC void simsimd_dot_f32_skylake(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n,
                                             simsimd_distance_t* result) {
@@ -1197,7 +1189,7 @@ simsimd_dot_f32_skylake_cycle:
     if (n)
         goto simsimd_dot_f32_skylake_cycle;
 
-    *result = _mm512_reduce_add_ps(ab_vec);
+    *result = _simsimd_reduce_f32x16_skylake(ab_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_dot_f64_skylake(simsimd_f64_t const* a, simsimd_f64_t const* b, simsimd_size_t n,
@@ -1225,11 +1217,10 @@ simsimd_dot_f64_skylake_cycle:
 
 SIMSIMD_PUBLIC void simsimd_dot_f32c_skylake(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n,
                                              simsimd_distance_t* results) {
-
     __m512 ab_real_vec = _mm512_setzero();
     __m512 ab_imag_vec = _mm512_setzero();
     __m512 a_vec;
-    __m512i b_vec;
+    __m512 b_vec;
 
     // We take into account, that FMS is the same as FMA with a negative multiplier.
     // To multiply a floating-point value by -1, we can use the `XOR` instruction to flip the sign bit.
@@ -1247,27 +1238,29 @@ simsimd_dot_f32c_skylake_cycle:
     if (n < 16) {
         __mmask16 mask = (__mmask16)_bzhi_u32(0xFFFFFFFF, n);
         a_vec = _mm512_maskz_loadu_ps(mask, a);
-        b_vec = _mm512_castps_si512(_mm512_maskz_loadu_ps(mask, b));
+        b_vec = _mm512_maskz_loadu_ps(mask, b);
         n = 0;
     } else {
         a_vec = _mm512_loadu_ps(a);
-        b_vec = _mm512_castps_si512(_mm512_loadu_ps(b));
+        b_vec = _mm512_loadu_ps(b);
         a += 16, b += 16, n -= 16;
     }
-    ab_real_vec = _mm512_fmadd_ps(_mm512_castsi512_ps(_mm512_xor_si512(b_vec, sign_flip_vec)), a_vec, ab_real_vec);
-    ab_imag_vec =
-        _mm512_fmadd_ps(_mm512_castsi512_ps(_mm512_shuffle_epi8(b_vec, swap_adjacent_vec)), a_vec, ab_imag_vec);
+    ab_real_vec = _mm512_fmadd_ps(b_vec, a_vec, ab_real_vec);
+    ab_imag_vec = _mm512_fmadd_ps(
+        _mm512_castsi512_ps(_mm512_shuffle_epi8(_mm512_castps_si512(b_vec), swap_adjacent_vec)), a_vec, ab_imag_vec);
     if (n)
         goto simsimd_dot_f32c_skylake_cycle;
 
+    // Flip the sign bit in every second scalar before accumulation:
+    ab_real_vec = _mm512_castsi512_ps(_mm512_xor_si512(_mm512_castps_si512(ab_real_vec), sign_flip_vec));
+
     // Reduce horizontal sums:
-    results[0] = _mm512_reduce_add_ps(ab_real_vec);
-    results[1] = _mm512_reduce_add_ps(ab_imag_vec);
+    results[0] = _simsimd_reduce_f32x16_skylake(ab_real_vec);
+    results[1] = _simsimd_reduce_f32x16_skylake(ab_imag_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_vdot_f32c_skylake(simsimd_f32_t const* a, simsimd_f32_t const* b, simsimd_size_t n,
                                               simsimd_distance_t* results) {
-
     __m512 ab_real_vec = _mm512_setzero();
     __m512 ab_imag_vec = _mm512_setzero();
     __m512 a_vec;
@@ -1297,24 +1290,25 @@ simsimd_vdot_f32c_skylake_cycle:
         a += 16, b += 16, n -= 16;
     }
     ab_real_vec = _mm512_fmadd_ps(a_vec, b_vec, ab_real_vec);
-    a_vec = _mm512_castsi512_ps(_mm512_xor_si512(_mm512_castps_si512(a_vec), sign_flip_vec));
     b_vec = _mm512_castsi512_ps(_mm512_shuffle_epi8(_mm512_castps_si512(b_vec), swap_adjacent_vec));
     ab_imag_vec = _mm512_fmadd_ps(a_vec, b_vec, ab_imag_vec);
     if (n)
         goto simsimd_vdot_f32c_skylake_cycle;
 
+    // Flip the sign bit in every second scalar before accumulation:
+    ab_imag_vec = _mm512_castsi512_ps(_mm512_xor_si512(_mm512_castps_si512(ab_imag_vec), sign_flip_vec));
+
     // Reduce horizontal sums:
-    results[0] = _mm512_reduce_add_ps(ab_real_vec);
-    results[1] = _mm512_reduce_add_ps(ab_imag_vec);
+    results[0] = _simsimd_reduce_f32x16_skylake(ab_real_vec);
+    results[1] = _simsimd_reduce_f32x16_skylake(ab_imag_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_dot_f64c_skylake(simsimd_f64_t const* a, simsimd_f64_t const* b, simsimd_size_t n,
                                              simsimd_distance_t* results) {
-
     __m512d ab_real_vec = _mm512_setzero_pd();
     __m512d ab_imag_vec = _mm512_setzero_pd();
     __m512d a_vec;
-    __m512i b_vec;
+    __m512d b_vec;
 
     // We take into account, that FMS is the same as FMA with a negative multiplier.
     // To multiply a floating-point value by -1, we can use the `XOR` instruction to flip the sign bit.
@@ -1335,19 +1329,22 @@ simsimd_dot_f64c_skylake_cycle:
     if (n < 8) {
         __mmask8 mask = (__mmask8)_bzhi_u32(0xFFFFFFFF, n);
         a_vec = _mm512_maskz_loadu_pd(mask, a);
-        b_vec = _mm512_castpd_si512(_mm512_maskz_loadu_pd(mask, b));
+        b_vec = _mm512_maskz_loadu_pd(mask, b);
         n = 0;
     } else {
         a_vec = _mm512_loadu_pd(a);
-        b_vec = _mm512_castpd_si512(_mm512_loadu_pd(b));
+        b_vec = _mm512_loadu_pd(b);
         a += 8, b += 8, n -= 8;
     }
-    ab_real_vec = _mm512_fmadd_pd(_mm512_castsi512_pd(_mm512_xor_si512(b_vec, sign_flip_vec)), a_vec, ab_real_vec);
-    ab_imag_vec =
-        _mm512_fmadd_pd(_mm512_castsi512_pd(_mm512_shuffle_epi8(b_vec, swap_adjacent_vec)), a_vec, ab_imag_vec);
+    ab_real_vec = _mm512_fmadd_pd(b_vec, a_vec, ab_real_vec);
+    ab_imag_vec = _mm512_fmadd_pd(
+        _mm512_castsi512_pd(_mm512_shuffle_epi8(_mm512_castpd_si512(b_vec), swap_adjacent_vec)), a_vec, ab_imag_vec);
     if (n)
         goto simsimd_dot_f64c_skylake_cycle;
 
+    // Flip the sign bit in every second scalar before accumulation:
+    ab_real_vec = _mm512_castsi512_pd(_mm512_xor_si512(_mm512_castpd_si512(ab_real_vec), sign_flip_vec));
+
     // Reduce horizontal sums:
     results[0] = _mm512_reduce_add_pd(ab_real_vec);
     results[1] = _mm512_reduce_add_pd(ab_imag_vec);
@@ -1355,7 +1352,6 @@ simsimd_dot_f64c_skylake_cycle:
 
 SIMSIMD_PUBLIC void simsimd_vdot_f64c_skylake(simsimd_f64_t const* a, simsimd_f64_t const* b, simsimd_size_t n,
                                               simsimd_distance_t* results) {
-
     __m512d ab_real_vec = _mm512_setzero_pd();
     __m512d ab_imag_vec = _mm512_setzero_pd();
     __m512d a_vec;
@@ -1388,12 +1384,14 @@ simsimd_vdot_f64c_skylake_cycle:
         a += 8, b += 8, n -= 8;
     }
     ab_real_vec = _mm512_fmadd_pd(a_vec, b_vec, ab_real_vec);
-    a_vec = _mm512_castsi512_pd(_mm512_xor_si512(_mm512_castpd_si512(a_vec), sign_flip_vec));
     b_vec = _mm512_castsi512_pd(_mm512_shuffle_epi8(_mm512_castpd_si512(b_vec), swap_adjacent_vec));
     ab_imag_vec = _mm512_fmadd_pd(a_vec, b_vec, ab_imag_vec);
     if (n)
         goto simsimd_vdot_f64c_skylake_cycle;
 
+    // Flip the sign bit in every second scalar before accumulation:
+    ab_imag_vec = _mm512_castsi512_pd(_mm512_xor_si512(_mm512_castpd_si512(ab_imag_vec), sign_flip_vec));
+
     // Reduce horizontal sums:
     results[0] = _mm512_reduce_add_pd(ab_real_vec);
     results[1] = _mm512_reduce_add_pd(ab_imag_vec);
@@ -1405,8 +1403,9 @@ simsimd_vdot_f64c_skylake_cycle:
 
 #if SIMSIMD_TARGET_GENOA
 #pragma GCC push_options
-#pragma GCC target("avx512f", "avx512vl", "bmi2", "avx512bw", "avx512bf16")
-#pragma clang attribute push(__attribute__((target("avx512f,avx512vl,bmi2,avx512bw,avx512bf16"))), apply_to = function)
+#pragma GCC target("avx2", "avx512f", "avx512vl", "bmi2", "avx512bw", "avx512bf16")
+#pragma clang attribute push(__attribute__((target("avx2,avx512f,avx512vl,bmi2,avx512bw,avx512bf16"))),                \
+                             apply_to = function)
 
 SIMSIMD_PUBLIC void simsimd_dot_bf16_genoa(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n,
                                            simsimd_distance_t* result) {
@@ -1428,12 +1427,11 @@ simsimd_dot_bf16_genoa_cycle:
     if (n)
         goto simsimd_dot_bf16_genoa_cycle;
 
-    *result = _mm512_reduce_add_ps(ab_vec);
+    *result = _simsimd_reduce_f32x16_skylake(ab_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_dot_bf16c_genoa(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n,
                                             simsimd_distance_t* results) {
-
     __m512 ab_real_vec = _mm512_setzero_ps();
     __m512 ab_imag_vec = _mm512_setzero_ps();
     __m512i a_vec;
@@ -1470,13 +1468,12 @@ simsimd_dot_bf16c_genoa_cycle:
         goto simsimd_dot_bf16c_genoa_cycle;
 
     // Reduce horizontal sums:
-    results[0] = _mm512_reduce_add_ps(ab_real_vec);
-    results[1] = _mm512_reduce_add_ps(ab_imag_vec);
+    results[0] = _simsimd_reduce_f32x16_skylake(ab_real_vec);
+    results[1] = _simsimd_reduce_f32x16_skylake(ab_imag_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_vdot_bf16c_genoa(simsimd_bf16_t const* a, simsimd_bf16_t const* b, simsimd_size_t n,
                                              simsimd_distance_t* results) {
-
     __m512 ab_real_vec = _mm512_setzero_ps();
     __m512 ab_imag_vec = _mm512_setzero_ps();
     __m512i a_vec;
@@ -1514,8 +1511,8 @@ simsimd_dot_bf16c_genoa_cycle:
         goto simsimd_dot_bf16c_genoa_cycle;
 
     // Reduce horizontal sums:
-    results[0] = _mm512_reduce_add_ps(ab_real_vec);
-    results[1] = _mm512_reduce_add_ps(ab_imag_vec);
+    results[0] = _simsimd_reduce_f32x16_skylake(ab_real_vec);
+    results[1] = _simsimd_reduce_f32x16_skylake(ab_imag_vec);
 }
 
 #pragma clang attribute pop
@@ -1524,8 +1521,9 @@ simsimd_dot_bf16c_genoa_cycle:
 
 #if SIMSIMD_TARGET_SAPPHIRE
 #pragma GCC push_options
-#pragma GCC target("avx512f", "avx512vl", "bmi2", "avx512bw", "avx512fp16")
-#pragma clang attribute push(__attribute__((target("avx512f,avx512vl,bmi2,avx512bw,avx512fp16"))), apply_to = function)
+#pragma GCC target("avx2", "avx512f", "avx512vl", "bmi2", "avx512bw", "avx512fp16")
+#pragma clang attribute push(__attribute__((target("avx2,avx512f,avx512vl,bmi2,avx512bw,avx512fp16"))),                \
+                             apply_to = function)
 
 SIMSIMD_PUBLIC void simsimd_dot_f16_sapphire(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n,
                                              simsimd_distance_t* result) {
@@ -1552,7 +1550,6 @@ simsimd_dot_f16_sapphire_cycle:
 
 SIMSIMD_PUBLIC void simsimd_dot_f16c_sapphire(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n,
                                               simsimd_distance_t* results) {
-
     __m512h ab_real_vec = _mm512_setzero_ph();
     __m512h ab_imag_vec = _mm512_setzero_ph();
     __m512i a_vec;
@@ -1582,6 +1579,7 @@ simsimd_dot_f16c_sapphire_cycle:
         b_vec = _mm512_loadu_epi16(b);
         a += 32, b += 32, n -= 32;
     }
+    // TODO: Consider using `_mm512_fmaddsub`
     ab_real_vec = _mm512_fmadd_ph(_mm512_castsi512_ph(_mm512_xor_si512(b_vec, sign_flip_vec)),
                                   _mm512_castsi512_ph(a_vec), ab_real_vec);
     ab_imag_vec = _mm512_fmadd_ph(_mm512_castsi512_ph(_mm512_shuffle_epi8(b_vec, swap_adjacent_vec)),
@@ -1590,13 +1588,13 @@ simsimd_dot_f16c_sapphire_cycle:
         goto simsimd_dot_f16c_sapphire_cycle;
 
     // Reduce horizontal sums:
+    // TODO: Optimize this with tree-like reductions
     results[0] = _mm512_reduce_add_ph(ab_real_vec);
     results[1] = _mm512_reduce_add_ph(ab_imag_vec);
 }
 
 SIMSIMD_PUBLIC void simsimd_vdot_f16c_sapphire(simsimd_f16_t const* a, simsimd_f16_t const* b, simsimd_size_t n,
                                                simsimd_distance_t* results) {
-
     __m512h ab_real_vec = _mm512_setzero_ph();
     __m512h ab_imag_vec = _mm512_setzero_ph();
     __m512i a_vec;
@@ -1644,8 +1642,9 @@ simsimd_dot_f16c_sapphire_cycle:
 
 #if SIMSIMD_TARGET_ICE
 #pragma GCC push_options
-#pragma GCC target("avx512f", "avx512vl", "bmi2", "avx512bw", "avx512vnni")
-#pragma clang attribute push(__attribute__((target("avx512f,avx512vl,bmi2,avx512bw,avx512vnni"))), apply_to = function)
+#pragma GCC target("avx2", "avx512f", "avx512vl", "bmi2", "avx512bw", "avx512vnni")
+#pragma clang attribute push(__attribute__((target("avx2,avx512f,avx512vl,bmi2,avx512bw,avx512vnni"))),                \
+                             apply_to = function)
 
 SIMSIMD_PUBLIC void simsimd_dot_i8_ice(simsimd_i8_t const* a, simsimd_i8_t const* b, simsimd_size_t n,
                                        simsimd_distance_t* result) {