usearch 2.1.2 → 2.2.0

package/simsimd/include/simsimd/simsimd.h

@@ -1,7 +1,7 @@
 /**
  *  @brief Collection of Similarity Measures, SIMD-accelerated with SSE, AVX, NEON, SVE.
  *
- *  @author Ashot Vardanian
+ *  @author Ash Vardanian
  *  @date March 14, 2023
  *
  *  x86 intrinsics: https://www.intel.com/content/www/us/en/docs/intrinsics-guide/
@@ -14,23 +14,82 @@
 #include <stddef.h> // `size_t`
 #include <stdint.h>
 
-#if defined(__AVX2__)
-#include <immintrin.h>
+#ifdef _MSC_VER
+#include <intrin.h>
+#define popcount32 __popcnt
+#define popcount64 __popcnt64
+#else
+#define popcount32 __builtin_popcount
+#define popcount64 __builtin_popcountll
 #endif
 
+// Compiling for Arm: SIMSIMD_TARGET_ARM
+#if defined(__aarch64__) || defined(_M_ARM64)
+#define SIMSIMD_TARGET_ARM 1
+
+// Compiling for Arm: SIMSIMD_TARGET_ARM_NEON
+#if !defined(SIMSIMD_TARGET_ARM_NEON)
 #if defined(__ARM_NEON)
-#include <arm_neon.h>
+#define SIMSIMD_TARGET_ARM_NEON 1
+#else
+#define SIMSIMD_TARGET_ARM_NEON 0
+#endif
 #endif
 
+// Compiling for Arm: SIMSIMD_TARGET_ARM_SVE
+#if !defined(SIMSIMD_TARGET_ARM_SVE)
 #if defined(__ARM_FEATURE_SVE)
-#include <arm_sve.h>
+#define SIMSIMD_TARGET_ARM_SVE 1
+#else
+#define SIMSIMD_TARGET_ARM_SVE 0
+#endif
 #endif
 
-#ifdef _MSC_VER
-#include <intrin.h>
-#define popcount32 __popcnt
+#define SIMSIMD_TARGET_X86 0
+#define SIMSIMD_TARGET_X86_AVX2 0
+#define SIMSIMD_TARGET_X86_AVX512 0
+
+// Compiling for x86: SIMSIMD_TARGET_X86
+#elif defined(__x86_64__) || defined(_M_X64)
+#define SIMSIMD_TARGET_X86 1
+
+// Compiling for x86: SIMSIMD_TARGET_X86_AVX2
+#if !defined(SIMSIMD_TARGET_X86_AVX2)
+#if defined(__AVX2__)
+#define SIMSIMD_TARGET_X86_AVX2 1
 #else
-#define popcount32 __builtin_popcount
+#define SIMSIMD_TARGET_X86_AVX2 0
+#endif
+#endif
+
+// Compiling for x86: SIMSIMD_TARGET_X86_AVX512
+#if !defined(SIMSIMD_TARGET_X86_AVX512)
+#if defined(__AVX512F__) || defined(__AVX512VPOPCNTDQ__)
+#define SIMSIMD_TARGET_X86_AVX512 1
+#else
+#define SIMSIMD_TARGET_X86_AVX512 0
+#endif
+#endif
+
+#define SIMSIMD_TARGET_ARM 0
+#define SIMSIMD_TARGET_ARM_NEON 0
+#define SIMSIMD_TARGET_ARM_SVE 0
+
+// Compiling for unknown hardware architecture
+#else
+#error Unknown hardware architecture!
+#endif
+
+#if SIMSIMD_TARGET_ARM_NEON
+#include <arm_neon.h>
+#endif
+
+#if SIMSIMD_TARGET_ARM_SVE
+#include <arm_sve.h>
+#endif
+
+#if SIMSIMD_TARGET_X86_AVX2 || SIMSIMD_TARGET_X86_AVX512
+#include <immintrin.h>
 #endif
 
 #ifdef __cplusplus
@@ -46,8 +105,12 @@ union simsimd_f32i32_t {
     float f;
 };
 
-inline static simsimd_f32_t simsimd_dot_f32_sve(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
-#if defined(__ARM_FEATURE_SVE)
+#if SIMSIMD_TARGET_ARM
+#if SIMSIMD_TARGET_ARM_SVE
+
+__attribute__((target("+sve"))) inline static simsimd_f32_t //
+simsimd_dot_f32_sve(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
+
     size_t i = 0;
     svfloat32_t ab_vec = svdupq_n_f32(0.f, 0.f, 0.f, 0.f);
     svbool_t pg_vec = svwhilelt_b32(i, d);
@@ -59,14 +122,10 @@ inline static simsimd_f32_t simsimd_dot_f32_sve(simsimd_f32_t const* a, simsimd_
         pg_vec = svwhilelt_b32(i, d);
     } while (svptest_any(svptrue_b32(), pg_vec));
     return 1 - svaddv_f32(svptrue_b32(), ab_vec);
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_cos_f32_sve(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
-#if defined(__ARM_FEATURE_SVE)
+__attribute__((target("+sve"))) inline static simsimd_f32_t //
+simsimd_cos_f32_sve(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
     size_t i = 0;
     svfloat32_t ab_vec = svdupq_n_f32(0.f, 0.f, 0.f, 0.f);
     svfloat32_t a2_vec = svdupq_n_f32(0.f, 0.f, 0.f, 0.f);
@@ -85,14 +144,10 @@ inline static simsimd_f32_t simsimd_cos_f32_sve(simsimd_f32_t const* a, simsimd_
     simsimd_f32_t a2 = svaddv_f32(svptrue_b32(), a2_vec);
     simsimd_f32_t b2 = svaddv_f32(svptrue_b32(), b2_vec);
     return 1 - ab / (sqrt(a2) * sqrt(b2));
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_l2sq_f32_sve(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
-#if defined(__ARM_FEATURE_SVE)
+__attribute__((target("+sve"))) inline static simsimd_f32_t //
+simsimd_l2sq_f32_sve(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
     size_t i = 0;
     svfloat32_t d2_vec = svdupq_n_f32(0.f, 0.f, 0.f, 0.f);
     svbool_t pg_vec = svwhilelt_b32(i, d);
@@ -105,15 +160,11 @@ inline static simsimd_f32_t simsimd_l2sq_f32_sve(simsimd_f32_t const* a, simsimd
         pg_vec = svwhilelt_b32(i, d);
     } while (svptest_any(svptrue_b32(), pg_vec));
     simsimd_f32_t d2 = svaddv_f32(svptrue_b32(), d2_vec);
-    return sqrt(d2);
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
+    return d2;
 }
 
-inline static simsimd_f32_t simsimd_cos_f16_sve(simsimd_f16_t const* a_enum, simsimd_f16_t const* b_enum, size_t d) {
-#if defined(__ARM_FEATURE_SVE)
+__attribute__((target("+sve+fp16"))) inline static simsimd_f32_t //
+simsimd_cos_f16_sve(simsimd_f16_t const* a_enum, simsimd_f16_t const* b_enum, size_t d) {
     size_t i = 0;
     svfloat16_t ab_vec = svdupq_n_f16(0, 0, 0, 0, 0, 0, 0, 0);
     svfloat16_t a2_vec = svdupq_n_f16(0, 0, 0, 0, 0, 0, 0, 0);
@@ -134,14 +185,10 @@ inline static simsimd_f32_t simsimd_cos_f16_sve(simsimd_f16_t const* a_enum, sim
     simsimd_f16_t a2 = svaddv_f16(svptrue_b16(), a2_vec);
     simsimd_f16_t b2 = svaddv_f16(svptrue_b16(), b2_vec);
     return 1 - ab / (sqrt(a2) * sqrt(b2));
-#else
-    (void)a_enum, (void)b_enum, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_l2sq_f16_sve(simsimd_f16_t const* a_enum, simsimd_f16_t const* b_enum, size_t d) {
-#if defined(__ARM_FEATURE_SVE)
+__attribute__((target("+sve+fp16"))) inline static simsimd_f32_t //
+simsimd_l2sq_f16_sve(simsimd_f16_t const* a_enum, simsimd_f16_t const* b_enum, size_t d) {
     size_t i = 0;
     svfloat16_t d2_vec = svdupq_n_f16(0, 0, 0, 0, 0, 0, 0, 0);
     svbool_t pg_vec = svwhilelt_b16(i, d);
@@ -155,16 +202,12 @@ inline static simsimd_f32_t simsimd_l2sq_f16_sve(simsimd_f16_t const* a_enum, si
         i += svcnth();
         pg_vec = svwhilelt_b16(i, d);
     } while (svptest_any(svptrue_b16(), pg_vec));
-    float16_t f16 = svaddv_f16(svptrue_b16(), d2_vec);
-    return 1 - simsimd_f32_t(f16);
-#else
-    (void)a_enum, (void)b_enum, (void)d;
-    return -1;
-#endif
+    float16_t d2_f16 = svaddv_f16(svptrue_b16(), d2_vec);
+    return 1 - d2_f16;
 }
 
-inline static simsimd_f32_t simsimd_hamming_b1x8_sve(uint8_t const* a, uint8_t const* b, size_t d) {
-#if defined(__ARM_FEATURE_SVE)
+__attribute__((target("+sve"))) inline static simsimd_f32_t //
+simsimd_hamming_b1x8_sve(uint8_t const* a, uint8_t const* b, size_t d) {
     size_t i = 0;
     svuint8_t d_vec = svdupq_n_u8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
     svbool_t pg_vec = svwhilelt_b8(i, d);
@@ -177,26 +220,24 @@ inline static simsimd_f32_t simsimd_hamming_b1x8_sve(uint8_t const* a, uint8_t c
         pg_vec = svwhilelt_b32(i, d);
     } while (svptest_any(svptrue_b32(), pg_vec));
     return 1 - svaddv_u8(svptrue_b32(), d_vec);
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_dot_f32x4_neon(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
-#if defined(__ARM_NEON)
+#endif // SIMSIMD_TARGET_ARM_SVE
+
+#if SIMSIMD_TARGET_ARM_NEON
+
+__attribute__((target("+simd"))) inline static simsimd_f32_t //
+simsimd_dot_f32x4_neon(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
+
     float32x4_t ab_vec = vdupq_n_f32(0);
     for (size_t i = 0; i != d; i += 4)
         ab_vec = vfmaq_f32(ab_vec, vld1q_f32(a + i), vld1q_f32(b + i));
     return 1 - vaddvq_f32(ab_vec);
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_cos_f16x4_neon(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
-#if defined(__ARM_NEON)
+__attribute__((target("+simd+fp16"))) inline static simsimd_f32_t //
+simsimd_cos_f16x4_neon(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
+
     float32x4_t ab_vec = vdupq_n_f32(0);
     float32x4_t a2_vec = vdupq_n_f32(0);
     float32x4_t b2_vec = vdupq_n_f32(0);
@@ -212,41 +253,36 @@ inline static simsimd_f32_t simsimd_cos_f16x4_neon(simsimd_f16_t const* a, simsi
     simsimd_f32_t a2 = vaddvq_f32(a2_vec);
     simsimd_f32_t b2 = vaddvq_f32(b2_vec);
     return 1 - ab / (sqrt(a2) * sqrt(b2));
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_cos_i8x16_neon(int8_t const* a, int8_t const* b, size_t d) {
-#if defined(__ARM_NEON)
+__attribute__((target("+simd"))) inline static simsimd_f32_t //
+simsimd_cos_i8x16_neon(int8_t const* a, int8_t const* b, size_t d) {
+
     int32x4_t ab_vec = vdupq_n_s32(0);
     int32x4_t a2_vec = vdupq_n_s32(0);
     int32x4_t b2_vec = vdupq_n_s32(0);
 
-#if 0 // This 128-bit `vdot_s32` intrinsic is often unavailable, so we use the 64-bit `vdot_s32`.
-    for (size_t i = 0; i != d; i += 16) {
-        int8x16_t a_vec = vld1q_s8(a + i);
-        int8x16_t b_vec = vld1q_s8(b + i);
-        ab_vec = vdotq_s32(ab_vec, a_vec, b_vec);
-        a2_vec = vdotq_s32(a2_vec, a_vec, a_vec);
-        b2_vec = vdotq_s32(b2_vec, b_vec, b_vec);
-    }
-#else
+    // This 128-bit `vdot_s32` intrinsic is often unavailable, so we use the 64-bit `vdot_s32`.
+    // for (size_t i = 0; i != d; i += 16) {
+    //     int8x16_t a_vec = vld1q_s8(a + i);
+    //     int8x16_t b_vec = vld1q_s8(b + i);
+    //     ab_vec = vdotq_s32(ab_vec, a_vec, b_vec);
+    //     a2_vec = vdotq_s32(a2_vec, a_vec, a_vec);
+    //     b2_vec = vdotq_s32(b2_vec, b_vec, b_vec);
+    // }
     for (size_t i = 0; i != d; i += 8) {
         int16x8_t a_vec = vmovl_s8(vld1_s8(a + i));
         int16x8_t b_vec = vmovl_s8(vld1_s8(b + i));
         int16x8_t ab_part_vec = vmulq_s16(a_vec, b_vec);
         int16x8_t a2_part_vec = vmulq_s16(a_vec, a_vec);
         int16x8_t b2_part_vec = vmulq_s16(b_vec, b_vec);
-        ab_vec = //
-            vaddq_s32(ab_vec, vaddq_s32(vmovl_s16(vget_high_s16(ab_part_vec)), vmovl_s16(vget_low_s16(ab_part_vec))));
-        a2_vec = //
-            vaddq_s32(a2_vec, vaddq_s32(vmovl_s16(vget_high_s16(a2_part_vec)), vmovl_s16(vget_low_s16(a2_part_vec))));
-        b2_vec = //
-            vaddq_s32(b2_vec, vaddq_s32(vmovl_s16(vget_high_s16(b2_part_vec)), vmovl_s16(vget_low_s16(b2_part_vec))));
+        ab_vec = vaddq_s32(ab_vec, vaddq_s32(vmovl_s16(vget_high_s16(ab_part_vec)), //
+                                             vmovl_s16(vget_low_s16(ab_part_vec))));
+        a2_vec = vaddq_s32(a2_vec, vaddq_s32(vmovl_s16(vget_high_s16(a2_part_vec)), //
+                                             vmovl_s16(vget_low_s16(a2_part_vec))));
+        b2_vec = vaddq_s32(b2_vec, vaddq_s32(vmovl_s16(vget_high_s16(b2_part_vec)), //
+                                             vmovl_s16(vget_low_s16(b2_part_vec))));
     }
-#endif
 
     int32x2_t ab_part = vadd_s32(vget_high_s32(ab_vec), vget_low_s32(ab_vec));
     int32_t ab = vget_lane_s32(vpadd_s32(ab_part, ab_part), 0);
@@ -255,14 +291,29 @@ inline static simsimd_f32_t simsimd_cos_i8x16_neon(int8_t const* a, int8_t const
     int32x2_t b2_part = vadd_s32(vget_high_s32(b2_vec), vget_low_s32(b2_vec));
     int32_t b2 = vget_lane_s32(vpadd_s32(b2_part, b2_part), 0);
     return 1 - ab / (sqrt(a2) * sqrt(b2));
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_cos_f32x4_neon(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
-#if defined(__ARM_NEON)
+__attribute__((target("+simd"))) inline static simsimd_f32_t //
+simsimd_l2sq_i8x16_neon(int8_t const* a, int8_t const* b, size_t d) {
+
+    int32x4_t d2_vec = vdupq_n_s32(0);
+    for (size_t i = 0; i != d; i += 8) {
+        int16x8_t a_vec = vmovl_s8(vld1_s8(a + i));
+        int16x8_t b_vec = vmovl_s8(vld1_s8(b + i));
+        int16x8_t d2_part_vec = vsubq_s16(a_vec, b_vec);
+        d2_part_vec = vmulq_s16(d2_part_vec, d2_part_vec);
+        d2_vec = vaddq_s32(d2_vec, vaddq_s32(vmovl_s16(vget_high_s16(d2_part_vec)), //
+                                             vmovl_s16(vget_low_s16(d2_part_vec))));
+    }
+
+    int32x2_t d2_part = vadd_s32(vget_high_s32(d2_vec), vget_low_s32(d2_vec));
+    int32_t d2 = vget_lane_s32(vpadd_s32(d2_part, d2_part), 0);
+    return d2;
+}
+
+__attribute__((target("+simd"))) inline static simsimd_f32_t //
+simsimd_cos_f32x4_neon(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
+
     float32x4_t ab_vec = vdupq_n_f32(0);
     float32x4_t a2_vec = vdupq_n_f32(0);
     float32x4_t b2_vec = vdupq_n_f32(0);
@@ -277,14 +328,11 @@ inline static simsimd_f32_t simsimd_cos_f32x4_neon(simsimd_f32_t const* a, simsi
     simsimd_f32_t a2 = vaddvq_f32(a2_vec);
     simsimd_f32_t b2 = vaddvq_f32(b2_vec);
     return 1 - ab / (sqrt(a2) * sqrt(b2));
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_hamming_b1x128_sve(uint8_t const* a, uint8_t const* b, size_t d) {
-#if defined(__ARM_NEON)
+__attribute__((target("+sve"))) inline static simsimd_f32_t //
+simsimd_hamming_b1x128_sve(uint8_t const* a, uint8_t const* b, size_t d) {
+
     /// Contains 16x 8-bit integers with running population count sums.
     uint8x16_t d_vec = vdupq_n_u8(0);
     for (size_t i = 0; i != d; i += 16) {
@@ -294,52 +342,30 @@ inline static simsimd_f32_t simsimd_hamming_b1x128_sve(uint8_t const* a, uint8_t
         d_vec = vaddq_u8(d_vec, vcntq_u8(a_xor_b_vec));
     }
     return 1 - vaddvq_u8(d_vec);
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
+#endif // SIMSIMD_TARGET_ARM_NEON
+#endif // SIMSIMD_TARGET_ARM
 
-inline static simsimd_f32_t simsimd_dot_f32x4_avx2(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
-#if defined(__AVX2__)
+#if SIMSIMD_TARGET_X86
+#if SIMSIMD_TARGET_X86_AVX2
+
+__attribute__((target("avx2")))                            //
+__attribute__((target("fma"))) inline static simsimd_f32_t //
+simsimd_dot_f32x4_avx2(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
     __m128 ab_vec = _mm_set1_ps(0);
     for (size_t i = 0; i != d; i += 4)
         ab_vec = _mm_fmadd_ps(_mm_loadu_ps(a + i), _mm_loadu_ps(b + i), ab_vec);
     ab_vec = _mm_hadd_ps(ab_vec, ab_vec);
     ab_vec = _mm_hadd_ps(ab_vec, ab_vec);
-    simsimd_f32i32_t ab_union;
+    union simsimd_f32i32_t ab_union;
     ab_union.i = _mm_cvtsi128_si32(_mm_castps_si128(ab_vec));
     return 1 - ab_union.f;
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_cos_f16x16_avx512(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
-#if defined(__AVX512F__)
-    __m512 ab_vec = _mm512_set1_ps(0);
-    __m512 a2_vec = _mm512_set1_ps(0);
-    __m512 b2_vec = _mm512_set1_ps(0);
-    for (size_t i = 0; i != d; i += 16) {
-        __m512 a_vec = _mm512_cvtxph_ps(_mm256_loadu_ph(a + i));
-        __m512 b_vec = _mm512_cvtxph_ps(_mm256_loadu_ph(b + i));
-        ab_vec = _mm512_fmadd_ps(a_vec, b_vec, ab_vec);
-        a2_vec = _mm512_fmadd_ps(a_vec, a_vec, a2_vec);
-        b2_vec = _mm512_fmadd_ps(b_vec, b_vec, b2_vec);
-    }
-    simsimd_f32_t ab = _mm512_reduce_add_ps(ab_vec);
-    simsimd_f32_t a2 = _mm512_reduce_add_ps(a2_vec);
-    simsimd_f32_t b2 = _mm512_reduce_add_ps(b2_vec);
-    return 1 - ab / (sqrt(a2) * sqrt(b2));
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
-}
+__attribute__((target("avx2")))                            //
+__attribute__((target("fma"))) inline static simsimd_f32_t //
+simsimd_cos_f32x4_avx2(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
 
-inline static simsimd_f32_t simsimd_cos_f32x4_avx2(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
-#if defined(__AVX2__)
     __m128 ab_vec = _mm_set1_ps(0);
     __m128 a2_vec = _mm_set1_ps(0);
     __m128 b2_vec = _mm_set1_ps(0);
@@ -356,18 +382,143 @@ inline static simsimd_f32_t simsimd_cos_f32x4_avx2(simsimd_f32_t const* a, simsi
     a2_vec = _mm_hadd_ps(a2_vec, a2_vec);
     b2_vec = _mm_hadd_ps(b2_vec, b2_vec);
     b2_vec = _mm_hadd_ps(b2_vec, b2_vec);
-    simsimd_f32i32_t ab_union = {_mm_cvtsi128_si32(_mm_castps_si128(ab_vec))};
-    simsimd_f32i32_t a2_union = {_mm_cvtsi128_si32(_mm_castps_si128(a2_vec))};
-    simsimd_f32i32_t b2_union = {_mm_cvtsi128_si32(_mm_castps_si128(b2_vec))};
+    union simsimd_f32i32_t ab_union = {_mm_cvtsi128_si32(_mm_castps_si128(ab_vec))};
+    union simsimd_f32i32_t a2_union = {_mm_cvtsi128_si32(_mm_castps_si128(a2_vec))};
+    union simsimd_f32i32_t b2_union = {_mm_cvtsi128_si32(_mm_castps_si128(b2_vec))};
     return 1 - ab_union.f / (sqrt(a2_union.f) * sqrt(b2_union.f));
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_hamming_b1x128_avx512(uint8_t const* a, uint8_t const* b, size_t d) {
-#if defined(__AVX512VPOPCNTDQ__)
+__attribute__((target("avx2")))                            //
+__attribute__((target("fma"))) inline static simsimd_f32_t //
+simsimd_l2sq_f32x4_avx2(simsimd_f32_t const* a, simsimd_f32_t const* b, size_t d) {
+    __m128 sum_vec = _mm_set1_ps(0);
+    for (size_t i = 0; i != d; i += 4) {
+        __m128 diff_vec = _mm_sub_ps(_mm_loadu_ps(a + i), _mm_loadu_ps(b + i));
+        sum_vec = _mm_fmadd_ps(diff_vec, diff_vec, sum_vec);
+    }
+    sum_vec = _mm_hadd_ps(sum_vec, sum_vec);
+    sum_vec = _mm_hadd_ps(sum_vec, sum_vec);
+    float result[1];
+    _mm_store_ss(result, sum_vec);
+    return result[0];
+}
+
+__attribute__((target("avx2")))                            //
+__attribute__((target("f16c")))                            //
+__attribute__((target("fma"))) inline static simsimd_f32_t //
+simsimd_dot_f16x8_avx2(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
+    __m128 ab_vec = _mm_set1_ps(0);
+    for (size_t i = 0; i != d; i += 8) {
+        __m128 a_vec = _mm_cvtph_ps(_mm_loadu_si128((__m128i const*)(a + i)));
+        __m128 b_vec = _mm_cvtph_ps(_mm_loadu_si128((__m128i const*)(b + i)));
+        ab_vec = _mm_fmadd_ps(a_vec, b_vec, ab_vec);
+    }
+    ab_vec = _mm_hadd_ps(ab_vec, ab_vec);
+    ab_vec = _mm_hadd_ps(ab_vec, ab_vec);
+    float result[1];
+    _mm_store_ss(result, ab_vec);
+    return 1 - result[0];
+}
+
+__attribute__((target("avx2")))                            //
+__attribute__((target("f16c")))                            //
+__attribute__((target("fma"))) inline static simsimd_f32_t //
+simsimd_cos_f16x8_avx2(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
+    __m128 ab_vec = _mm_set1_ps(0);
+    __m128 a2_vec = _mm_set1_ps(0);
+    __m128 b2_vec = _mm_set1_ps(0);
+    for (size_t i = 0; i != d; i += 8) {
+        __m128 a_vec = _mm_cvtph_ps(_mm_loadu_si128((__m128i const*)(a + i)));
+        __m128 b_vec = _mm_cvtph_ps(_mm_loadu_si128((__m128i const*)(b + i)));
+        ab_vec = _mm_fmadd_ps(a_vec, b_vec, ab_vec);
+        a2_vec = _mm_fmadd_ps(a_vec, a_vec, a2_vec);
+        b2_vec = _mm_fmadd_ps(b_vec, b_vec, b2_vec);
+    }
+    ab_vec = _mm_hadd_ps(ab_vec, ab_vec);
+    ab_vec = _mm_hadd_ps(ab_vec, ab_vec);
+    a2_vec = _mm_hadd_ps(a2_vec, a2_vec);
+    a2_vec = _mm_hadd_ps(a2_vec, a2_vec);
+    b2_vec = _mm_hadd_ps(b2_vec, b2_vec);
+    b2_vec = _mm_hadd_ps(b2_vec, b2_vec);
+    float ab_result[1], a2_result[1], b2_result[1];
+    _mm_store_ss(ab_result, ab_vec);
+    _mm_store_ss(a2_result, a2_vec);
+    _mm_store_ss(b2_result, b2_vec);
+    return 1 - ab_result[0] / (sqrt(a2_result[0]) * sqrt(b2_result[0]));
+}
+
+__attribute__((target("avx2")))                            //
+__attribute__((target("f16c")))                            //
+__attribute__((target("fma"))) inline static simsimd_f32_t //
+simsimd_l2sq_f16x8_avx2(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
+    __m128 sum_vec = _mm_set1_ps(0);
+    for (size_t i = 0; i != d; i += 8) {
+        __m128 a_vec = _mm_cvtph_ps(_mm_loadu_si128((__m128i const*)(a + i)));
+        __m128 b_vec = _mm_cvtph_ps(_mm_loadu_si128((__m128i const*)(b + i)));
+        __m128 diff_vec = _mm_sub_ps(a_vec, b_vec);
+        sum_vec = _mm_fmadd_ps(diff_vec, diff_vec, sum_vec);
+    }
+    sum_vec = _mm_hadd_ps(sum_vec, sum_vec);
+    sum_vec = _mm_hadd_ps(sum_vec, sum_vec);
+    float result[1];
+    _mm_store_ss(result, sum_vec);
+    return result[0];
+}
+
+#endif // SIMSIMD_TARGET_X86_AVX2
+
+#if SIMSIMD_TARGET_X86_AVX512
+
+__attribute__((target("avx512fp16")))                          //
+__attribute__((target("avx512f"))) inline static simsimd_f32_t //
+simsimd_dot_f16x16_avx512(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
+    __m512 ab_vec = _mm512_set1_ps(0);
+    for (size_t i = 0; i != d; i += 16) {
+        __m512 a_vec = _mm512_cvtxph_ps(_mm256_loadu_ph(a + i));
+        __m512 b_vec = _mm512_cvtxph_ps(_mm256_loadu_ph(b + i));
+        ab_vec = _mm512_fmadd_ps(a_vec, b_vec, ab_vec);
+    }
+    simsimd_f32_t ab = _mm512_reduce_add_ps(ab_vec);
+    return 1 - ab;
+}
+
+__attribute__((target("avx512fp16")))                          //
+__attribute__((target("avx512f"))) inline static simsimd_f32_t //
+simsimd_cos_f16x16_avx512(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
+    __m512 ab_vec = _mm512_set1_ps(0);
+    __m512 a2_vec = _mm512_set1_ps(0);
+    __m512 b2_vec = _mm512_set1_ps(0);
+    for (size_t i = 0; i != d; i += 16) {
+        __m512 a_vec = _mm512_cvtxph_ps(_mm256_loadu_ph(a + i));
+        __m512 b_vec = _mm512_cvtxph_ps(_mm256_loadu_ph(b + i));
+        ab_vec = _mm512_fmadd_ps(a_vec, b_vec, ab_vec);
+        a2_vec = _mm512_fmadd_ps(a_vec, a_vec, a2_vec);
+        b2_vec = _mm512_fmadd_ps(b_vec, b_vec, b2_vec);
+    }
+    simsimd_f32_t ab = _mm512_reduce_add_ps(ab_vec);
+    simsimd_f32_t a2 = _mm512_reduce_add_ps(a2_vec);
+    simsimd_f32_t b2 = _mm512_reduce_add_ps(b2_vec);
+    return 1 - ab / (sqrt(a2) * sqrt(b2));
+}
+
+__attribute__((target("avx512fp16")))                          //
+__attribute__((target("avx512f"))) inline static simsimd_f32_t //
+simsimd_l2sq_f16x16_avx512(simsimd_f16_t const* a, simsimd_f16_t const* b, size_t d) {
+    __m512 sum_vec = _mm512_set1_ps(0);
+    for (size_t i = 0; i != d; i += 16) {
+        __m512 a_vec = _mm512_cvtxph_ps(_mm256_loadu_ph(a + i));
+        __m512 b_vec = _mm512_cvtxph_ps(_mm256_loadu_ph(b + i));
+        __m512 diff_vec = _mm512_sub_ps(a_vec, b_vec);
+        sum_vec = _mm512_fmadd_ps(diff_vec, diff_vec, sum_vec);
+    }
+    simsimd_f32_t sum = _mm512_reduce_add_ps(sum_vec);
+    return sum;
+}
+
+__attribute__((target("avx512vpopcntdq")))                     //
+__attribute__((target("avx512vl")))                            //
+__attribute__((target("avx512f"))) inline static simsimd_f32_t //
+simsimd_hamming_b1x128_avx512(uint8_t const* a, uint8_t const* b, size_t d) {
     size_t words = d / 128;
     uint64_t const* a64 = (uint64_t const*)(a);
     uint64_t const* b64 = (uint64_t const*)(b);
@@ -380,20 +531,29 @@ inline static simsimd_f32_t simsimd_hamming_b1x128_avx512(uint8_t const* a, uint
                 _mm_xor_si128( //
                     _mm_load_si128((__m128i const*)(a64 + i)), _mm_load_si128((__m128i const*)(b64 + i)))));
     return _mm_cvtm64_si64(_mm_movepi64_pi64(d_vec)) + _mm_extract_epi64(d_vec, 1);
-#else
-    (void)a, (void)b, (void)d;
-    return -1;
-#endif
 }
 
-inline static simsimd_f32_t simsimd_tanimoto_b1x8_naive(uint8_t const* a, uint8_t const* b, size_t d) {
+#endif // SIMSIMD_TARGET_X86_AVX512
+#endif // SIMSIMD_TARGET_X86
+
+inline static simsimd_f32_t //
+simsimd_tanimoto_b1x8_naive(uint8_t const* a, uint8_t const* b, size_t d) {
     size_t and_count = 0, or_count = 0;
-    for (size_t i = 0; i != d; ++i)
-        and_count += popcount32(a[i] & b[i]), or_count += popcount32(a[i] | b[i]);
+    uint8_t const* a_end = a + d / 8;
+    // Misaligned prefix
+    for (; a != a_end && (size_t)(a) % 8 != 0; ++a, ++b)
+        and_count += popcount32(*a & *b), or_count += popcount32(*a | *b);
+    // Properly aligned body
+    for (; a + 8 <= a_end; a += 8, b += 8)
+        and_count += popcount64(*(uint64_t*)a & *(uint64_t*)b), or_count += popcount64(*(uint64_t*)a | *(uint64_t*)b);
+    // Misaligned suffix
+    for (; a != a_end; ++a, ++b)
+        and_count += popcount32(*a & *b), or_count += popcount32(*a | *b);
     return 1 - (simsimd_f32_t)(and_count) / or_count;
 }
 
 #undef popcount32
+#undef popcount64
 
 #ifdef __cplusplus
 }

package/simsimd/include/simsimd/simsimd_bio.h

@@ -0,0 +1,54 @@
+/**
+ *  @brief Collection of Biology-oriented Similarity Measures, SIMD-accelerated with SSE, AVX, NEON, SVE.
+ *
+ *  @author Ash Vardanian
+ *  @date August 8, 2023
+ */
+
+#pragma once
+
+#include <simsimd/simsimd_chem.h>
+
+#ifdef _MSC_VER
+#define hash32
+#define hash64
+#else
+#define hash32
+#define hash64
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  @brief  Used to compute the similarity of two DNA or RNA sequences in "TwoBit" form.
+ *
+ *  By design uses a separate bit-set for every string, expanding the compressed
+ *  representation into bitsets, and then computes the tanimoto distance on those.
+ *
+ *  Optimal `length_hash` should be derived from `max(a_length, b_length)`, as
+ */
+inline static simsimd_f32_t simsimd_tanimoto_twobit( //
+    uint8_t const* a_chars, uint8_t const* b_chars,  //
+    size_t a_length, size_t b_length,                //
+    uint8_t* a_hash, uint8_t* b_hash, size_t length_hash) {
+
+    // uint64 -> 32-gram
+    // uint32 -> 16-gram
+    uint64_t last_word = 0;
+    for (size_t i = 0; i + 8 <= a_length; i += 8) {
+        uint64_t a_word;
+        memcpy(&a_word, a_chars, 8);
+    }
+
+    size_t b_words = (b_length + 7) / 8;
+
+    return simsimd_tanimoto_b1x8_naive(a_hash, b_hash, length_hash);
+}
+
+#undef popcount64
+
+#ifdef __cplusplus
+}
+#endif