udxcms 1.0.10 → 1.0.12

package/dist/components/cmsComponents/wiki/lib/highlight/lib/languages/vbscript.js

@@ -2,25 +2,27 @@
  * @param {string} value
  * @returns {RegExp}
  * */
+
 /**
  * @param {RegExp | string } re
  * @returns {string}
  */
 function source(re) {
-    if (!re)
-        return null;
-    if (typeof re === "string")
-        return re;
-    return re.source;
+  if (!re) return null;
+  if (typeof re === "string") return re;
+
+  return re.source;
 }
+
 /**
  * @param {...(RegExp | string) } args
  * @returns {string}
  */
 function concat(...args) {
-    const joined = args.map((x) => source(x)).join("");
-    return joined;
+  const joined = args.map((x) => source(x)).join("");
+  return joined;
 }
+
 /**
  * Any of the passed expresssions may match
  *
@@ -29,9 +31,10 @@ function concat(...args) {
  * @returns {string}
  */
 function either(...args) {
-    const joined = '(' + args.map((x) => source(x)).join("|") + ")";
-    return joined;
+  const joined = '(' + args.map((x) => source(x)).join("|") + ")";
+  return joined;
 }
+
 /*
 Language: VBScript
 Description: VBScript ("Microsoft Visual Basic Scripting Edition") is an Active Scripting language developed by Microsoft that is modeled on Visual Basic.
@@ -40,57 +43,67 @@ Contributors: Michal Gabrukiewicz <mgabru@gmail.com>
 Website: https://en.wikipedia.org/wiki/VBScript
 Category: scripting
 */
+
 /** @type LanguageFn */
 function vbscript(hljs) {
-    const BUILT_IN_FUNCTIONS = ('lcase month vartype instrrev ubound setlocale getobject rgb getref string ' +
-        'weekdayname rnd dateadd monthname now day minute isarray cbool round formatcurrency ' +
-        'conversions csng timevalue second year space abs clng timeserial fixs len asc ' +
-        'isempty maths dateserial atn timer isobject filter weekday datevalue ccur isdate ' +
-        'instr datediff formatdatetime replace isnull right sgn array snumeric log cdbl hex ' +
-        'chr lbound msgbox ucase getlocale cos cdate cbyte rtrim join hour oct typename trim ' +
-        'strcomp int createobject loadpicture tan formatnumber mid ' +
-        'split  cint sin datepart ltrim sqr ' +
-        'time derived eval date formatpercent exp inputbox left ascw ' +
-        'chrw regexp cstr err').split(" ");
-    const BUILT_IN_OBJECTS = [
-        "server",
-        "response",
-        "request",
-        // take no arguments so can be called without ()
-        "scriptengine",
-        "scriptenginebuildversion",
-        "scriptengineminorversion",
-        "scriptenginemajorversion"
-    ];
-    const BUILT_IN_CALL = {
-        begin: concat(either(...BUILT_IN_FUNCTIONS), "\\s*\\("),
-        // relevance 0 because this is acting as a beginKeywords really
-        relevance: 0,
-        keywords: {
-            built_in: BUILT_IN_FUNCTIONS
+  const BUILT_IN_FUNCTIONS = ('lcase month vartype instrrev ubound setlocale getobject rgb getref string ' +
+  'weekdayname rnd dateadd monthname now day minute isarray cbool round formatcurrency ' +
+  'conversions csng timevalue second year space abs clng timeserial fixs len asc ' +
+  'isempty maths dateserial atn timer isobject filter weekday datevalue ccur isdate ' +
+  'instr datediff formatdatetime replace isnull right sgn array snumeric log cdbl hex ' +
+  'chr lbound msgbox ucase getlocale cos cdate cbyte rtrim join hour oct typename trim ' +
+  'strcomp int createobject loadpicture tan formatnumber mid ' +
+  'split  cint sin datepart ltrim sqr ' +
+  'time derived eval date formatpercent exp inputbox left ascw ' +
+  'chrw regexp cstr err').split(" ");
+  const BUILT_IN_OBJECTS = [
+    "server",
+    "response",
+    "request",
+    // take no arguments so can be called without ()
+    "scriptengine",
+    "scriptenginebuildversion",
+    "scriptengineminorversion",
+    "scriptenginemajorversion"
+  ];
+
+  const BUILT_IN_CALL = {
+    begin: concat(either(...BUILT_IN_FUNCTIONS), "\\s*\\("),
+    // relevance 0 because this is acting as a beginKeywords really
+    relevance:0,
+    keywords: {
+      built_in: BUILT_IN_FUNCTIONS
+    }
+  };
+
+  return {
+    name: 'VBScript',
+    aliases: ['vbs'],
+    case_insensitive: true,
+    keywords: {
+      keyword:
+        'call class const dim do loop erase execute executeglobal exit for each next function ' +
+        'if then else on error option explicit new private property let get public randomize ' +
+        'redim rem select case set stop sub while wend with end to elseif is or xor and not ' +
+        'class_initialize class_terminate default preserve in me byval byref step resume goto',
+      built_in: BUILT_IN_OBJECTS,
+      literal:
+        'true false null nothing empty'
+    },
+    illegal: '//',
+    contains: [
+      BUILT_IN_CALL,
+      hljs.inherit(hljs.QUOTE_STRING_MODE, {contains: [{begin: '""'}]}),
+      hljs.COMMENT(
+        /'/,
+        /$/,
+        {
+          relevance: 0
         }
-    };
-    return {
-        name: 'VBScript',
-        aliases: ['vbs'],
-        case_insensitive: true,
-        keywords: {
-            keyword: 'call class const dim do loop erase execute executeglobal exit for each next function ' +
-                'if then else on error option explicit new private property let get public randomize ' +
-                'redim rem select case set stop sub while wend with end to elseif is or xor and not ' +
-                'class_initialize class_terminate default preserve in me byval byref step resume goto',
-            built_in: BUILT_IN_OBJECTS,
-            literal: 'true false null nothing empty'
-        },
-        illegal: '//',
-        contains: [
-            BUILT_IN_CALL,
-            hljs.inherit(hljs.QUOTE_STRING_MODE, { contains: [{ begin: '""' }] }),
-            hljs.COMMENT(/'/, /$/, {
-                relevance: 0
-            }),
-            hljs.C_NUMBER_MODE
-        ]
-    };
+      ),
+      hljs.C_NUMBER_MODE
+    ]
+  };
 }
+
 module.exports = vbscript;

package/dist/components/cmsComponents/wiki/lib/highlight/lib/languages/verilog.js

@@ -5,120 +5,127 @@ Contributors: Boone Severson <boone.severson@gmail.com>
 Description: Verilog is a hardware description language used in electronic design automation to describe digital and mixed-signal systems. This highlighter supports Verilog and SystemVerilog through IEEE 1800-2012.
 Website: http://www.verilog.com
 */
+
 function verilog(hljs) {
-    const SV_KEYWORDS = {
-        $pattern: /[\w\$]+/,
-        keyword: 'accept_on alias always always_comb always_ff always_latch and assert assign ' +
-            'assume automatic before begin bind bins binsof bit break buf|0 bufif0 bufif1 ' +
-            'byte case casex casez cell chandle checker class clocking cmos config const ' +
-            'constraint context continue cover covergroup coverpoint cross deassign default ' +
-            'defparam design disable dist do edge else end endcase endchecker endclass ' +
-            'endclocking endconfig endfunction endgenerate endgroup endinterface endmodule ' +
-            'endpackage endprimitive endprogram endproperty endspecify endsequence endtable ' +
-            'endtask enum event eventually expect export extends extern final first_match for ' +
-            'force foreach forever fork forkjoin function generate|5 genvar global highz0 highz1 ' +
-            'if iff ifnone ignore_bins illegal_bins implements implies import incdir include ' +
-            'initial inout input inside instance int integer interconnect interface intersect ' +
-            'join join_any join_none large let liblist library local localparam logic longint ' +
-            'macromodule matches medium modport module nand negedge nettype new nexttime nmos ' +
-            'nor noshowcancelled not notif0 notif1 or output package packed parameter pmos ' +
-            'posedge primitive priority program property protected pull0 pull1 pulldown pullup ' +
-            'pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos ' +
-            'real realtime ref reg reject_on release repeat restrict return rnmos rpmos rtran ' +
-            'rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with scalared ' +
-            'sequence shortint shortreal showcancelled signed small soft solve specify specparam ' +
-            'static string strong strong0 strong1 struct super supply0 supply1 sync_accept_on ' +
-            'sync_reject_on table tagged task this throughout time timeprecision timeunit tran ' +
-            'tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unique0 ' +
-            'unsigned until until_with untyped use uwire var vectored virtual void wait wait_order ' +
-            'wand weak weak0 weak1 while wildcard wire with within wor xnor xor',
-        literal: 'null',
-        built_in: '$finish $stop $exit $fatal $error $warning $info $realtime $time $printtimescale ' +
-            '$bitstoreal $bitstoshortreal $itor $signed $cast $bits $stime $timeformat ' +
-            '$realtobits $shortrealtobits $rtoi $unsigned $asserton $assertkill $assertpasson ' +
-            '$assertfailon $assertnonvacuouson $assertoff $assertcontrol $assertpassoff ' +
-            '$assertfailoff $assertvacuousoff $isunbounded $sampled $fell $changed $past_gclk ' +
-            '$fell_gclk $changed_gclk $rising_gclk $steady_gclk $coverage_control ' +
-            '$coverage_get $coverage_save $set_coverage_db_name $rose $stable $past ' +
-            '$rose_gclk $stable_gclk $future_gclk $falling_gclk $changing_gclk $display ' +
-            '$coverage_get_max $coverage_merge $get_coverage $load_coverage_db $typename ' +
-            '$unpacked_dimensions $left $low $increment $clog2 $ln $log10 $exp $sqrt $pow ' +
-            '$floor $ceil $sin $cos $tan $countbits $onehot $isunknown $fatal $warning ' +
-            '$dimensions $right $high $size $asin $acos $atan $atan2 $hypot $sinh $cosh ' +
-            '$tanh $asinh $acosh $atanh $countones $onehot0 $error $info $random ' +
-            '$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson ' +
-            '$dist_t $dist_uniform $q_initialize $q_remove $q_exam $async$and$array ' +
-            '$async$nand$array $async$or$array $async$nor$array $sync$and$array ' +
-            '$sync$nand$array $sync$or$array $sync$nor$array $q_add $q_full $psprintf ' +
-            '$async$and$plane $async$nand$plane $async$or$plane $async$nor$plane ' +
-            '$sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane $system ' +
-            '$display $displayb $displayh $displayo $strobe $strobeb $strobeh $strobeo ' +
-            '$write $readmemb $readmemh $writememh $value$plusargs ' +
-            '$dumpvars $dumpon $dumplimit $dumpports $dumpportson $dumpportslimit ' +
-            '$writeb $writeh $writeo $monitor $monitorb $monitorh $monitoro $writememb ' +
-            '$dumpfile $dumpoff $dumpall $dumpflush $dumpportsoff $dumpportsall ' +
-            '$dumpportsflush $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo ' +
-            '$fstrobe $fstrobeb $fstrobeh $fstrobeo $swrite $swriteb $swriteh ' +
-            '$swriteo $fscanf $fread $fseek $fflush $feof $fopen $fwrite $fwriteb ' +
-            '$fwriteh $fwriteo $fmonitor $fmonitorb $fmonitorh $fmonitoro $sformat ' +
-            '$sformatf $fgetc $ungetc $fgets $sscanf $rewind $ftell $ferror'
-    };
-    return {
-        name: 'Verilog',
-        aliases: [
-            'v',
-            'sv',
-            'svh'
-        ],
-        case_insensitive: false,
-        keywords: SV_KEYWORDS,
-        contains: [
-            hljs.C_BLOCK_COMMENT_MODE,
-            hljs.C_LINE_COMMENT_MODE,
-            hljs.QUOTE_STRING_MODE,
-            {
-                className: 'number',
-                contains: [hljs.BACKSLASH_ESCAPE],
-                variants: [
-                    {
-                        begin: '\\b((\\d+\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+)'
-                    },
-                    {
-                        begin: '\\B((\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+)'
-                    },
-                    {
-                        begin: '\\b([0-9_])+',
-                        relevance: 0
-                    }
-                ]
-            },
-            /* parameters to instances */
-            {
-                className: 'variable',
-                variants: [
-                    {
-                        begin: '#\\((?!parameter).+\\)'
-                    },
-                    {
-                        begin: '\\.\\w+',
-                        relevance: 0
-                    }
-                ]
-            },
-            {
-                className: 'meta',
-                begin: '`',
-                end: '$',
-                keywords: {
-                    'meta-keyword': 'define __FILE__ ' +
-                        '__LINE__ begin_keywords celldefine default_nettype define ' +
-                        'else elsif end_keywords endcelldefine endif ifdef ifndef ' +
-                        'include line nounconnected_drive pragma resetall timescale ' +
-                        'unconnected_drive undef undefineall'
-                },
-                relevance: 0
-            }
+  const SV_KEYWORDS = {
+    $pattern: /[\w\$]+/,
+    keyword:
+      'accept_on alias always always_comb always_ff always_latch and assert assign ' +
+      'assume automatic before begin bind bins binsof bit break buf|0 bufif0 bufif1 ' +
+      'byte case casex casez cell chandle checker class clocking cmos config const ' +
+      'constraint context continue cover covergroup coverpoint cross deassign default ' +
+      'defparam design disable dist do edge else end endcase endchecker endclass ' +
+      'endclocking endconfig endfunction endgenerate endgroup endinterface endmodule ' +
+      'endpackage endprimitive endprogram endproperty endspecify endsequence endtable ' +
+      'endtask enum event eventually expect export extends extern final first_match for ' +
+      'force foreach forever fork forkjoin function generate|5 genvar global highz0 highz1 ' +
+      'if iff ifnone ignore_bins illegal_bins implements implies import incdir include ' +
+      'initial inout input inside instance int integer interconnect interface intersect ' +
+      'join join_any join_none large let liblist library local localparam logic longint ' +
+      'macromodule matches medium modport module nand negedge nettype new nexttime nmos ' +
+      'nor noshowcancelled not notif0 notif1 or output package packed parameter pmos ' +
+      'posedge primitive priority program property protected pull0 pull1 pulldown pullup ' +
+      'pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos ' +
+      'real realtime ref reg reject_on release repeat restrict return rnmos rpmos rtran ' +
+      'rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with scalared ' +
+      'sequence shortint shortreal showcancelled signed small soft solve specify specparam ' +
+      'static string strong strong0 strong1 struct super supply0 supply1 sync_accept_on ' +
+      'sync_reject_on table tagged task this throughout time timeprecision timeunit tran ' +
+      'tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unique0 ' +
+      'unsigned until until_with untyped use uwire var vectored virtual void wait wait_order ' +
+      'wand weak weak0 weak1 while wildcard wire with within wor xnor xor',
+    literal:
+      'null',
+    built_in:
+      '$finish $stop $exit $fatal $error $warning $info $realtime $time $printtimescale ' +
+      '$bitstoreal $bitstoshortreal $itor $signed $cast $bits $stime $timeformat ' +
+      '$realtobits $shortrealtobits $rtoi $unsigned $asserton $assertkill $assertpasson ' +
+      '$assertfailon $assertnonvacuouson $assertoff $assertcontrol $assertpassoff ' +
+      '$assertfailoff $assertvacuousoff $isunbounded $sampled $fell $changed $past_gclk ' +
+      '$fell_gclk $changed_gclk $rising_gclk $steady_gclk $coverage_control ' +
+      '$coverage_get $coverage_save $set_coverage_db_name $rose $stable $past ' +
+      '$rose_gclk $stable_gclk $future_gclk $falling_gclk $changing_gclk $display ' +
+      '$coverage_get_max $coverage_merge $get_coverage $load_coverage_db $typename ' +
+      '$unpacked_dimensions $left $low $increment $clog2 $ln $log10 $exp $sqrt $pow ' +
+      '$floor $ceil $sin $cos $tan $countbits $onehot $isunknown $fatal $warning ' +
+      '$dimensions $right $high $size $asin $acos $atan $atan2 $hypot $sinh $cosh ' +
+      '$tanh $asinh $acosh $atanh $countones $onehot0 $error $info $random ' +
+      '$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson ' +
+      '$dist_t $dist_uniform $q_initialize $q_remove $q_exam $async$and$array ' +
+      '$async$nand$array $async$or$array $async$nor$array $sync$and$array ' +
+      '$sync$nand$array $sync$or$array $sync$nor$array $q_add $q_full $psprintf ' +
+      '$async$and$plane $async$nand$plane $async$or$plane $async$nor$plane ' +
+      '$sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane $system ' +
+      '$display $displayb $displayh $displayo $strobe $strobeb $strobeh $strobeo ' +
+      '$write $readmemb $readmemh $writememh $value$plusargs ' +
+      '$dumpvars $dumpon $dumplimit $dumpports $dumpportson $dumpportslimit ' +
+      '$writeb $writeh $writeo $monitor $monitorb $monitorh $monitoro $writememb ' +
+      '$dumpfile $dumpoff $dumpall $dumpflush $dumpportsoff $dumpportsall ' +
+      '$dumpportsflush $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo ' +
+      '$fstrobe $fstrobeb $fstrobeh $fstrobeo $swrite $swriteb $swriteh ' +
+      '$swriteo $fscanf $fread $fseek $fflush $feof $fopen $fwrite $fwriteb ' +
+      '$fwriteh $fwriteo $fmonitor $fmonitorb $fmonitorh $fmonitoro $sformat ' +
+      '$sformatf $fgetc $ungetc $fgets $sscanf $rewind $ftell $ferror'
+  };
+
+  return {
+    name: 'Verilog',
+    aliases: [
+      'v',
+      'sv',
+      'svh'
+    ],
+    case_insensitive: false,
+    keywords: SV_KEYWORDS,
+    contains: [
+      hljs.C_BLOCK_COMMENT_MODE,
+      hljs.C_LINE_COMMENT_MODE,
+      hljs.QUOTE_STRING_MODE,
+      {
+        className: 'number',
+        contains: [ hljs.BACKSLASH_ESCAPE ],
+        variants: [
+          {
+            begin: '\\b((\\d+\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+)'
+          },
+          {
+            begin: '\\B((\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+)'
+          },
+          {
+            begin: '\\b([0-9_])+',
+            relevance: 0
+          }
         ]
-    };
+      },
+      /* parameters to instances */
+      {
+        className: 'variable',
+        variants: [
+          {
+            begin: '#\\((?!parameter).+\\)'
+          },
+          {
+            begin: '\\.\\w+',
+            relevance: 0
+          }
+        ]
+      },
+      {
+        className: 'meta',
+        begin: '`',
+        end: '$',
+        keywords: {
+          'meta-keyword':
+            'define __FILE__ ' +
+            '__LINE__ begin_keywords celldefine default_nettype define ' +
+            'else elsif end_keywords endcelldefine endif ifdef ifndef ' +
+            'include line nounconnected_drive pragma resetall timescale ' +
+            'unconnected_drive undef undefineall'
+        },
+        relevance: 0
+      }
+    ]
+  };
 }
+
 module.exports = verilog;

package/dist/components/cmsComponents/wiki/lib/highlight/lib/languages/vhdl.js

@@ -5,59 +5,67 @@ Contributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guilla
 Description: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.
 Website: https://en.wikipedia.org/wiki/VHDL
 */
+
 function vhdl(hljs) {
-    // Regular expression for VHDL numeric literals.
-    // Decimal literal:
-    const INTEGER_RE = '\\d(_|\\d)*';
-    const EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;
-    const DECIMAL_LITERAL_RE = INTEGER_RE + '(\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';
-    // Based literal:
-    const BASED_INTEGER_RE = '\\w+';
-    const BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';
-    const NUMBER_RE = '\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';
-    return {
-        name: 'VHDL',
-        case_insensitive: true,
-        keywords: {
-            keyword: 'abs access after alias all and architecture array assert assume assume_guarantee attribute ' +
-                'begin block body buffer bus case component configuration constant context cover disconnect ' +
-                'downto default else elsif end entity exit fairness file for force function generate ' +
-                'generic group guarded if impure in inertial inout is label library linkage literal ' +
-                'loop map mod nand new next nor not null of on open or others out package parameter port ' +
-                'postponed procedure process property protected pure range record register reject ' +
-                'release rem report restrict restrict_guarantee return rol ror select sequence ' +
-                'severity shared signal sla sll sra srl strong subtype then to transport type ' +
-                'unaffected units until use variable view vmode vprop vunit wait when while with xnor xor',
-            built_in: 'boolean bit character ' +
-                'integer time delay_length natural positive ' +
-                'string bit_vector file_open_kind file_open_status ' +
-                'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' +
-                'std_ulogic std_ulogic_vector unresolved_unsigned u_unsigned unresolved_signed u_signed ' +
-                'real_vector time_vector',
-            literal: 'false true note warning error failure ' + // severity_level
-                'line text side width' // textio
-        },
-        illegal: /\{/,
-        contains: [
-            hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.
-            hljs.COMMENT('--', '$'),
-            hljs.QUOTE_STRING_MODE,
-            {
-                className: 'number',
-                begin: NUMBER_RE,
-                relevance: 0
-            },
-            {
-                className: 'string',
-                begin: '\'(U|X|0|1|Z|W|L|H|-)\'',
-                contains: [hljs.BACKSLASH_ESCAPE]
-            },
-            {
-                className: 'symbol',
-                begin: '\'[A-Za-z](_?[A-Za-z0-9])*',
-                contains: [hljs.BACKSLASH_ESCAPE]
-            }
-        ]
-    };
+  // Regular expression for VHDL numeric literals.
+
+  // Decimal literal:
+  const INTEGER_RE = '\\d(_|\\d)*';
+  const EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;
+  const DECIMAL_LITERAL_RE = INTEGER_RE + '(\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';
+  // Based literal:
+  const BASED_INTEGER_RE = '\\w+';
+  const BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';
+
+  const NUMBER_RE = '\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';
+
+  return {
+    name: 'VHDL',
+    case_insensitive: true,
+    keywords: {
+      keyword:
+        'abs access after alias all and architecture array assert assume assume_guarantee attribute ' +
+        'begin block body buffer bus case component configuration constant context cover disconnect ' +
+        'downto default else elsif end entity exit fairness file for force function generate ' +
+        'generic group guarded if impure in inertial inout is label library linkage literal ' +
+        'loop map mod nand new next nor not null of on open or others out package parameter port ' +
+        'postponed procedure process property protected pure range record register reject ' +
+        'release rem report restrict restrict_guarantee return rol ror select sequence ' +
+        'severity shared signal sla sll sra srl strong subtype then to transport type ' +
+        'unaffected units until use variable view vmode vprop vunit wait when while with xnor xor',
+      built_in:
+        'boolean bit character ' +
+        'integer time delay_length natural positive ' +
+        'string bit_vector file_open_kind file_open_status ' +
+        'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' +
+        'std_ulogic std_ulogic_vector unresolved_unsigned u_unsigned unresolved_signed u_signed ' +
+        'real_vector time_vector',
+      literal:
+        'false true note warning error failure ' + // severity_level
+        'line text side width' // textio
+    },
+    illegal: /\{/,
+    contains: [
+      hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.
+      hljs.COMMENT('--', '$'),
+      hljs.QUOTE_STRING_MODE,
+      {
+        className: 'number',
+        begin: NUMBER_RE,
+        relevance: 0
+      },
+      {
+        className: 'string',
+        begin: '\'(U|X|0|1|Z|W|L|H|-)\'',
+        contains: [ hljs.BACKSLASH_ESCAPE ]
+      },
+      {
+        className: 'symbol',
+        begin: '\'[A-Za-z](_?[A-Za-z0-9])*',
+        contains: [ hljs.BACKSLASH_ESCAPE ]
+      }
+    ]
+  };
 }
+
 module.exports = vhdl;