tsci-agent 0.1.0

package/dist/skill/CHECKLIST.md

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+# Pre-export / pre-fab checklist
+
+Connectivity
+- All intended nets are connected; no floating power pins.
+- No accidental shorts between rails.
+
+Footprints and pinout
+- Footprints match intended package size and orientation.
+- Pin 1 orientation is correct for polarized parts.
+
+PCB constraints
+- Board outline, mounting holes, and keepouts are correct.
+- Trace width/clearance meets target fab rules.
+
+Schematic hygiene
+- Key nets labeled; power/ground clear.
+- Reference designators present and stable.
+
+Assembly readiness
+- Use `supplierPartNumbers` for critical parts / specific suppliers.
+- Mark hand-soldered parts with `doNotPlace`.
+
+Build/export
+- `tsci build` succeeds without unexpected errors.
+- Exported artifacts match your needs (SVG, netlist, DSN, 3D, KiCad library).
+- Fabrication zip contains Gerbers, BOM CSV, Pick'n'Place CSV.

package/dist/skill/CLI.md

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+# tsci CLI primer
+
+Prereqs
+- Node.js or Bun
+- Install the tscircuit CLI (global install):
+  - npm: `npm install -g tscircuit`
+  - bun: `bun install --global tscircuit`
+
+Core commands
+
+1) Create / bootstrap a project
+- `tsci init` (interactive)
+- `tsci init -y` (accept defaults)
+
+Typical output includes:
+- `index.circuit.tsx` (main circuit entrypoint)
+- `package.json`, `tsconfig.json`
+- `tscircuit.config.json`
+
+2) Preview locally (interactive)
+- `tsci dev`
+- Opens a local preview server (commonly https://localhost:3020)
+- Note: For AI-driven iteration, prefer `tsci build` over `tsci dev`—dev mode is primarily for interactive visual feedback.
+
+3) Search the ecosystem
+- `tsci search "<query>"`
+  - Finds footprints, components, and packages across multiple sources
+
+Search flags:
+- `--jlcpcb` (or `--lcsc`) – Search JLCPCB/LCSC components by name or part number
+- `--kicad` – Search KiCad footprint library
+- `--tscircuit` – Search tscircuit registry packages
+- `--json` – Return machine-readable JSON output instead of plain text
+
+Examples:
+```bash
+# Search JLCPCB for microcontrollers
+tsci search --jlcpcb "ATmega328"
+# Output: ATMEGA328P-AU (C14877) - stock: 20,226
+
+# Search JLCPCB by part number
+tsci search --jlcpcb "C14877"
+
+# Search JLCPCB for Micro-USB connectors
+tsci search --jlcpcb "micro usb connector"
+
+# Search KiCad footprints
+tsci search --kicad "QFP-32"
+# Output: kicad:Package_QFP/LQFP-32_5x5mm_P0.5mm
+
+# Search KiCad for SMD resistor footprints
+tsci search --kicad "0402"
+
+# Search tscircuit registry for existing projects
+tsci search --tscircuit "LED"
+# Output: seveibar/usb-c-flashlight - Stars: 5
+
+# Search without flags (searches all sources)
+tsci search "ESP32"
+
+# Search with JSON output (useful for scripts)
+tsci search --jlcpcb "ATmega328" --json
+# Example output:
+# {
+#   "results": [
+#     {
+#       "source": "jlcpcb",
+#       "name": "ATMEGA328P-AU",
+#       "part_number": "C14877",
+#       "description": "Microcontroller Unit, 8-bit AVR",
+#       "manufacturer": "Microchip Tech",
+#       "stock": 20226,
+#       "price": "0.735"
+#     }
+#   ]
+# }
+```
+
+4) Add existing registry packages to your project
+- `tsci add <author/pkg>`
+  - Use when a reusable tscircuit package already exists in the registry
+  - Example: `tsci add seveibar/PICO_W`
+  - Imports look like: `import { PICO_W } from "@tsci/seveibar.PICO_W"`
+  - The `@tsci/` scope with dot notation (`author.pkg`) is the registry convention
+
+5) Import components (e.g., from JLCPCB)
+- `tsci import <query>`
+  - Use when you need to bring a specific part into your project
+  - Searches both the tscircuit registry and JLCPCB parts database
+  - Opens an interactive picker to select and import the component
+  - For USB-C connectors, prefer `<connector standard="usb_c" />` directly instead of importing from JLCPCB
+
+Workflow:
+```bash
+# First, search to find the part number
+tsci search --jlcpcb "ATmega328"
+# Output: ATMEGA328P-AU (C14877) - stock: 20,226
+
+# Then import using the part number or name
+tsci import "C14877"
+# or
+tsci import "ATmega328"
+```
+
+The interactive picker shows:
+- Registry packages (already wrapped by other users): `author/PART_NAME`
+- JLCPCB parts (raw import): `[jlcpcb] PART_NAME (CXXXXXX)`
+
+Tip: If someone has already imported the part, prefer the registry version—it may have better pin mappings or schematic symbols.
+
+6) Build (generate circuit.json)
+
+Before placement checks or builds, run a netlist check first:
+- `tsci check netlist [file]`
+
+Then check schematic placement:
+- `tsci check schematic-placement [file]`
+
+Then generate a placement snapshot before routing checks:
+- `tsci snapshot`
+
+Then check placement of the entire board or a specific component:
+- `tsci check placement [file] [refdes]`
+
+After placement, identify potential congestion before routing:
+- `tsci check routing-difficulty [file]`
+
+- `tsci build` (auto-detects entrypoint)
+- `tsci build path/to/file.circuit.tsx`
+
+Notes
+- If no path is provided, `tsci build` searches for `index.circuit.tsx` or `mainEntrypoint` in `tscircuit.config.json`.
+- `*.circuit.tsx` files are built automatically.
+- Outputs go to `dist/`.
+
+Useful flags
+- `--all-images` (emit PCB/schematic/3D renders into `dist/`)
+
+DRC (Design Rule Check)
+- DRC errors are often reported but can frequently be ignored during development.
+- Focus on getting the circuit correct first; DRC violations can be addressed later when preparing for manufacturing.
+
+7) Export (SVG/netlist/3D/library)
+- `tsci export <file> -f <format>`
+
+Common formats
+- `schematic-svg`
+- `pcb-svg`
+- `readable-netlist`
+- `specctra-dsn`
+- `gltf` / `glb`
+- `kicad-library`
+
+8) Visual snapshots for analysis and verification
+- `tsci snapshot` generates visual outputs (schematic/PCB, optionally 3D) and writes/overwrites snapshots by default.
+- Use these visuals to inspect placement, orientation, and overall circuit understanding during iteration.
+- `tsci snapshot --test` switches to regression-test mode: it fails on visual diffs and does **not** overwrite snapshots.
+- `tsci snapshot --pcb-only` generates only PCB visuals, which is especially useful for placement-focused iteration.
+- `tsci snapshot --3d` includes 3D snapshots in the output.
+
+Recommended pattern:
+```bash
+# During development: generate fresh visuals for analysis and review
+tsci snapshot
+
+# During placement-heavy iterations: focus only on PCB output
+tsci snapshot --pcb-only
+
+# In CI/regression checks: detect unexpected visual changes without overwriting
+tsci snapshot --test
+```
+
+9) Auth / publish
+- `tsci login` (browser-based)
+- `tsci push` (publish package)
+- `tsci auth print-token`
+
+Guidance
+- Prefer `tsci --help` and `tsci <cmd> --help` when unsure about flags.
+- Avoid `tsci push` unless the user explicitly asks to publish.

package/dist/skill/LICENSE

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+MIT License
+
+Copyright (c) 2026 tscircuit
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

package/dist/skill/README.md

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+# tscircuit Agent Skill
+
+This folder is intended to be used as an agent Skill.
+
+Install as:
+
+- `npx skills add tscircuit/skill`
+
+The canonical entrypoint is `SKILL.md`.
+
+## Contents
+
+- `SKILL.md` – Main skill definition (frontmatter + instructions)
+- `CLI.md` – tsci CLI command reference
+- `SYNTAX.md` – tscircuit JSX syntax primer
+- `WORKFLOW.md` – Recommended development workflow
+- `CHECKLIST.md` – Pre-export/pre-fab checklist
+- `templates/` – Reference TSX examples (copy into your project)
+- `scripts/` – Helper shell scripts
+
+## Templates
+
+The files in `templates/` are **reference examples**—they are not standalone runnable projects. To use them:
+
+1. Create a tscircuit project: `tsci init`
+2. Copy the desired template into your project
+3. Install any additional dependencies (e.g., `npm install @tscircuit/common` for Arduino/RPi templates)
+4. Run `tsci build` or `tsci dev`
+
+## License
+
+See `LICENSE` for terms.

package/dist/skill/SKILL.md

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+---
+name: tscircuit
+description: Build, modify, and debug tscircuit (React/TypeScript) PCB designs. Use when working with tsci CLI (init/dev/search/add/import/build/export/snapshot/push), choosing footprints, placing parts, wiring nets/traces, or preparing fabrication outputs (Gerbers/BOM/PnP).
+allowed-tools: Read, Write, Grep, Glob, Bash
+---
+
+# tscircuit
+
+You are helping the user design electronics using tscircuit (React/TypeScript) and the `tsci` CLI.
+
+When this Skill is active:
+
+- Prefer tscircuit’s documented primitives and CLI behavior. If something is unclear, confirm by:
+  - Reading local files in the repo (e.g., `tscircuit.config.json`, `index.circuit.tsx`, `package.json`)
+  - Running `tsci --help` or the specific subcommand’s `--help`
+- Avoid “inventing” JSX props or CLI flags.
+
+## Default workflow
+
+1) Clarify requirements (if not already given)
+- Board form factor / size constraints
+- Power sources and voltage rails
+- I/O: connectors, headers, mounting holes, mechanical constraints
+- Target manufacturer constraints (trace/space, assembly, supplier)
+
+2) Choose a starting point
+- If the repo is not a tscircuit project, recommend:
+  - Install CLI, then `tsci init` to bootstrap a project.
+- If a form-factor template is appropriate (Arduino Shield, Raspberry Pi HAT, etc.), prefer `@tscircuit/common` templates.
+
+3) Find and install components
+- Use `tsci search "<query>"` to discover footprints and tscircuit registry packages.
+- For USB-C receptacles/connectors, prefer builtin syntax with `<connector standard="usb_c" />` instead of importing from JLCPCB.
+- Use one of:
+  - `tsci add <author/pkg>` for registry packages (installs `@tsci/*` packages)
+  - `tsci import <query>` when you need to import a component from JLCPCB or the registry.
+
+4) Write/modify TSX circuit code
+- Keep circuits as a default-exported function that returns JSX.
+- Use layout props intentionally:
+  - PCB: `pcbX`, `pcbY`, `pcbRotation`, `layer`
+  - Schematic: `schX`, `schY`, `schRotation`, `schOrientation`
+- On large projects (5+ components), use `<schematicsection />` to group components by function (e.g. "Power", "MCU", "IO"). This is one of the most important things for schematic readability. Assign each component a `schSectionName` and manually position all members of a section in close proximity using `schX`/`schY`.
+- Use `<trace />` for connectivity; prefer net connections (`net.GND`, `net.VCC`, etc.) for power/ground.
+
+5) Build and iterate
+- Run `tsci check netlist` before `tsci check schematic-placement`, `tsci check placement`, and `tsci build` to catch connectivity issues early.
+- Use `tsci check schematic-placement` to validate schematic-side placement before checking PCB placement.
+- Do not finalize unless both `tsci check schematic-placement` and `tsci check placement` pass with no actionable placement violations; if violations exist, fix layout and rerun until clean.
+- Use `tsci check trace-length` to check for long straight line distances (before routing) or long routes (after routing)
+- Run `tsci build --pcb-png [file]` to inspect placement before checking routing.
+- Run `tsci check routing-difficulty` after placement to identify potential areas of congestion.
+- Run `tsci build` to compile and validate the circuit.
+- DRC (Design Rule Check) errors can often be ignored during development—focus on getting the circuit correct first.
+- If routing struggles, reduce density, use `<group />` for sub-layouts, or change autorouter settings.
+- Use `tsci dev` only when you need interactive visual feedback (not typical for AI-driven iteration).
+
+6) Validate and export
+- Run `tsci check netlist` before `tsci check schematic-placement`, `tsci check placement`, and `tsci build` when preparing to share/publish.
+- Run `tsci build` (and optionally `tsci snapshot`) before sharing/publishing.
+- Use `tsci export` for SVG/netlist/DSN/3D/library outputs.
+- For manufacturing, obtain fabrication outputs (Gerbers/BOM/PnP) from the export UI after `tsci dev`.
+
+## Safety and non-goals
+
+- Treat electrical safety, regulatory compliance, and manufacturability as user-owned responsibilities.
+- Do not publish (`tsci push`) or place orders unless the user explicitly requests it.
+
+## Local references bundled with this Skill
+
+- CLI primer: `CLI.md`
+- Syntax primer: `SYNTAX.md`
+- Workflow patterns: `WORKFLOW.md`
+- Pre-export checklist: `CHECKLIST.md`
+- Ready-to-copy templates: `templates/`
+- Helper scripts: `scripts/`
+
+## Builtin Elements
+
+- [`<analogsimulation />`](./elements/analogsimulation.md)
+- [`<battery />`](./elements/battery.md)
+- [`<board />`](./elements/board.md)
+- [`<breakout />`](./elements/breakout.md)
+- [`<breakoutpoint />`](./elements/breakoutpoint.md)
+- [`<cadassembly />`](./elements/cadassembly.md)
+- [`<cadmodel />`](./elements/cadmodel.md)
+- [`<capacitor />`](./elements/capacitor.md)
+- [`<chip />`](./elements/chip.md)
+- [`<connector />`](./elements/connector.md)
+- [`<constraint />`](./elements/constraint.md)
+- [`<copperpour />`](./elements/copperpour.md)
+- [`<coppertext />`](./elements/coppertext.md)
+- [`<courtyardcircle />`](./elements/courtyardcircle.md)
+- [`<courtyardoutline />`](./elements/courtyardoutline.md)
+- [`<courtyardpill />`](./elements/courtyardpill.md)
+- [`<courtyardrect />`](./elements/courtyardrect.md)
+- [`<crystal />`](./elements/crystal.md)
+- [`<currentsource />`](./elements/currentsource.md)
+- [`<cutout />`](./elements/cutout.md)
+- [`<diode />`](./elements/diode.md)
+- [`<fabricationnotedimension />`](./elements/fabricationnotedimension.md)
+- [`<fabricationnotepath />`](./elements/fabricationnotepath.md)
+- [`<fabricationnoterect />`](./elements/fabricationnoterect.md)
+- [`<fabricationnotetext />`](./elements/fabricationnotetext.md)
+- [`<fiducial />`](./elements/fiducial.md)
+- [`<footprint />`](./elements/footprint.md)
+- [`<fuse />`](./elements/fuse.md)
+- [`<group />`](./elements/group.md)
+- [`<hole />`](./elements/hole.md)
+- [`<inductor />`](./elements/inductor.md)
+- [`<jumper />`](./elements/jumper.md)
+- [`<led />`](./elements/led.md)
+- [`<mosfet />`](./elements/mosfet.md)
+- [`<mountedboard />`](./elements/mountedboard.md)
+- [`<net />`](./elements/net.md)
+- [`<netalias />`](./elements/netalias.md)
+- [`<netlabel />`](./elements/netlabel.md)
+- [`<opamp />`](./elements/opamp.md)
+- [`<panel />`](./elements/panel.md)
+- [`<pcbkeepout />`](./elements/pcbkeepout.md)
+- [`<pcbnotedimension />`](./elements/pcbnotedimension.md)
+- [`<pcbnoteline />`](./elements/pcbnoteline.md)
+- [`<pcbnotepath />`](./elements/pcbnotepath.md)
+- [`<pcbnoterect />`](./elements/pcbnoterect.md)
+- [`<pcbnotetext />`](./elements/pcbnotetext.md)
+- [`<pcbtrace />`](./elements/pcbtrace.md)
+- [`<pinheader />`](./elements/pinheader.md)
+- [`<pinout />`](./elements/pinout.md)
+- [`<platedhole />`](./elements/platedhole.md)
+- [`<port />`](./elements/port.md)
+- [`<potentiometer />`](./elements/potentiometer.md)
+- [`<pushbutton />`](./elements/pushbutton.md)
+- [`<resistor />`](./elements/resistor.md)
+- [`<resonator />`](./elements/resonator.md)
+- [`<schematicarc />`](./elements/schematicarc.md)
+- [`<schematicbox />`](./elements/schematicbox.md)
+- [`<schematiccell />`](./elements/schematiccell.md)
+- [`<schematiccircle />`](./elements/schematiccircle.md)
+- [`<schematicline />`](./elements/schematicline.md)
+- [`<schematicpath />`](./elements/schematicpath.md)
+- [`<schematicrect />`](./elements/schematicrect.md)
+- [`<schematicrow />`](./elements/schematicrow.md)
+- [`<schematicsection />`](./elements/schematicsection.md)
+- [`<schematictable />`](./elements/schematictable.md)
+- [`<schematictext />`](./elements/schematictext.md)
+- [`<silkscreencircle />`](./elements/silkscreencircle.md)
+- [`<silkscreenline />`](./elements/silkscreenline.md)
+- [`<silkscreenpath />`](./elements/silkscreenpath.md)
+- [`<silkscreenrect />`](./elements/silkscreenrect.md)
+- [`<silkscreentext />`](./elements/silkscreentext.md)
+- [`<smtpad />`](./elements/smtpad.md)
+- [`<solderjumper />`](./elements/solderjumper.md)
+- [`<subcircuit />`](./elements/subcircuit.md)
+- [`<subpanel />`](./elements/subpanel.md)
+- [`<switch />`](./elements/switch.md)
+- [`<symbol />`](./elements/symbol.md)
+- [`<testpoint />`](./elements/testpoint.md)
+- [`<trace />`](./elements/trace.md)
+- [`<tracehint />`](./elements/tracehint.md)
+- [`<transistor />`](./elements/transistor.md)
+- [`<via />`](./elements/via.md)
+- [`<voltageprobe />`](./elements/voltageprobe.md)
+- [`<voltagesource />`](./elements/voltagesource.md)

package/dist/skill/SYNTAX.md

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+# tscircuit syntax primer
+
+## 1) Root element
+
+A circuit is typically a default export that returns a `<board />` or a form-factor board component from `@tscircuit/common`.
+
+Example:
+
+```tsx
+import React from "react"
+
+export default () => (
+  <board width="10mm" height="10mm" layers={2}>
+    <resistor name="R1" resistance="1k" footprint="0402" />
+  </board>
+)
+```
+
+
+## 2) Layout properties
+
+You can place nearly any element with:
+- `pcbX`, `pcbY` (PCB position)
+- `pcbRotation`
+- `layer` (e.g., `"bottom"`)
+
+
+For schematics:
+- `schX`, `schY`
+- `schRotation`
+- `schOrientation`
+
+Units
+- Numbers are interpreted as mm.
+- Strings can include units (e.g., `"0.1in"`, `"2.54mm"`).
+
+## 3) Pin labels with `pinLabels`
+
+Use `pinLabels` to map physical pin numbers to meaningful names. This is essential for chips and ICs.
+
+```tsx
+<chip
+  name="U1"
+  footprint="qfp32"
+  pinLabels={{
+    pin1: ["GP0", "SPI0_RX", "I2C0_SDA", "UART0_TX"],
+    pin2: ["GP1", "SPI0_CS", "I2C0_SCL", "UART0_RX"],
+    pin3: "GND",
+    // ...
+  }}
+/>
+```
+
+With multi-alias, any of the names can be used in traces:
+
+```tsx
+<trace from="U1.GP0" to="U2.SDA" />
+<trace from="U1.SPI0_RX" to="U3.MISO" />
+```
+
+## 4) Pin attributes with `pinAttributes`
+
+Use `pinAttributes` to add semantic metadata to pins. This enables DRC checks, schematic arrows, and board-level pinout exposure.
+
+Example using a 555 timer (NE555):
+
+```tsx
+<chip
+  name="U1"
+  footprint="dip8"
+  pinLabels={{
+    pin1: "GND",
+    pin2: "TRIG",
+    pin3: "OUT",
+    pin4: "RESET",
+    pin5: "CTRL",
+    pin6: "THRES",
+    pin7: "DISCH",
+    pin8: "VCC",
+  }}
+  pinAttributes={{
+    VCC: { requiresPower: true },
+    RESET: { mustBeConnected: true },
+  }}
+/>
+```
+
+Available attributes:
+
+| Attribute | Type | Description |
+|-----------|------|-------------|
+| `requiresPower` | boolean | Signal goes INTO the chip (shows input arrow on schematic) |
+| `providesPower` | boolean | Signal comes OUT of the chip (shows output arrow on schematic) |
+| `mustBeConnected` | boolean | DRC error if this pin is left floating |
+| `includeInBoardPinout` | boolean | Expose this pin to the board-level pinout |
+
+## 5) Type-safe chip components
+
+For reusable chip components, define `pinLabels` as a const and use `ChipProps` for type safety:
+
+```tsx
+import type { ChipProps } from "tscircuit"
+
+const pinLabels = {
+  pin1: "VCC",
+  pin2: "GND",
+  pin3: ["SDA", "I2C_DATA"],
+  pin4: ["SCL", "I2C_CLK"],
+} as const
+
+export const MyChip = (props: ChipProps<typeof pinLabels>) => (
+  <chip
+    {...props}
+    pinLabels={pinLabels}
+    footprint="soic4"
+  />
+)
+```
+
+## 6) Use `<connector />` for USB connectors
+
+Use `<connector />` for all USB connector footprints (USB-C, Micro-USB, Mini-USB, and USB-A/B variants). This gives the design checker better semantic information for connector-related DRC.
+
+If a `<chip />` is currently modeling a USB receptacle, plug, or jack, consider refactoring it to `<connector />` so additional USB-specific DRC checks can apply.
+
+For a USB-C connector component, prefer the built-in standard:
+
+```tsx
+<connector name="USBC" standard="usb_c" />
+
+<trace from="USBC.VBUS1" to="net.VBUS" />
+<trace from="USBC.VBUS2" to="net.VBUS" />
+<trace from="USBC.DP1" to="net.USB_DP" />
+<trace from="USBC.DP2" to="net.USB_DP" />
+<trace from="USBC.DM1" to="net.USB_DM" />
+<trace from="USBC.DM2" to="net.USB_DM" />
+```
+
+No JLC import is required for this default USB-C connector usage.
+
+## 7) Connectivity with `<trace />`
+
+Connect pins with port selectors:
+
+```tsx
+<trace from="R1.pin1" to="C1.pin1" />
+```
+
+Connect to named nets. Net names must start with a letter or underscore and can only contain letters, numbers and underscores. 
+
+```tsx
+<trace from="U1.pin1" to="net.GND" />
+<trace from="U1.pin8" to="net.VCC" />
+<trace from="U1.pin8" to="net.V3_3" />
+```
+
+Pin labels (in `pinLabels`) can contain letters, numbers, and underscores. Unlike net names, pin labels **can** start with a number (e.g., `"3V3"` is valid).
+
+Useful trace props (optional)
+- `width` / `thickness`
+- `minLength` / `maxLength`
+
+## 8) Grouping for PCB layout
+
+Use `<group />` like a container to move/layout parts together.
+
+```tsx
+<board width="20mm" height="20mm">
+  <group pcbX={5} pcbY={5}>
+    <resistor name="R1" resistance="1k" footprint="0402" pcbX={2.5} pcbY={2.5} />
+    <resistor name="R2" resistance="1k" footprint="0402" pcbX={2.5} pcbY={0} />
+    <resistor name="R3" resistance="1k" footprint="0402" pcbX={2.5} pcbY={-2.5} />
+  </group>
+</board>
+```
+
+## 9) Schematic pin arrangement
+
+Control how pins appear on the schematic symbol with `schPinArrangement`:
+
+```tsx
+<chip
+  name="U1"
+  footprint="soic16"
+  pinLabels={{
+    pin1: "VCC1",
+    pin2: "IN1",
+    pin3: "IN2",
+    pin4: "IN3",
+    pin5: "IN4",
+    pin6: "GND1",
+    pin7: "GND2",
+    pin8: "VCC2",
+    pin9: "OUT1",
+    pin10: "OUT2",
+    pin11: "OUT3",
+    pin12: "OUT4",
+  }}
+  schPinArrangement={{
+    topSide: { pins: ["VCC1", "VCC2"], direction: "left-to-right" },
+    bottomSide: { pins: ["GND1", "GND2"], direction: "left-to-right" },
+    leftSide: { pins: ["IN1", "IN2", "IN3", "IN4"], direction: "top-to-bottom" },
+    rightSide: { pins: ["OUT1", "OUT2", "OUT3", "OUT4"], direction: "top-to-bottom" },
+  }}
+/>
+```
+
+Available sides: `leftSide`, `rightSide`, `topSide`, `bottomSide`
+- Left/right sides use `direction: "top-to-bottom"` or `"bottom-to-top"`
+- Top/bottom sides use `direction: "left-to-right"` or `"right-to-left"`
+
+## 10) Manufacturing helpers
+
+For turnkey assembly you will often want:
+- `supplierPartNumbers` (pin a specific supplier SKU/part number)
+- `doNotPlace` (exclude from automated placement)
+
+Example:
+
+```tsx
+<capacitor
+  name="C1"
+  capacitance="100nF"
+  footprint="0402"
+  supplierPartNumbers={{ jlcpcb: "C14663" }}
+/>
+
+<resistor name="R1" resistance="10k" footprint="0402" doNotPlace />
+```