tm-grammars 1.6.7 → 1.6.8

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Files changed (4) hide show
  1. package/README.md +1 -1
  2. package/grammars/system-verilog.json +1005 -649
  3. package/index.js +4 -4
  4. package/package.json +1 -1
package/grammars/system-verilog.json CHANGED
@@ -1,705 +1,816 @@
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  {
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  "displayName": "SystemVerilog",
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  "fileTypes": [
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- "sv",
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- "SV",
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  "v",
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- "V",
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- "svh",
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- "SVH",
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  "vh",
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- "VH"
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+ "sv",
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+ "svh"
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  ],
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  "name": "system-verilog",
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  "patterns": [
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  {
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- "begin": "\\s*\\b(function|task)\\b(\\s+automatic)?",
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- "beginCaptures": {
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- "1": {
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- "name": "keyword.control.systemverilog"
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- },
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- "2": {
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- "name": "keyword.control.systemverilog"
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- }
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- },
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- "end": ";",
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- "name": "meta.function.systemverilog",
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- "patterns": [
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- {
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- "captures": {
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- "1": {
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- "name": "storage.type.systemverilog"
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- },
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- "2": {
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- "name": "entity.name.function.systemverilog"
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- }
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- },
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- "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*\\s+)?([a-zA-Z_][a-zA-Z0-9_:]*)\\s*(?=\\(|;)"
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- },
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- {
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- "include": "#port-dir"
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- },
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- {
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- "include": "#base-grammar"
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- }
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- ]
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+ "include": "#comments"
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  },
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  {
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- "captures": {
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- "1": {
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- "name": "keyword.control.systemverilog"
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- },
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- "2": {
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- "name": "keyword.control.systemverilog"
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- },
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- "3": {
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- "name": "entity.name.function.systemverilog"
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- }
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- },
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- "match": "\\s*\\b(task)\\s+(automatic)?\\s*(\\w+)\\s*;",
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- "name": "meta.task.simple.systemverilog"
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+ "include": "#strings"
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  },
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  {
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- "begin": "\\s*\\b(typedef\\s+(struct|enum|union)\\b)\\s*(packed)?\\s*([a-zA-Z_][a-zA-Z0-9_]*)?",
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- "beginCaptures": {
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- "1": {
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- "name": "keyword.control.systemverilog"
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- },
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- "2": {
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- "name": "keyword.control.systemverilog"
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- },
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- "3": {
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- "name": "keyword.control.systemverilog"
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- },
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- "4": {
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- "name": "storage.type.systemverilog"
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- }
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- },
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- "end": "(})\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s*;",
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- "endCaptures": {
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- "1": {
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- "name": "keyword.operator.other.systemverilog"
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- },
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- "2": {
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- "name": "entity.name.function.systemverilog"
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- }
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- },
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- "name": "meta.typedef.struct.systemverilog",
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+ "include": "#typedef-enum-struct-union"
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+ },
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+ {
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+ "include": "#typedef"
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+ },
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+ {
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+ "include": "#functions"
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+ },
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+ {
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+ "include": "#keywords"
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+ },
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+ {
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+ "include": "#tables"
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+ },
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+ {
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+ "include": "#function-task"
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+ },
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+ {
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+ "include": "#module-declaration"
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+ },
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+ {
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+ "include": "#class-declaration"
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+ },
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+ {
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+ "include": "#enum-struct-union"
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+ },
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+ {
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+ "include": "#sequence"
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+ },
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+ {
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+ "include": "#all-types"
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+ },
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+ {
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+ "include": "#module-parameters"
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+ },
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+ {
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+ "include": "#module-no-parameters"
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+ },
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+ {
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+ "include": "#port-net-parameter"
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+ },
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+ {
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+ "include": "#system-tf"
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+ },
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+ {
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+ "include": "#assertion"
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+ },
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+ {
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+ "include": "#bind-directive"
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+ },
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+ {
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+ "include": "#cast-operator"
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+ },
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+ {
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+ "include": "#storage-scope"
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+ },
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+ {
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+ "include": "#attributes"
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+ },
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+ {
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+ "include": "#imports"
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+ },
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+ {
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+ "include": "#operators"
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+ },
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+ {
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+ "include": "#constants"
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+ },
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+ {
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+ "include": "#identifiers"
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+ },
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+ {
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+ "include": "#selects"
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+ }
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+ ],
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+ "repository": {
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+ "all-types": {
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  "patterns": [
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  {
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- "include": "#struct-anonymous"
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+ "include": "#built-ins"
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  },
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  {
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- "include": "#base-grammar"
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+ "include": "#modifiers"
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  }
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  ]
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  },
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- {
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+ "assertion": {
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  "captures": {
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  "1": {
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- "name": "keyword.control.systemverilog"
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+ "name": "entity.name.goto-label.php"
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  },
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  "2": {
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- "name": "entity.name.declaration.systemverilog"
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+ "name": "keyword.operator.systemverilog"
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+ },
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+ "3": {
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+ "name": "keyword.sva.systemverilog"
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  }
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  },
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- "match": "\\s*\\b(typedef\\s+class)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\s*;",
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- "name": "meta.typedef.class.systemverilog"
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+ "match": "\\b([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\r\\n]*(:)[ \\t\\r\\n]*(assert|assume|cover|restrict)\\b"
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  },
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- {
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- "begin": "\\s*\\b(typedef)\\b",
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+ "attributes": {
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+ "begin": "(?<!@[ \\t\\r\\n]?)\\(\\*",
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  "beginCaptures": {
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- "1": {
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- "name": "keyword.control.systemverilog"
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+ "0": {
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+ "name": "punctuation.attribute.rounds.begin"
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  }
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  },
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- "end": "([a-zA-Z_][a-zA-Z0-9_]*)\\s*(?=(\\[[a-zA-Z0-9_:\\$\\-\\+]*\\])?;)",
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+ "end": "\\*\\)",
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  "endCaptures": {
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- "1": {
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- "name": "entity.name.function.systemverilog"
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+ "0": {
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+ "name": "punctuation.attribute.rounds.end"
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  }
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  },
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- "name": "meta.typedef.simple.systemverilog",
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+ "name": "meta.attribute.systemverilog",
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  "patterns": [
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  {
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  "captures": {
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  "1": {
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- "name": "storage.type.userdefined.systemverilog"
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+ "name": "keyword.control.systemverilog"
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  },
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  "2": {
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- "name": "keyword.operator.param.systemverilog"
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+ "name": "keyword.operator.assignment.systemverilog"
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  }
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  },
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- "match": "\\b([a-zA-Z_]\\w*)\\s*(#)\\(",
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- "name": "meta.typedef.class.systemverilog"
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+ "match": "([a-zA-Z_][a-zA-Z0-9_$]*)(?:[ \\t\\r\\n]*(=)[ \\t\\r\\n]*)?"
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  },
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  {
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- "include": "#base-grammar"
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+ "include": "#constants"
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  },
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  {
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- "include": "#module-binding"
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+ "include": "#strings"
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  }
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  ]
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  },
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- {
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- "begin": "\\s*(module)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
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- "beginCaptures": {
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- "1": {
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- "name": "keyword.control.systemverilog"
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- },
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- "2": {
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- "name": "entity.name.type.module.systemverilog"
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- }
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- },
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- "end": ";",
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- "endCaptures": {
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- "1": {
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- "name": "entity.name.function.systemverilog"
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- }
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- },
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- "name": "meta.module.systemverilog",
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+ "base-grammar": {
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  "patterns": [
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  {
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- "include": "#port-dir"
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+ "include": "#all-types"
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  },
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  {
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- "match": "\\s*(parameter)",
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- "name": "keyword.other.systemverilog"
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+ "include": "#comments"
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  },
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  {
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- "include": "#base-grammar"
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+ "include": "#operators"
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+ },
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+ {
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+ "include": "#constants"
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+ },
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+ {
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+ "include": "#strings"
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  },
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  {
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- "include": "#ifmodport"
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+ "captures": {
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+ "1": {
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+ "name": "storage.type.interface.systemverilog"
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+ }
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+ },
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+ "match": "[ \\t\\r\\n]*\\b([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\r\\n]+[a-zA-Z_][a-zA-Z0-9_,= \\t\\n]*"
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  },
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  {
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- "match": "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
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- "name": "support.function.systemverilog"
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+ "include": "#storage-scope"
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  }
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  ]
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  },
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- {
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+ "bind-directive": {
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  "captures": {
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  "1": {
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  "name": "keyword.control.systemverilog"
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  },
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  "2": {
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- "name": "entity.name.function.systemverilog"
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- }
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- },
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- "match": "\\b(sequence)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
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- "name": "meta.sequence.systemverilog"
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- },
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- {
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- "captures": {
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- "1": {
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- "name": "keyword.control.systemverilog"
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+ "name": "entity.name.type.module.systemverilog"
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  }
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  },
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- "match": "\\b(bind)\\s+([a-zA-Z_][a-zA-Z0-9_\\.]*)\\b"
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+ "match": "[ \\t\\r\\n]*\\b(bind)[ \\t\\r\\n]+([a-zA-Z_][a-zA-Z0-9_$\\.]*)\\b",
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+ "name": "meta.definition.systemverilog"
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  },
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- {
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- "captures": {
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- "0": {
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- "name": "meta.section.begin.systemverilog"
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+ "built-ins": {
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+ "patterns": [
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+ {
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+ "match": "[ \\t\\r\\n]*\\b(bit|logic|reg)\\b",
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+ "name": "storage.type.vector.systemverilog"
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  },
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- "1": {
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- "name": "keyword.other.block.systemverilog"
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+ {
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+ "match": "[ \\t\\r\\n]*\\b(byte|shortint|int|longint|integer|time|genvar)\\b",
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+ "name": "storage.type.atom.systemverilog"
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  },
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- "3": {
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- "name": "keyword.operator.systemverilog"
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+ {
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+ "match": "[ \\t\\r\\n]*\\b(shortreal|real|realtime)\\b",
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+ "name": "storage.type.notint.systemverilog"
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  },
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- "4": {
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- "name": "entity.name.section.systemverilog"
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- }
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- },
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- "match": "\\s*(begin|fork)\\s*((:)\\s*([a-zA-Z_][a-zA-Z0-9_]*))\\b",
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- "name": "meta.definition.systemverilog"
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- },
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- {
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- "captures": {
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- "1": {
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- "name": "keyword.sva.systemverilog"
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+ {
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+ "match": "[ \\t\\r\\n]*\\b(supply[01]|tri|triand|trior|trireg|tri[01]|uwire|wire|wand|wor)\\b",
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+ "name": "storage.type.net.systemverilog"
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  },
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- "2": {
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- "name": "entity.name.sva.systemverilog"
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+ {
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+ "match": "[ \\t\\r\\n]*\\b(genvar|var|void|signed|unsigned|string|const|process)\\b",
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+ "name": "storage.type.built-in.systemverilog"
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+ },
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+ {
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+ "match": "[ \\t\\r\\n]*\\b(uvm_(?:root|transaction|component|monitor|driver|test|env|object|agent|sequence_base|sequence_item|sequence_state|sequencer|sequencer_base|sequence|component_registry|analysis_imp|analysis_port|analysis_export|config_db|active_passive_enum|phase|verbosity|tlm_analysis_fifo|tlm_fifo|report_server|objection|recorder|domain|reg_field|reg_block|reg|bitstream_t|radix_enum|printer|packer|comparer|scope_stack))\\b",
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+ "name": "storage.type.uvm.systemverilog"
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  }
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- },
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- "match": "\\b(asset|cover)\\s(property)\\s+(\\w+)"
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+ ]
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  },
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- {
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+ "cast-operator": {
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  "captures": {
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  "1": {
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- "name": "entity.name.sva.systemverilog"
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+ "patterns": [
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+ {
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+ "include": "#built-ins"
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+ },
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+ {
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+ "include": "#constants"
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+ },
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+ {
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+ "match": "[a-zA-Z_][a-zA-Z0-9_$]*",
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+ "name": "storage.type.user-defined.systemverilog"
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+ }
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+ ]
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  },
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  "2": {
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- "name": "keyword.operator.systemverilog"
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- },
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- "3": {
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- "name": "keyword.sva.systemverilog"
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+ "name": "keyword.operator.cast.systemverilog"
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  }
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  },
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- "match": "\\b(\\w+)\\s*(:)\\s*(assert)\\b"
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+ "match": "[ \\t\\r\\n]*([0-9]+|[a-zA-Z_][a-zA-Z0-9_$]*)(')(?=\\()",
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+ "name": "meta.cast.systemverilog"
243
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  },
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- {
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- "begin": "\\s*(//)\\s*(psl)\\s+((\\w+)\\s*(:))?\\s*(default|assert|assume)",
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+ "class-declaration": {
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+ "begin": "[ \\t\\r\\n]*\\b(virtual[ \\t\\r\\n]+)?(class)(?:[ \\t\\r\\n]+(static|automatic))?[ \\t\\r\\n]+([a-zA-Z_][a-zA-Z0-9_$:]*)(?:[ \\t\\r\\n]+(extends|implements)[ \\t\\r\\n]+([a-zA-Z_][a-zA-Z0-9_$:]*))?",
246
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  "beginCaptures": {
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- "0": {
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- "name": "meta.psl.systemverilog"
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- },
250
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  "1": {
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- "name": "comment.line.double-slash.systemverilog"
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+ "name": "storage.modifier.systemverilog"
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  },
253
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  "2": {
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- "name": "keyword.psl.systemverilog"
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+ "name": "storage.type.class.systemverilog"
253
+ },
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+ "3": {
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+ "name": "storage.modifier.systemverilog"
255
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  },
256
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  "4": {
257
- "name": "entity.psl.name.systemverilog"
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+ "name": "entity.name.type.class.systemverilog"
258
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  },
259
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  "5": {
260
- "name": "keyword.operator.systemverilog"
261
+ "name": "keyword.control.systemverilog"
261
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  },
262
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  "6": {
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- "name": "keyword.psl.systemverilog"
264
+ "name": "entity.name.type.class.systemverilog"
264
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  }
265
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  },
266
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  "end": ";",
267
- "name": "meta.psl.systemverilog",
268
+ "endCaptures": {
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271
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268
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269
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- "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge)\\b",
271
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- },
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- {
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- "include": "#operators"
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- },
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- "include": "#functions"
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278
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  },
279
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280
- "include": "#constants"
290
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+ },
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+ "name": "meta.typedef.class.systemverilog"
300
+ },
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+ {
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+ "include": "#port-net-parameter"
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+ },
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+ {
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+ "include": "#base-grammar"
306
+ },
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+ {
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+ "include": "#module-binding"
309
+ },
310
+ {
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+ "include": "#identifiers"
281
312
  }
282
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  ]
283
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  },
284
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285
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286
- "beginCaptures": {
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- "name": "meta.psl.systemverilog"
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319
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+ },
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331
+ "patterns": [
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+ {
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+ "include": "#fixme-todo"
334
+ }
335
+ ]
292
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  },
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- "2": {
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- }
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- },
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- "end": "(\\*/)",
298
- "endCaptures": {
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- "1": {
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- "name": "comment.block.systemverilog"
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342
+ }
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+ "end": "$\\n?",
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346
+ "patterns": [
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+ {
348
+ "include": "#fixme-todo"
349
+ }
350
+ ]
301
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  }
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- },
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- "name": "meta.psl.systemverilog",
352
+ ]
353
+ },
354
+ "compiler-directives": {
355
+ "name": "meta.preprocessor.systemverilog",
304
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  "patterns": [
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  {
306
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  "captures": {
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- "0": {
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- "name": "meta.psl.systemverilog"
359
+ "1": {
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+ "name": "punctuation.definition.directive.systemverilog"
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+ },
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+ "2": {
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+ "name": "string.regexp.systemverilog"
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+ }
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982
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932
983
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985
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941
995
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942
996
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943
997
  "name": "support.type.scope.systemverilog"
@@ -946,72 +1000,127 @@
946
1000
  "name": "keyword.operator.scope.systemverilog"
947
1001
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1002
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949
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1003
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1009
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1010
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1012
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1013
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1026
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1027
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1079
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1080
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970
1083
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971
1084
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974
1087
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975
1088
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976
1089
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1094
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986
1095
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1096
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1097
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1098
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1100
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1101
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1126
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1020
1129
  "name": "string.quoted.double.systemverilog",
1021
1130
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1131
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1132
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1133
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1025
1134
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1135
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1138
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1139
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1141
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+ },
1393
+ "2": {
1394
+ "patterns": [
1395
+ {
1396
+ "include": "#selects"
1397
+ }
1398
+ ]
1052
1399
  }
1053
1400
  },
1054
- "name": "meta.struct.anonymous.systemverilog",
1401
+ "name": "meta.typedef-enum-struct-union.systemverilog",
1055
1402
  "patterns": [
1403
+ {
1404
+ "include": "#port-net-parameter"
1405
+ },
1406
+ {
1407
+ "include": "#keywords"
1408
+ },
1056
1409
  {
1057
1410
  "include": "#base-grammar"
1411
+ },
1412
+ {
1413
+ "include": "#identifiers"
1058
1414
  }
1059
1415
  ]
1060
1416
  }