tjs-lang 0.9.0 → 0.9.1

package/src/lang/wasm.ts

@@ -262,6 +262,19 @@ const SimdOp = {
   f32x4_sub: 0xe5,
   f32x4_mul: 0xe6,
   f32x4_div: 0xe7,
+  f32x4_min: 0xe8,
+  f32x4_max: 0xe9,
+
+  // f32x4 comparisons → v128 lane mask (all-1s / all-0s per lane)
+  f32x4_eq: 0x41,
+  f32x4_ne: 0x42,
+  f32x4_lt: 0x43,
+  f32x4_gt: 0x44,
+  f32x4_le: 0x45,
+  f32x4_ge: 0x46,
+
+  // Lane-wise blend: bitselect(a, b, mask) — bits of a where mask=1, else b.
+  v128_bitselect: 0x52,
 } as const
 
 /** Reverse lookup for SIMD opcodes */
@@ -1160,6 +1173,18 @@ function compileBinaryExpr(
     return [Op.f64_const, ...encodeF64(0)]
   }
 
+  // Lint the i32/i32 division footgun: `/` with two integer operands (loop vars,
+  // `0`-annotated params, int literals) does TRUNCATING integer division, and the
+  // coercion to f64 only happens at the *next* operator — so `x / w - 0.5` is
+  // silently `0 - 0.5` for all `x < w`. Warn once per block; add `+ 0.0` to an
+  // operand to force f64 division. (UI-#4 — this is a warning, not an error:
+  // integer division may be intended.)
+  if (node.operator === '/' && opType === 'i32') {
+    const msg =
+      "integer division: '/' with two i32 operands truncates (result coerces to f64 only at the next operator). Add `+ 0.0` to an operand to force f64 division."
+    if (!ctx.warnings.includes(msg)) ctx.warnings.push(msg)
+  }
+
   return [...leftCode, ...rightCode, opcode]
 }
 
@@ -1808,8 +1833,17 @@ function compileSIMDCall(
     case 'f32x4_add':
     case 'f32x4_sub':
     case 'f32x4_mul':
-    case 'f32x4_div': {
-      // Binary v128 op: f32x4_add(a, b) → v128
+    case 'f32x4_div':
+    case 'f32x4_min':
+    case 'f32x4_max':
+    case 'f32x4_eq':
+    case 'f32x4_ne':
+    case 'f32x4_lt':
+    case 'f32x4_gt':
+    case 'f32x4_le':
+    case 'f32x4_ge': {
+      // Binary v128 op: f(a, b) → v128. The comparisons (eq/ne/lt/gt/le/ge)
+      // return a v128 lane mask (all-1s where true, all-0s else).
       code.push(...compileExpression(args[0], ctx))
       code.push(...compileExpression(args[1], ctx))
       const opMap: Record<string, number> = {
@@ -1817,11 +1851,36 @@ function compileSIMDCall(
         f32x4_sub: SimdOp.f32x4_sub,
         f32x4_mul: SimdOp.f32x4_mul,
         f32x4_div: SimdOp.f32x4_div,
+        f32x4_min: SimdOp.f32x4_min,
+        f32x4_max: SimdOp.f32x4_max,
+        f32x4_eq: SimdOp.f32x4_eq,
+        f32x4_ne: SimdOp.f32x4_ne,
+        f32x4_lt: SimdOp.f32x4_lt,
+        f32x4_gt: SimdOp.f32x4_gt,
+        f32x4_le: SimdOp.f32x4_le,
+        f32x4_ge: SimdOp.f32x4_ge,
       }
       code.push(...encodeSIMD(opMap[name]))
       return code
     }
 
+    case 'f32x4_select': {
+      // Branch-free lane blend: f32x4_select(mask, a, b) → a where the mask lane
+      // is true (all-1s, e.g. from a compare), b where false. Maps to
+      // v128.bitselect(a, b, mask) — bits of a where mask=1, of b where mask=0.
+      if (args.length !== 3) {
+        ctx.errors.push(
+          `f32x4_select expects (mask, a, b) — 3 args, got ${args.length}`
+        )
+        return [Op.f64_const, ...encodeF64(0)]
+      }
+      code.push(...compileExpression(args[1], ctx)) // a (bitselect v1)
+      code.push(...compileExpression(args[2], ctx)) // b (bitselect v2)
+      code.push(...compileExpression(args[0], ctx)) // mask
+      code.push(...encodeSIMD(SimdOp.v128_bitselect))
+      return code
+    }
+
     case 'f32x4_neg':
     case 'f32x4_sqrt': {
       // Unary v128 op: f32x4_neg(a) → v128