tasmota-webserial-esptool 9.2.8 → 9.2.10

package/dist/const.d.ts

@@ -67,14 +67,18 @@ export declare const ESP32S2_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32S2_SPI_W0_OFFS = 88;
 export declare const ESP32S2_UART_DATE_REG_ADDR = 1610612856;
 export declare const ESP32S2_BOOTLOADER_FLASH_OFFSET = 4096;
-export declare const ESP32S2_RTC_CNTL_WDTWPROTECT_REG = 1061191852;
-export declare const ESP32S2_RTC_CNTL_WDTCONFIG0_REG = 1061191828;
-export declare const ESP32S2_RTC_CNTL_WDTCONFIG1_REG = 1061191832;
+export declare const ESP32S2_RTCCNTL_BASE_REG = 1061191680;
+export declare const ESP32S2_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32S2_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32S2_RTC_CNTL_WDTCONFIG1_REG: number;
 export declare const ESP32S2_RTC_CNTL_WDT_WKEY = 1356348065;
 export declare const ESP32S2_GPIO_STRAP_REG = 1061175352;
 export declare const ESP32S2_GPIO_STRAP_SPI_BOOT_MASK: number;
+export declare const ESP32S2_GPIO_STRAP_VDDSPI_MASK: number;
 export declare const ESP32S2_RTC_CNTL_OPTION1_REG = 1061191976;
 export declare const ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 1;
+export declare const ESP32S2_UARTDEV_BUF_NO = 1073741076;
+export declare const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2;
 export declare const ESP32S3_SPI_REG_BASE = 1610620928;
 export declare const ESP32S3_BASEFUSEADDR = 1610641408;
 export declare const ESP32S3_MACFUSEADDR: number;
@@ -86,14 +90,19 @@ export declare const ESP32S3_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32S3_SPI_W0_OFFS = 88;
 export declare const ESP32S3_UART_DATE_REG_ADDR = 1610612864;
 export declare const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0;
-export declare const ESP32S3_RTC_CNTL_WDTWPROTECT_REG = 1610645680;
-export declare const ESP32S3_RTC_CNTL_WDTCONFIG0_REG = 1610645656;
-export declare const ESP32S3_RTC_CNTL_WDTCONFIG1_REG = 1610645660;
+export declare const ESP32S3_RTCCNTL_BASE_REG = 1610645504;
+export declare const ESP32S3_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32S3_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32S3_RTC_CNTL_WDTCONFIG1_REG: number;
 export declare const ESP32S3_RTC_CNTL_WDT_WKEY = 1356348065;
 export declare const ESP32S3_GPIO_STRAP_REG = 1610629176;
 export declare const ESP32S3_GPIO_STRAP_SPI_BOOT_MASK: number;
+export declare const ESP32S3_GPIO_STRAP_VDDSPI_MASK: number;
 export declare const ESP32S3_RTC_CNTL_OPTION1_REG = 1610645804;
 export declare const ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 1;
+export declare const ESP32S3_UARTDEV_BUF_NO = 1070526796;
+export declare const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3;
+export declare const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4;
 export declare const ESP32C2_SPI_REG_BASE = 1610620928;
 export declare const ESP32C2_BASEFUSEADDR = 1610647552;
 export declare const ESP32C2_MACFUSEADDR: number;
@@ -105,8 +114,14 @@ export declare const ESP32C2_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32C2_SPI_W0_OFFS = 88;
 export declare const ESP32C2_UART_DATE_REG_ADDR = 1610612860;
 export declare const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0;
+export declare const ESP32C2_RTCCNTL_BASE_REG = 1610645504;
+export declare const ESP32C2_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32C2_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32C2_RTC_CNTL_WDTCONFIG1_REG: number;
+export declare const ESP32C2_RTC_CNTL_WDT_WKEY = 1356348065;
 export declare const ESP32C3_SPI_REG_BASE = 1610620928;
 export declare const ESP32C3_BASEFUSEADDR = 1610647552;
+export declare const ESP32C3_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32C3_MACFUSEADDR: number;
 export declare const ESP32C3_SPI_USR_OFFS = 24;
 export declare const ESP32C3_SPI_USR1_OFFS = 28;
@@ -116,6 +131,19 @@ export declare const ESP32C3_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32C3_SPI_W0_OFFS = 88;
 export declare const ESP32C3_UART_DATE_REG_ADDR = 1610612860;
 export declare const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0;
+export declare const ESP32C3_RTC_CNTL_BASE_REG = 1610645504;
+export declare const ESP32C3_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32C3_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32C3_RTC_CNTL_WDTCONFIG1_REG: number;
+export declare const ESP32C3_RTC_CNTL_WDT_WKEY = 1356348065;
+export declare const ESP32C3_RTC_CNTL_SWD_WKEY = 2401055018;
+export declare const ESP32C3_RTC_CNTL_SWD_CONF_REG: number;
+export declare const ESP32C3_RTC_CNTL_SWD_AUTO_FEED_EN: number;
+export declare const ESP32C3_RTC_CNTL_SWD_WPROTECT_REG: number;
+export declare const ESP32C3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
+export declare const ESP32C3_BUF_UART_NO_OFFSET = 24;
+export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 1610647632;
+export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 1610647640;
 export declare const ESP32C5_SPI_REG_BASE = 1610625024;
 export declare const ESP32C5_BASEFUSEADDR = 1611352064;
 export declare const ESP32C5_MACFUSEADDR: number;
@@ -127,6 +155,8 @@ export declare const ESP32C5_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32C5_SPI_W0_OFFS = 88;
 export declare const ESP32C5_UART_DATE_REG_ADDR = 1610612860;
 export declare const ESP32C5_BOOTLOADER_FLASH_OFFSET = 8192;
+export declare const ESP32C5_UARTDEV_BUF_NO = 1082520852;
+export declare const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
 export declare const ESP32C6_SPI_REG_BASE = 1610625024;
 export declare const ESP32C6_BASEFUSEADDR = 1611335680;
 export declare const ESP32C6_MACFUSEADDR: number;
@@ -138,6 +168,22 @@ export declare const ESP32C6_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32C6_SPI_W0_OFFS = 88;
 export declare const ESP32C6_UART_DATE_REG_ADDR = 1610612860;
 export declare const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0;
+export declare const ESP32C6_DR_REG_LP_WDT_BASE = 1611340800;
+export declare const ESP32C6_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32C6_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32C6_RTC_CNTL_WDTCONFIG1_REG: number;
+export declare const ESP32C6_RTC_CNTL_WDT_WKEY = 1356348065;
+export declare const ESP32C6_RTC_CNTL_SWD_WKEY = 1356348065;
+export declare const ESP32C6_UARTDEV_BUF_NO = 1082652032;
+export declare const ESP32C6_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
+export declare const ESP32C5_C6_DR_REG_LP_WDT_BASE = 1611340800;
+export declare const ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG: number;
+export declare const ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32C5_C6_RTC_CNTL_WDT_WKEY = 1356348065;
+export declare const ESP32C5_C6_RTC_CNTL_SWD_CONF_REG: number;
+export declare const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN: number;
+export declare const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG: number;
 export declare const ESP32C61_SPI_REG_BASE = 1610625024;
 export declare const ESP32C61_BASEFUSEADDR = 1611352064;
 export declare const ESP32C61_MACFUSEADDR: number;
@@ -160,6 +206,14 @@ export declare const ESP32H2_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32H2_SPI_W0_OFFS = 88;
 export declare const ESP32H2_UART_DATE_REG_ADDR = 1610612860;
 export declare const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0;
+export declare const ESP32H2_DR_REG_LP_WDT_BASE = 1611340800;
+export declare const ESP32H2_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32H2_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32H2_RTC_CNTL_WDTCONFIG1_REG: number;
+export declare const ESP32H2_RTC_CNTL_WDT_WKEY = 1356348065;
+export declare const ESP32H2_RTC_CNTL_SWD_WKEY = 1356348065;
+export declare const ESP32H2_UARTDEV_BUF_NO = 1082457852;
+export declare const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
 export declare const ESP32H4_SPI_REG_BASE = 1611239424;
 export declare const ESP32H4_BASEFUSEADDR = 1611339776;
 export declare const ESP32H4_MACFUSEADDR: number;
@@ -171,6 +225,12 @@ export declare const ESP32H4_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32H4_SPI_W0_OFFS = 88;
 export declare const ESP32H4_UART_DATE_REG_ADDR: number;
 export declare const ESP32H4_BOOTLOADER_FLASH_OFFSET = 8192;
+export declare const ESP32H4_DR_REG_LP_WDT_BASE = 1611355136;
+export declare const ESP32H4_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32H4_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32H4_RTC_CNTL_WDTCONFIG1_REG: number;
+export declare const ESP32H4_RTC_CNTL_WDT_WKEY = 1356348065;
+export declare const ESP32H4_RTC_CNTL_SWD_WKEY = 1356348065;
 export declare const ESP32H21_SPI_REG_BASE = 1610625024;
 export declare const ESP32H21_BASEFUSEADDR = 1611350016;
 export declare const ESP32H21_MACFUSEADDR: number;
@@ -182,6 +242,12 @@ export declare const ESP32H21_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32H21_SPI_W0_OFFS = 88;
 export declare const ESP32H21_UART_DATE_REG_ADDR = 1610612860;
 export declare const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0;
+export declare const ESP32H21_DR_REG_LP_WDT_BASE = 1611340800;
+export declare const ESP32H21_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32H21_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32H21_RTC_CNTL_WDTCONFIG1_REG: number;
+export declare const ESP32H21_RTC_CNTL_WDT_WKEY = 1356348065;
+export declare const ESP32H21_RTC_CNTL_SWD_WKEY = 1356348065;
 export declare const ESP32P4_SPI_REG_BASE = 1342754816;
 export declare const ESP32P4_BASEFUSEADDR = 1343410176;
 export declare const ESP32P4_EFUSE_BLOCK1_ADDR: number;
@@ -194,6 +260,23 @@ export declare const ESP32P4_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32P4_SPI_W0_OFFS = 88;
 export declare const ESP32P4_UART_DATE_REG_ADDR: number;
 export declare const ESP32P4_BOOTLOADER_FLASH_OFFSET = 8192;
+export declare const ESP32P4_DR_REG_LP_WDT_BASE = 1343315968;
+export declare const ESP32P4_RTC_CNTL_WDTWPROTECT_REG: number;
+export declare const ESP32P4_RTC_CNTL_WDTCONFIG0_REG: number;
+export declare const ESP32P4_RTC_CNTL_WDTCONFIG1_REG: number;
+export declare const ESP32P4_RTC_CNTL_WDT_WKEY = 1356348065;
+export declare const ESP32P4_RTC_CNTL_SWD_CONF_REG: number;
+export declare const ESP32P4_RTC_CNTL_SWD_AUTO_FEED_EN: number;
+export declare const ESP32P4_RTC_CNTL_SWD_WPROTECT_REG: number;
+export declare const ESP32P4_RTC_CNTL_SWD_WKEY = 1356348065;
+export declare const ESP32P4_UARTDEV_BUF_NO_REV0 = 1341390536;
+export declare const ESP32P4_UARTDEV_BUF_NO_REV300 = 1341914824;
+export declare const ESP32P4_UARTDEV_BUF_NO_USB_OTG = 5;
+export declare const ESP32P4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6;
+export declare const ESP32P4_GPIO_STRAP_REG = 1343094840;
+export declare const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 8;
+export declare const ESP32P4_RTC_CNTL_OPTION1_REG = 1343291400;
+export declare const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 4;
 export declare const ESP32S31_SPI_REG_BASE = 542113792;
 export declare const ESP32S31_BASEFUSEADDR = 544296960;
 export declare const ESP32S31_EFUSE_BLOCK1_ADDR: number;

package/dist/const.js

@@ -63,7 +63,7 @@ export const ESP8266_SPI_MOSI_DLEN_OFFS = -1;
 export const ESP8266_SPI_MISO_DLEN_OFFS = -1;
 export const ESP8266_SPI_W0_OFFS = 0x40;
 export const ESP8266_UART_DATE_REG_ADDR = 0x60000078;
-export const ESP8266_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP8266_BOOTLOADER_FLASH_OFFSET = 0x0000;
 export const ESP32_SPI_REG_BASE = 0x3ff42000;
 export const ESP32_BASEFUSEADDR = 0x3ff5a000;
 export const ESP32_MACFUSEADDR = 0x3ff5a000;
@@ -87,15 +87,19 @@ export const ESP32S2_SPI_W0_OFFS = 0x58;
 export const ESP32S2_UART_DATE_REG_ADDR = 0x60000078;
 export const ESP32S2_BOOTLOADER_FLASH_OFFSET = 0x1000;
 // ESP32-S2 RTC Watchdog Timer registers for USB-OTG reset
-export const ESP32S2_RTC_CNTL_WDTWPROTECT_REG = 0x3f4080ac;
-export const ESP32S2_RTC_CNTL_WDTCONFIG0_REG = 0x3f408094;
-export const ESP32S2_RTC_CNTL_WDTCONFIG1_REG = 0x3f408098;
+export const ESP32S2_RTCCNTL_BASE_REG = 0x3f408000;
+export const ESP32S2_RTC_CNTL_WDTWPROTECT_REG = ESP32S2_RTCCNTL_BASE_REG + 0x00ac;
+export const ESP32S2_RTC_CNTL_WDTCONFIG0_REG = ESP32S2_RTCCNTL_BASE_REG + 0x0094;
+export const ESP32S2_RTC_CNTL_WDTCONFIG1_REG = ESP32S2_RTCCNTL_BASE_REG + 0x0098;
 export const ESP32S2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
 // ESP32-S2 GPIO strap register and boot mode control
 export const ESP32S2_GPIO_STRAP_REG = 0x3f404038;
 export const ESP32S2_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
+export const ESP32S2_GPIO_STRAP_VDDSPI_MASK = 1 << 4; // SPI voltage (1.8V vs 3.3V)
 export const ESP32S2_RTC_CNTL_OPTION1_REG = 0x3f408128;
 export const ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
+export const ESP32S2_UARTDEV_BUF_NO = 0x3ffffd14; // Variable in ROM .bss which indicates the port in use
+export const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2; // Value of the above indicating that USB-OTG is in use
 export const ESP32S3_SPI_REG_BASE = 0x60002000;
 export const ESP32S3_BASEFUSEADDR = 0x60007000;
 export const ESP32S3_MACFUSEADDR = 0x60007000 + 0x044;
@@ -106,20 +110,25 @@ export const ESP32S3_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32S3_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32S3_SPI_W0_OFFS = 0x58;
 export const ESP32S3_UART_DATE_REG_ADDR = 0x60000080;
-export const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0x0000;
 // ESP32-S3 RTC Watchdog Timer registers for USB-OTG reset
-export const ESP32S3_RTC_CNTL_WDTWPROTECT_REG = 0x600080b0;
-export const ESP32S3_RTC_CNTL_WDTCONFIG0_REG = 0x60008098;
-export const ESP32S3_RTC_CNTL_WDTCONFIG1_REG = 0x6000809c;
+export const ESP32S3_RTCCNTL_BASE_REG = 0x60008000;
+export const ESP32S3_RTC_CNTL_WDTWPROTECT_REG = ESP32S3_RTCCNTL_BASE_REG + 0x00b0;
+export const ESP32S3_RTC_CNTL_WDTCONFIG0_REG = ESP32S3_RTCCNTL_BASE_REG + 0x0098;
+export const ESP32S3_RTC_CNTL_WDTCONFIG1_REG = ESP32S3_RTCCNTL_BASE_REG + 0x009c;
 export const ESP32S3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
 // ESP32-S3 GPIO strap register and boot mode control
 export const ESP32S3_GPIO_STRAP_REG = 0x60004038;
 export const ESP32S3_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
+export const ESP32S3_GPIO_STRAP_VDDSPI_MASK = 1 << 4;
 export const ESP32S3_RTC_CNTL_OPTION1_REG = 0x6000812c;
 export const ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
+export const ESP32S3_UARTDEV_BUF_NO = 0x3fcef14c; // Variable in ROM .bss which indicates the port in use
+export const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3; // The above var when USB-OTG is used
+export const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4; // The above var when USB-JTAG/Serial is used
 export const ESP32C2_SPI_REG_BASE = 0x60002000;
 export const ESP32C2_BASEFUSEADDR = 0x60008800;
-export const ESP32C2_MACFUSEADDR = 0x60008800 + 0x044;
+export const ESP32C2_MACFUSEADDR = ESP32C2_BASEFUSEADDR + 0x040;
 export const ESP32C2_SPI_USR_OFFS = 0x18;
 export const ESP32C2_SPI_USR1_OFFS = 0x1c;
 export const ESP32C2_SPI_USR2_OFFS = 0x20;
@@ -127,9 +136,16 @@ export const ESP32C2_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C2_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C2_SPI_W0_OFFS = 0x58;
 export const ESP32C2_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-C2 RTC Watchdog Timer registers
+export const ESP32C2_RTCCNTL_BASE_REG = 0x60008000;
+export const ESP32C2_RTC_CNTL_WDTWPROTECT_REG = ESP32C2_RTCCNTL_BASE_REG + 0x009c;
+export const ESP32C2_RTC_CNTL_WDTCONFIG0_REG = ESP32C2_RTCCNTL_BASE_REG + 0x0084;
+export const ESP32C2_RTC_CNTL_WDTCONFIG1_REG = ESP32C2_RTCCNTL_BASE_REG + 0x0088;
+export const ESP32C2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
 export const ESP32C3_SPI_REG_BASE = 0x60002000;
 export const ESP32C3_BASEFUSEADDR = 0x60008800;
+export const ESP32C3_EFUSE_BLOCK1_ADDR = ESP32C3_BASEFUSEADDR + 0x044;
 export const ESP32C3_MACFUSEADDR = 0x60008800 + 0x044;
 export const ESP32C3_SPI_USR_OFFS = 0x18;
 export const ESP32C3_SPI_USR1_OFFS = 0x1c;
@@ -138,7 +154,24 @@ export const ESP32C3_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C3_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C3_SPI_W0_OFFS = 0x58;
 export const ESP32C3_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-C3 RTC Watchdog Timer registers
+export const ESP32C3_RTC_CNTL_BASE_REG = 0x60008000;
+export const ESP32C3_RTC_CNTL_WDTWPROTECT_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00a8;
+export const ESP32C3_RTC_CNTL_WDTCONFIG0_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x0090;
+export const ESP32C3_RTC_CNTL_WDTCONFIG1_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x0094;
+export const ESP32C3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
+export const ESP32C3_RTC_CNTL_SWD_WKEY = 0x8f1d312a;
+export const ESP32C3_RTC_CNTL_SWD_CONF_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00ac;
+export const ESP32C3_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 31;
+export const ESP32C3_RTC_CNTL_SWD_WPROTECT_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00b0;
+export const ESP32C3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
+export const ESP32C3_BUF_UART_NO_OFFSET = 24;
+// Note: ESP32C3_BSS_UART_DEV_ADDR is calculated dynamically based on chip revision in esp_loader.ts
+// Revision < 101: 0x3FCDF064, Revision >= 101: 0x3FCDF060
+// ESP32-C3 EFUSE registers for chip revision detection
+export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 0x60008850;
+export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 0x60008858;
 export const ESP32C5_SPI_REG_BASE = 0x60003000;
 export const ESP32C5_BASEFUSEADDR = 0x600b4800;
 export const ESP32C5_MACFUSEADDR = 0x600b4800 + 0x044;
@@ -150,6 +183,9 @@ export const ESP32C5_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C5_SPI_W0_OFFS = 0x58;
 export const ESP32C5_UART_DATE_REG_ADDR = 0x6000007c;
 export const ESP32C5_BOOTLOADER_FLASH_OFFSET = 0x2000;
+// ESP32-C5 USB-JTAG/Serial detection
+export const ESP32C5_UARTDEV_BUF_NO = 0x4085f514; // Variable in ROM .bss which indicates the port in use
+export const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 export const ESP32C6_SPI_REG_BASE = 0x60003000;
 export const ESP32C6_BASEFUSEADDR = 0x600b0800;
 export const ESP32C6_MACFUSEADDR = 0x600b0800 + 0x044;
@@ -160,7 +196,26 @@ export const ESP32C6_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C6_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C6_SPI_W0_OFFS = 0x58;
 export const ESP32C6_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-C6 RTC Watchdog Timer registers (LP_WDT)
+export const ESP32C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
+export const ESP32C6_RTC_CNTL_WDTWPROTECT_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
+export const ESP32C6_RTC_CNTL_WDTCONFIG0_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
+export const ESP32C6_RTC_CNTL_WDTCONFIG1_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+export const ESP32C6_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+// ESP32-C6 USB-JTAG/Serial detection
+export const ESP32C6_UARTDEV_BUF_NO = 0x4087f580; // Variable in ROM .bss which indicates the port in use
+export const ESP32C6_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
+// ESP32-C5/C6 LP Watchdog Timer registers (Low Power WDT)
+export const ESP32C5_C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
+export const ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
+export const ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
+export const ESP32C5_C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY
+export const ESP32C5_C6_RTC_CNTL_SWD_CONF_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_SWD_CONFIG_REG
+export const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
+export const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0020; // LP_WDT_SWD_WPROTECT_REG
 export const ESP32C61_SPI_REG_BASE = 0x60003000;
 export const ESP32C61_BASEFUSEADDR = 0x600b4800;
 export const ESP32C61_MACFUSEADDR = 0x600b4800 + 0x044;
@@ -171,7 +226,7 @@ export const ESP32C61_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C61_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C61_SPI_W0_OFFS = 0x58;
 export const ESP32C61_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0000;
 export const ESP32H2_SPI_REG_BASE = 0x60003000;
 export const ESP32H2_BASEFUSEADDR = 0x600b0800;
 export const ESP32H2_MACFUSEADDR = 0x600b0800 + 0x044;
@@ -182,7 +237,17 @@ export const ESP32H2_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32H2_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32H2_SPI_W0_OFFS = 0x58;
 export const ESP32H2_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-H2 RTC Watchdog Timer registers (LP_WDT)
+export const ESP32H2_DR_REG_LP_WDT_BASE = 0x600b1c00;
+export const ESP32H2_RTC_CNTL_WDTWPROTECT_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_RWDT_WPROTECT_REG
+export const ESP32H2_RTC_CNTL_WDTCONFIG0_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
+export const ESP32H2_RTC_CNTL_WDTCONFIG1_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32H2_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+export const ESP32H2_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+// ESP32-H2 USB-JTAG/Serial detection
+export const ESP32H2_UARTDEV_BUF_NO = 0x4084fefc; // Variable in ROM .bss which indicates the port in use
+export const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 export const ESP32H4_SPI_REG_BASE = 0x60099000;
 export const ESP32H4_BASEFUSEADDR = 0x600b1800;
 export const ESP32H4_MACFUSEADDR = 0x600b1800 + 0x044;
@@ -194,6 +259,13 @@ export const ESP32H4_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32H4_SPI_W0_OFFS = 0x58;
 export const ESP32H4_UART_DATE_REG_ADDR = 0x60012000 + 0x7c;
 export const ESP32H4_BOOTLOADER_FLASH_OFFSET = 0x2000;
+// ESP32-H4 RTC Watchdog Timer registers
+export const ESP32H4_DR_REG_LP_WDT_BASE = 0x600b5400;
+export const ESP32H4_RTC_CNTL_WDTWPROTECT_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
+export const ESP32H4_RTC_CNTL_WDTCONFIG0_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
+export const ESP32H4_RTC_CNTL_WDTCONFIG1_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32H4_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+export const ESP32H4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
 export const ESP32H21_SPI_REG_BASE = 0x60003000;
 export const ESP32H21_BASEFUSEADDR = 0x600b4000;
 export const ESP32H21_MACFUSEADDR = 0x600b4000 + 0x044;
@@ -204,7 +276,14 @@ export const ESP32H21_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32H21_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32H21_SPI_W0_OFFS = 0x58;
 export const ESP32H21_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-H21 RTC Watchdog Timer registers (LP_WDT)
+export const ESP32H21_DR_REG_LP_WDT_BASE = 0x600b1c00;
+export const ESP32H21_RTC_CNTL_WDTWPROTECT_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x001c;
+export const ESP32H21_RTC_CNTL_WDTCONFIG0_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x0000;
+export const ESP32H21_RTC_CNTL_WDTCONFIG1_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32H21_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
+export const ESP32H21_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
 export const ESP32P4_SPI_REG_BASE = 0x5008d000;
 export const ESP32P4_BASEFUSEADDR = 0x5012d000;
 export const ESP32P4_EFUSE_BLOCK1_ADDR = ESP32P4_BASEFUSEADDR + 0x044;
@@ -217,6 +296,28 @@ export const ESP32P4_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32P4_SPI_W0_OFFS = 0x58;
 export const ESP32P4_UART_DATE_REG_ADDR = 0x500ca000 + 0x8c;
 export const ESP32P4_BOOTLOADER_FLASH_OFFSET = 0x2000;
+// ESP32-P4 RTC Watchdog Timer registers
+export const ESP32P4_DR_REG_LP_WDT_BASE = 0x50116000;
+export const ESP32P4_RTC_CNTL_WDTWPROTECT_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_WPROTECT_REG
+export const ESP32P4_RTC_CNTL_WDTCONFIG0_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_CONFIG0_REG
+export const ESP32P4_RTC_CNTL_WDTCONFIG1_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_CONFIG1_REG
+export const ESP32P4_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
+export const ESP32P4_RTC_CNTL_SWD_CONF_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x001c; // RTC_WDT_SWD_CONFIG_REG
+export const ESP32P4_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
+export const ESP32P4_RTC_CNTL_SWD_WPROTECT_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0020; // RTC_WDT_SWD_WPROTECT_REG
+export const ESP32P4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // RTC_WDT_SWD_WKEY, same as WDT key in this case
+// ESP32-P4 USB-JTAG/Serial and USB-OTG detection
+// Note: UARTDEV_BUF_NO is dynamic based on chip revision
+// Revision < 300: 0x4FF3FEB0 + 24 = 0x4FF3FEC8
+// Revision >= 300: 0x4FFBFEB0 + 24 = 0x4FFBFEC8
+export const ESP32P4_UARTDEV_BUF_NO_REV0 = 0x4ff3fec8; // Variable in ROM .bss (revision < 300)
+export const ESP32P4_UARTDEV_BUF_NO_REV300 = 0x4ffbfec8; // Variable in ROM .bss (revision >= 300)
+export const ESP32P4_UARTDEV_BUF_NO_USB_OTG = 5; // The above var when USB-OTG is used
+export const ESP32P4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6; // The above var when USB-JTAG/Serial is used
+export const ESP32P4_GPIO_STRAP_REG = 0x500e0038;
+export const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 0x8; // Not download mode
+export const ESP32P4_RTC_CNTL_OPTION1_REG = 0x50110008;
+export const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x4; // Is download mode forced over USB?
 export const ESP32S31_SPI_REG_BASE = 0x20500000;
 export const ESP32S31_BASEFUSEADDR = 0x20715000;
 export const ESP32S31_EFUSE_BLOCK1_ADDR = ESP32S31_BASEFUSEADDR + 0x044;

package/dist/esp_loader.d.ts

@@ -16,14 +16,26 @@ export declare class ESPLoader extends EventTarget {
     __inputBuffer?: number[];
     __inputBufferReadIndex?: number;
     __totalBytesRead?: number;
-    private __currentBaudRate;
+    currentBaudRate: number;
     private _maxUSBSerialBaudrate?;
     __reader?: ReadableStreamDefaultReader<Uint8Array>;
+    private SLIP_END;
+    private SLIP_ESC;
+    private SLIP_ESC_END;
+    private SLIP_ESC_ESC;
     private _isESP32S2NativeUSB;
     private _initializationSucceeded;
     private __commandLock;
     private __isReconfiguring;
     private __abandonCurrentOperation;
+    private _suppressDisconnect;
+    private __consoleMode;
+    _isUsbJtagOrOtg: boolean | undefined;
+    /**
+     * Check if device is using USB-JTAG or USB-OTG (not external serial chip)
+     * Returns undefined if not yet determined
+     */
+    get isUsbJtagOrOtg(): boolean | undefined;
     private __adaptiveBlockMultiplier;
     private __adaptiveMaxInFlightMultiplier;
     private __consecutiveSuccessfulChunks;
@@ -38,6 +50,9 @@ export declare class ESPLoader extends EventTarget {
     set chipRevision(value: number | null);
     get chipVariant(): string | null;
     set chipVariant(value: string | null);
+    private get _consoleMode();
+    private set _consoleMode(value);
+    setConsoleMode(value: boolean): void;
     private get _inputBuffer();
     private get _inputBufferReadIndex();
     private set _inputBufferReadIndex(value);
@@ -108,6 +123,16 @@ export declare class ESPLoader extends EventTarget {
      * Classic reset for Web Serial (Desktop) DTR = IO0, RTS = EN
      */
     hardResetClassic(): Promise<void>;
+    /**
+     * Reset to firmware mode (not bootloader) for Web Serial
+     * Keeps IO0=HIGH during reset so chip boots into firmware
+     */
+    hardResetToFirmware(): Promise<void>;
+    /**
+     * Reset to firmware mode (not bootloader) for WebUSB
+     * Keeps IO0=HIGH during reset so chip boots into firmware
+     */
+    hardResetToFirmwareWebUSB(): Promise<void>;
     /**
      * @name hardResetUnixTight
      * Unix Tight reset for Web Serial (Desktop) - sets DTR and RTS simultaneously
@@ -174,10 +199,52 @@ export declare class ESPLoader extends EventTarget {
     connectWithResetStrategies(): Promise<void>;
     /**
      * @name watchdogReset
-     * Watchdog reset for ESP32-S2/S3 with USB-OTG
+     * Watchdog reset for ESP32-S2/S3/C3 with USB-OTG or USB-JTAG/Serial
      * Uses RTC watchdog timer to reset the chip - works when DTR/RTS signals are not available
+     * This is an alias for rtcWdtResetChipSpecific() for backwards compatibility
      */
     watchdogReset(): Promise<void>;
+    /**
+     * Check if current chip is using USB-OTG
+     * Supports ESP32-S2 and ESP32-S3
+     */
+    usingUsbOtg(): Promise<boolean>;
+    /**
+     * Check if current chip is using USB-JTAG/Serial
+     * Supports ESP32-S3 and ESP32-C3
+     */
+    usingUsbJtagSerial(): Promise<boolean>;
+    /**
+     * Get chip revision for ESP32-C3
+     * Reads from EFUSE registers and calculates revision
+     */
+    getChipRevisionC3(): Promise<number>;
+    /**
+     * RTC watchdog timer reset for ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C5, ESP32-C6, and ESP32-P4
+     * Uses specific registers for each chip family
+     * Note: ESP32-H2 does NOT support WDT reset
+     */
+    rtcWdtResetChipSpecific(): Promise<void>;
+    /**
+     * Helper: Check if USB-based WDT reset should be used for S2/S3
+     * Returns true if WDT reset was performed, false otherwise
+     */
+    private tryUsbWdtReset;
+    /**
+     * Chip-specific hard reset for ESP32-S2
+     * Checks if using USB-JTAG/Serial and uses watchdog reset if necessary
+     */
+    hardResetS2(): Promise<void>;
+    /**
+     * Chip-specific hard reset for ESP32-S3
+     * Checks if using USB-JTAG/Serial and uses watchdog reset if necessary
+     */
+    hardResetS3(): Promise<void>;
+    /**
+     * Chip-specific hard reset for ESP32-C3
+     * Checks if using USB-JTAG/Serial and uses watchdog reset if necessary
+     */
+    hardResetC3(): Promise<void>;
     hardReset(bootloader?: boolean): Promise<void>;
     /**
      * @name macAddr
@@ -318,10 +385,43 @@ export declare class ESPLoader extends EventTarget {
     private set _writer(value);
     private get _writeChain();
     private set _writeChain(value);
-    private get _currentBaudRate();
-    private set _currentBaudRate(value);
     writeToStream(data: number[]): Promise<void>;
     disconnect(): Promise<void>;
+    /**
+     * @name releaseReaderWriter
+     * Release reader and writer locks without closing the port
+     * Used when switching to console mode
+     */
+    releaseReaderWriter(): Promise<void>;
+    /**
+     * @name resetToFirmware
+     * Public method to reset device from bootloader to firmware for console mode
+     * Automatically detects USB-JTAG/Serial and USB-OTG devices and performs appropriate reset
+     * @returns true if reset was performed, false if not needed
+     */
+    resetToFirmware(): Promise<boolean>;
+    /**
+     * @name detectUsbConnectionType
+     * Detect if device is using USB-JTAG/Serial or USB-OTG (not external serial chip)
+     * This helper extracts the detection logic from initialize() for reuse
+     * @returns true if USB-JTAG or USB-OTG, false if external serial chip
+     * @throws Error if detection fails and chipFamily is not set
+     */
+    private detectUsbConnectionType;
+    /**
+     * @name enterConsoleMode
+     * Prepare device for console mode by resetting to firmware
+     * Handles both USB-JTAG/OTG devices (closes port) and external serial chips (keeps port open)
+     * @returns true if port was closed (USB-JTAG), false if port stays open (serial chip)
+     */
+    enterConsoleMode(): Promise<boolean>;
+    /**
+     * @name _resetToFirmwareIfNeeded
+     * Reset device from bootloader to firmware when switching to console mode
+     * Detects USB-JTAG/Serial and USB-OTG devices and performs appropriate reset
+     * @returns true if reconnect was performed, false otherwise
+     */
+    private _resetToFirmwareIfNeeded;
     /**
      * @name reconnectAndResume
      * Reconnect the serial port to flush browser buffers and reload stub
@@ -333,6 +433,29 @@ export declare class ESPLoader extends EventTarget {
      * This is needed after Improv or other operations that leave ESP in firmware mode
      */
     reconnectToBootloader(): Promise<void>;
+    /**
+     * @name exitConsoleMode
+     * Exit console mode and return to bootloader
+     * For ESP32-S2, uses reconnectToBootloader which will trigger port change
+     * @returns true if manual reconnection is needed (ESP32-S2), false otherwise
+     */
+    exitConsoleMode(): Promise<boolean>;
+    /**
+     * @name isConsoleResetSupported
+     * Check if console reset is supported for this device
+     * ESP32-S2 USB-JTAG/CDC does not support reset in console mode
+     * because any reset causes USB port to be lost (hardware limitation)
+     */
+    isConsoleResetSupported(): boolean;
+    /**
+     * @name resetInConsoleMode
+     * Reset device while in console mode (firmware mode)
+     *
+     * NOTE: For ESP32-S2 USB-JTAG/CDC, ANY reset (hardware or software) causes
+     * the USB port to be lost because the device switches USB modes during reset.
+     * This is a hardware limitation - use isConsoleResetSupported() to check first.
+     */
+    resetInConsoleMode(): Promise<void>;
     /**
      * @name drainInputBuffer
      * Actively drain the input buffer by reading data for a specified time.
@@ -356,9 +479,17 @@ export declare class ESPLoader extends EventTarget {
      * @param addr - Address to read from
      * @param size - Number of bytes to read
      * @param onPacketReceived - Optional callback function called when packet is received
+     * @param options - Optional parameters for advanced control
+     *   - chunkSize: Amount of data to request from ESP in one command (bytes)
+     *   - blockSize: Size of each data block sent by ESP (bytes)
+     *   - maxInFlight: Maximum unacknowledged bytes (bytes)
      * @returns Uint8Array containing the flash data
      */
-    readFlash(addr: number, size: number, onPacketReceived?: (packet: Uint8Array, progress: number, totalSize: number) => void): Promise<Uint8Array>;
+    readFlash(addr: number, size: number, onPacketReceived?: (packet: Uint8Array, progress: number, totalSize: number) => void, options?: {
+        chunkSize?: number;
+        blockSize?: number;
+        maxInFlight?: number;
+    }): Promise<Uint8Array>;
 }
 declare class EspStubLoader extends ESPLoader {
     IS_STUB: boolean;