schematex 0.6.5 → 0.6.6

package/dist/{chunk-RVHOCGHT.js.map → chunk-3GAPHXCE.js.map}

@@ -1 +1 @@
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Keep it with\n      // the `unknown` sentinel + the raw token so the renderer draws a flagged\n      // placeholder and the lint pass warns. Blanking the whole diagram on one\n      // bad gate word is hostile to LLM-generated DSL.\n      if (GATE_TYPES.has(rawType)) {\n        gates.push({ id, gateType: rawType as LogicGateType, inputs: gInputs, moduleId });\n      } else {\n        gates.push({ id, gateType: \"unknown\", rawType: gateMatch[2], inputs: gInputs, moduleId });\n        warnings.push(\n          `Gate \"${id}\" has unrecognised type \"${gateMatch[2]}\"; drawn as a flagged placeholder.`\n        );\n      }\n      continue;\n    }\n  }\n\n  if (moduleStack.length > 0) {\n    throw new LogicParseError(`Unclosed module (${moduleStack.length} open)`);\n  }\n\n  // Wire outputs: if output not explicitly mapped, look for gate with same id\n  for (const out of outputs) {\n    const mapped = explicitOutputFrom.get(out.id);\n    if (mapped) out.from = mapped;\n    else if (gates.some((g) => g.id === out.id)) out.from = out.id;\n  }\n\n  // Resolve undefined signal references: auto-declare them as inputs and\n  // emit a warning. Hard-failing here is hostile to LLM-generated DSL where\n  // the model often forgets the explicit `input` line — see playbook.\n  const known = new Set<string>([\n    ...inputs.map((i) => i.id),\n    ...gates.map((g) => g.id),\n  ]);\n  const autoDeclared = new Set<string>();\n  for (const g of gates) {\n    for (const inp of g.inputs) {\n      const isLow = inp.startsWith(\"~\");\n      const clean = isLow ? inp.slice(1) : inp;\n      if (!known.has(clean) && !autoDeclared.has(clean)) {\n        autoDeclared.add(clean);\n        inputs.push({\n          id: clean,\n          label: clean,\n          isActiveLow: isLow || undefined,\n          autoDeclared: true,\n        });\n        warnings.push(\n          `Signal \"${clean}\" referenced in gate ${g.id} was not declared; auto-declared as input.`\n        );\n      }\n    }\n  }\n\n  return {\n    type: \"logic\",\n    title,\n    style: style ?? \"ansi\",\n    inputs,\n    outputs,\n    gates,\n    modules: modules.length > 0 ? modules : undefined,\n    warnings: warnings.length > 0 ? warnings : undefined,\n  };\n}\n","import type { LogicGateType } from \"../../core/types\";\n\n// Normalized gate geometry: combinational gates fit in 100×60; sequential in 60×80.\nexport interface GateGeometry {\n  width: number;\n  height: number;\n  inputPins: Array<{ id: string; x: number; y: number; label?: string }>;\n  outputPins: Array<{ id: string; x: number; y: number; label?: string; bubble?: boolean }>;\n  /** Body SVG path (ANSI) */\n  ansiPath: string;\n  /** Output bubble? */\n  outputBubble?: boolean;\n  /** Clock triangle pin id (sequential) */\n  clockPin?: string;\n  /** IEC label inside rectangle */\n  iecLabel?: string;\n}\n\nfunction combPins(nInputs: number, _width: number, leftX: number): Array<{ id: string; x: number; y: number }> {\n  const pins: Array<{ id: string; x: number; y: number }> = [];\n  if (nInputs === 1) {\n    pins.push({ id: \"in1\", x: leftX, y: 30 });\n  } else if (nInputs === 2) {\n    pins.push({ id: \"in1\", x: leftX, y: 15 });\n    pins.push({ id: \"in2\", x: leftX, y: 45 });\n  } else {\n    const step = 50 / (nInputs - 1);\n    for (let i = 0; i < nInputs; i++) {\n      pins.push({ id: `in${i + 1}`, x: leftX, y: 5 + step * i });\n    }\n  }\n  return pins;\n}\n\nexport function getGateGeometry(\n  gateType: LogicGateType,\n  inputCount: number\n): GateGeometry {\n  switch (gateType) {\n    case \"AND\":\n    case \"NAND\": {\n      const bubble = gateType === \"NAND\";\n      return {\n        width: bubble ? 90 : 80,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 20).map((p) => ({ ...p, x: 20 })),\n        outputPins: [{ id: \"out\", x: bubble ? 90 : 80, y: 30, bubble }],\n        ansiPath: \"M 20,60 L 20,0 Q 80,0 80,30 Q 80,60 20,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"&\",\n      };\n    }\n    case \"OR\":\n    case \"NOR\": {\n      const bubble = gateType === \"NOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 18).map((p) => ({ ...p, x: 18 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath: \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"≥1\",\n      };\n    }\n    case \"XOR\":\n    case \"XNOR\": {\n      const bubble = gateType === \"XNOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 12).map((p) => ({ ...p, x: 12 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath:\n          \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z M 8,60 Q 3,30 8,0\",\n        outputBubble: bubble,\n        iecLabel: \"=1\",\n      };\n    }\n    case \"NOT\": {\n      return {\n        width: 70,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 70, y: 30, bubble: true }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: true,\n        iecLabel: \"1\",\n      };\n    }\n    case \"BUF\":\n    case \"SCHMITT\": {\n      return {\n        width: 60,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 60, y: 30 }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        iecLabel: \"1\",\n      };\n    }\n    case \"TRISTATE_BUF\":\n    case \"TRISTATE_INV\":\n    case \"OPEN_DRAIN\": {\n      const bubble = gateType === \"TRISTATE_INV\";\n      return {\n        width: bubble ? 70 : 60,\n        height: 70,\n        inputPins: [\n          { id: \"in1\", x: 10, y: 30 },\n          { id: \"en\", x: 35, y: 65, label: \"EN\" },\n        ],\n        outputPins: [{ id: \"out\", x: bubble ? 70 : 60, y: 30, bubble }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: bubble,\n        iecLabel: \"1\",\n      };\n    }\n    case \"DFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"CLK\", x: 0, y: 50, label: \"\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"DFF\",\n      };\n    }\n    case \"JKFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"J\", x: 0, y: 15, label: \"J\" },\n          { id: \"CLK\", x: 0, y: 40 },\n          { id: \"K\", x: 0, y: 65, label: \"K\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"JK\",\n      };\n    }\n    case \"SRFF\":\n    case \"LATCH_SR\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"S\", x: 0, y: 20, label: \"S\" },\n          { id: \"R\", x: 0, y: 60, label: \"R\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"SR\",\n      };\n    }\n    case \"TFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"T\", x: 0, y: 20, label: \"T\" },\n          { id: \"CLK\", x: 0, y: 50 },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"T\",\n      };\n    }\n    case \"LATCH_D\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"E\", x: 0, y: 60, label: \"E\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"D\",\n      };\n    }\n    case \"unknown\": {\n      // Visibly-flagged placeholder for an unrecognised gate token. A box with\n      // a \"?\" label — never a real gate shape, so it can't be mistaken for one.\n      const ins = Math.max(inputCount, 1);\n      const inputPins = combPins(ins, 90, 0).map((p) => ({ ...p, x: 0 }));\n      return {\n        width: 90,\n        height: 70,\n        inputPins,\n        outputPins: [{ id: \"out\", x: 90, y: 35 }],\n        ansiPath: \"M 0,0 H 90 V 70 H 0 Z\",\n        iecLabel: \"?\",\n      };\n    }\n    default: {\n      // Generic box for MUX/DEMUX/DECODER/ENCODER/COUNTER/SHIFT_REG\n      const ins = Math.max(inputCount, 2);\n      const inputPins = combPins(ins, 100, 0).map((p, i) => ({\n        ...p,\n        x: 0,\n        label: `I${i}`,\n      }));\n      return {\n        width: 100,\n        height: 80,\n        inputPins,\n        outputPins: [{ id: \"out\", x: 100, y: 40 }],\n        ansiPath: \"M 0,0 H 100 V 80 H 0 Z\",\n        iecLabel: gateType,\n      };\n    }\n  }\n}\n","import type { LogicGateAST } from \"../../core/types\";\nimport { getGateGeometry, type GateGeometry } from \"./symbols\";\n\nexport interface LogicLayoutNode {\n  id: string;\n  kind: \"input\" | \"gate\" | \"output\";\n  x: number;\n  y: number;\n  layer: number;\n  geometry?: GateGeometry;\n  gateType?: string;\n  /** Original (unrecognised) gate token, set only when `gateType === \"unknown\"`. */\n  rawType?: string;\n  label: string;\n  isActiveLow?: boolean;\n}\n\nexport interface LogicLayoutWire {\n  fromNode: string;\n  fromX: number;\n  fromY: number;\n  toNode: string;\n  toX: number;\n  toY: number;\n  isActiveLow?: boolean;\n  path: string;\n}\n\nexport interface LogicLayoutModule {\n  id: string;\n  label: string;\n  x: number;\n  y: number;\n  width: number;\n  height: number;\n}\n\nexport interface LogicLayoutResult {\n  width: number;\n  height: number;\n  nodes: LogicLayoutNode[];\n  wires: LogicLayoutWire[];\n  modules: LogicLayoutModule[];\n}\n\nconst LAYER_GAP = 80; // extra horizontal gap between layers\nconst ROW_GAP = 40;   // vertical gap between rows in same layer\nconst PORT_SIZE = 40; // input/output port pseudo-box width\nconst PORT_H = 30;\n\nexport function layoutLogic(ast: LogicGateAST): LogicLayoutResult {\n  // Determine layer per signal id using longest-path layering\n  const layerOf = new Map<string, number>();\n  for (const inp of ast.inputs) layerOf.set(inp.id, 0);\n\n  // Build dependency map for gates\n  const pending = new Set(ast.gates.map((g) => g.id));\n  let safety = 0;\n  while (pending.size > 0 && safety++ < 1000) {\n    for (const g of ast.gates) {\n      if (!pending.has(g.id)) continue;\n      let maxDep = -1;\n      let ready = true;\n      for (const inp of g.inputs) {\n        const clean = inp.startsWith(\"~\") ? inp.slice(1) : inp;\n        const l = layerOf.get(clean);\n        if (l === undefined) {\n          ready = false;\n          break;\n        }\n        if (l > maxDep) maxDep = l;\n      }\n      if (ready) {\n        layerOf.set(g.id, maxDep + 1);\n        pending.delete(g.id);\n      }\n    }\n  }\n  if (pending.size > 0) {\n    // cycle or unresolved: force layer 1\n    for (const id of pending) layerOf.set(id, 1);\n  }\n\n  const outputLayer =\n    Math.max(0, ...Array.from(layerOf.values())) + 1;\n  // All outputs get a terminal label node. Use synthetic id to avoid colliding\n  // with a gate that shares the output's name (e.g. `output Y; Y = AND(A,B)`).\n  const outTermId = (o: { id: string }) => `$out$${o.id}`;\n  const portOutputs = ast.outputs.map((o) => ({\n    ...o,\n    termId: outTermId(o),\n    source: o.from,\n  }));\n  for (const o of portOutputs) layerOf.set(o.termId, outputLayer);\n\n  // Group ids by layer\n  const layers = new Map<number, string[]>();\n  const addToLayer = (id: string, layer: number) => {\n    if (!layers.has(layer)) layers.set(layer, []);\n    layers.get(layer)!.push(id);\n  };\n  for (const i of ast.inputs) addToLayer(i.id, 0);\n  for (const g of ast.gates) addToLayer(g.id, layerOf.get(g.id)!);\n  for (const o of portOutputs) addToLayer(o.termId, outputLayer);\n\n  // Compute sizes per node (precompute geometries for gates)\n  const gateGeoms = new Map<string, GateGeometry>();\n  for (const g of ast.gates) {\n    gateGeoms.set(g.id, getGateGeometry(g.gateType, g.inputs.length));\n  }\n\n  // Assign coordinates\n  const nodes: LogicLayoutNode[] = [];\n  const sortedLayers = Array.from(layers.keys()).sort((a, b) => a - b);\n\n  // compute each layer's widest node\n  const layerWidth = new Map<number, number>();\n  for (const [layerIdx, ids] of layers) {\n    let maxW = 60;\n    for (const id of ids) {\n      const g = gateGeoms.get(id);\n      if (g && g.width > maxW) maxW = g.width;\n      if (!g && layerIdx === 0) maxW = Math.max(maxW, PORT_SIZE);\n      if (!g && layerIdx === outputLayer) maxW = Math.max(maxW, PORT_SIZE);\n    }\n    layerWidth.set(layerIdx, maxW);\n  }\n\n  let cursorX = 20;\n  const layerStartMap = new Map<number, number>();\n  for (const layerIdx of sortedLayers) {\n    layerStartMap.set(layerIdx, cursorX);\n    cursorX += (layerWidth.get(layerIdx) ?? 60) + LAYER_GAP;\n  }\n  const totalW = cursorX;\n\n  // Compute vertical placement per layer\n  const heightOf = (id: string): number => {\n    const g = gateGeoms.get(id);\n    if (g) return g.height;\n    return PORT_H;\n  };\n\n  // find max column height\n  let maxColH = 0;\n  for (const ids of layers.values()) {\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    if (total > maxColH) maxColH = total;\n  }\n  const totalH = maxColH + 80;\n\n  const nodeInfo = new Map<string, LogicLayoutNode>();\n  for (const [layerIdx, ids] of layers) {\n    const xStart = layerStartMap.get(layerIdx)!;\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    let y = 40 + (maxColH - total) / 2;\n    for (const id of ids) {\n      const h = heightOf(id);\n      const g = gateGeoms.get(id);\n      let node: LogicLayoutNode;\n      if (layerIdx === 0) {\n        const inp = ast.inputs.find((i) => i.id === id)!;\n        node = {\n          id,\n          kind: \"input\",\n          x: xStart,\n          y,\n          layer: 0,\n          label: inp.label,\n          isActiveLow: inp.isActiveLow,\n        };\n      } else if (layerIdx === outputLayer && !g && id.startsWith(\"$out$\")) {\n        const out = portOutputs.find((o) => o.termId === id)!;\n        node = {\n          id,\n          kind: \"output\",\n          x: xStart,\n          y,\n          layer: outputLayer,\n          label: out.label,\n          isActiveLow: out.isActiveLow,\n        };\n      } else {\n        node = {\n          id,\n          kind: \"gate\",\n          x: xStart,\n          y,\n          layer: layerIdx,\n          geometry: g,\n          gateType: ast.gates.find((gg) => gg.id === id)!.gateType,\n          rawType: ast.gates.find((gg) => gg.id === id)!.rawType,\n          label: id,\n        };\n      }\n      nodes.push(node);\n      nodeInfo.set(id, node);\n      y += h + ROW_GAP;\n    }\n  }\n\n  // Wires\n  const wires: LogicLayoutWire[] = [];\n  const getSourcePoint = (id: string) => {\n    const n = nodeInfo.get(id);\n    if (!n) return null;\n    if (n.kind === \"input\") return { x: n.x + PORT_SIZE, y: n.y + PORT_H / 2 };\n    if (n.kind === \"gate\" && n.geometry) {\n      const out = n.geometry.outputPins[0];\n      return { x: n.x + out.x, y: n.y + out.y };\n    }\n    return null;\n  };\n\n  for (const g of ast.gates) {\n    const target = nodeInfo.get(g.id);\n    if (!target || !target.geometry) continue;\n    g.inputs.forEach((rawInp, idx) => {\n      const isLow = rawInp.startsWith(\"~\");\n      const srcId = isLow ? rawInp.slice(1) : rawInp;\n      const src = getSourcePoint(srcId);\n      if (!src) return;\n      const pin = target.geometry!.inputPins[idx];\n      if (!pin) return;\n      const toX = target.x + pin.x;\n      const toY = target.y + pin.y;\n      const midX = (src.x + toX) / 2;\n      const path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n      wires.push({\n        fromNode: srcId,\n        fromX: src.x,\n        fromY: src.y,\n        toNode: g.id,\n        toX,\n        toY,\n        isActiveLow: isLow,\n        path,\n      });\n    });\n  }\n\n  // Output port wires\n  for (const o of portOutputs) {\n    const src = getSourcePoint(o.source);\n    const target = nodeInfo.get(o.termId);\n    if (!src || !target || target.kind !== \"output\") continue;\n    const toX = target.x;\n    const toY = target.y + PORT_H / 2;\n    let path: string;\n    if (Math.abs(src.y - toY) < 0.5) {\n      path = `M ${src.x},${src.y} L ${toX},${toY}`;\n    } else {\n      const midX = (src.x + toX) / 2;\n      path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n    }\n    wires.push({\n      fromNode: o.source,\n      fromX: src.x,\n      fromY: src.y,\n      toNode: o.termId,\n      toX,\n      toY,\n      path,\n    });\n  }\n\n  // Module bounding boxes (dashed enclosure for sub-circuits)\n  const modules: LogicLayoutModule[] = [];\n  if (ast.modules && ast.modules.length > 0) {\n    const PAD = 14;\n    for (const mod of ast.modules) {\n      const memberIds = new Set(\n        ast.gates.filter((g) => g.moduleId === mod.id).map((g) => g.id)\n      );\n      if (memberIds.size === 0) continue;\n      let minX = Infinity, minY = Infinity, maxX = -Infinity, maxY = -Infinity;\n      for (const n of nodes) {\n        if (!memberIds.has(n.id)) continue;\n        const w = n.geometry?.width ?? 60;\n        const h = n.geometry?.height ?? 60;\n        if (n.x < minX) minX = n.x;\n        if (n.y < minY) minY = n.y;\n        if (n.x + w > maxX) maxX = n.x + w;\n        if (n.y + h > maxY) maxY = n.y + h;\n      }\n      if (!isFinite(minX)) continue;\n      modules.push({\n        id: mod.id,\n        label: mod.label,\n        x: minX - PAD,\n        y: minY - PAD - 4,\n        width: maxX - minX + PAD * 2,\n        height: maxY - minY + PAD * 2 + 4,\n      });\n    }\n  }\n\n  return { width: totalW, height: totalH, nodes, wires, modules };\n}\n","import type { LogicGateAST, LogicGateStyle, RenderConfig } from \"../../core/types\";\nimport { layoutLogic } from \"./layout\";\nimport {\n  svgRoot,\n  defs,\n  group,\n  el,\n  circle,\n  path as pathEl,\n  text,\n  title as titleEl,\n  desc,\n  polygon,\n} from \"../../core/svg\";\nimport { resolveIndustrialTheme } from \"../../core/theme\";\n\nconst PORT_SIZE = 40;\nconst PORT_H = 30;\n\nfunction renderGateBody(\n  n: ReturnType<typeof layoutLogic>[\"nodes\"][number],\n  style: LogicGateStyle\n): string[] {\n  const out: string[] = [];\n  if (!n.geometry) return out;\n  const g = n.geometry;\n\n  if (style === \"iec\") {\n    // Rectangle\n    out.push(\n      el(\"rect\", {\n        x: 0,\n        y: 0,\n        width: g.width,\n        height: g.height,\n        class: \"schematex-logic-gate-body\",\n      })\n    );\n    if (g.iecLabel) {\n      out.push(\n        text(\n          {\n            x: g.width / 2,\n            y: g.height / 2 + 4,\n            class: \"schematex-logic-gate-iec-label\",\n            \"text-anchor\": \"middle\",\n          },\n          g.iecLabel\n        )\n      );\n    }\n  } else {\n    out.push(\n      el(\"path\", { d: g.ansiPath, class: \"schematex-logic-gate-body\" })\n    );\n  }\n\n  // Unrecognised gate: stamp a centred \"?\" so the ANSI box reads as a flagged\n  // placeholder (IEC already centres the \"?\" via iecLabel above).\n  if (n.gateType === \"unknown\" && style !== \"iec\") {\n    out.push(\n      text(\n        {\n          x: g.width / 2,\n          y: g.height / 2 + 6,\n          class: \"schematex-logic-gate-iec-label\",\n          \"text-anchor\": \"middle\",\n        },\n        \"?\"\n      )\n    );\n  }\n\n  // Output bubble\n  if (g.outputBubble) {\n    const op = g.outputPins[0];\n    out.push(\n      circle({\n        cx: op.x - 4,\n        cy: op.y,\n        r: 4,\n        class: \"schematex-logic-bubble\",\n      })\n    );\n  }\n\n  // Clock triangle\n  if (g.clockPin) {\n    const cp = g.inputPins.find((p) => p.id === g.clockPin);\n    if (cp) {\n      out.push(\n        polygon({\n          points: `${cp.x},${cp.y - 5} ${cp.x + 8},${cp.y} ${cp.x},${cp.y + 5}`,\n          class: \"schematex-logic-clock-tri\",\n        })\n      );\n    }\n  }\n\n  // Qn bubble (sequential)\n  for (const op of g.outputPins) {\n    if (op.bubble && op.id !== \"out\") {\n      out.push(\n        circle({\n          cx: op.x + 4,\n          cy: op.y,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n  }\n\n  // Pin labels\n  for (const pin of g.inputPins) {\n    if (pin.label && pin.id !== g.clockPin) {\n      out.push(\n        text(\n          {\n            x: pin.x + 5,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n  for (const pin of g.outputPins) {\n    if (pin.label) {\n      out.push(\n        text(\n          {\n            x: pin.x - 6,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n            \"text-anchor\": \"end\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n\n  // Gate type label (center top, small)\n  if (style === \"ansi\" && g.iecLabel && g.height >= 60) {\n    const labelX = g.width / 2;\n    const labelY = g.height + 14;\n    out.push(\n      text(\n        {\n          x: labelX,\n          y: labelY,\n          class: \"schematex-logic-gate-type\",\n          \"text-anchor\": \"middle\",\n        },\n        n.gateType === \"unknown\" ? n.rawType ?? \"?\" : n.gateType ?? \"\"\n      )\n    );\n  }\n\n  return out;\n}\n\nexport function renderLogic(ast: LogicGateAST, config?: RenderConfig): string {\n  const style: LogicGateStyle = ast.style ?? \"ansi\";\n  const layout = layoutLogic(ast);\n  const { width, height } = layout;\n  const t = resolveIndustrialTheme(config?.theme ?? \"default\");\n\n  const gateSvgs: string[] = [];\n  const portSvgs: string[] = [];\n  const moduleSvgs: string[] = [];\n\n  for (const m of layout.modules) {\n    moduleSvgs.push(\n      group({ \"data-module-id\": m.id }, [\n        el(\"rect\", {\n          x: m.x,\n          y: m.y,\n          width: m.width,\n          height: m.height,\n          rx: 6,\n          class: \"schematex-logic-module\",\n        }),\n        text(\n          {\n            x: m.x + 10,\n            y: m.y + 14,\n            class: \"schematex-logic-module-label\",\n          },\n          m.label\n        ),\n      ])\n    );\n  }\n\n  for (const n of layout.nodes) {\n    if (n.kind === \"gate\") {\n      gateSvgs.push(\n        group(\n          {\n            transform: `translate(${n.x}, ${n.y})`,\n            \"data-gate-id\": n.id,\n            \"data-gate-type\": n.gateType ?? \"\",\n          },\n          renderGateBody(n, style)\n        )\n      );\n    } else if (n.kind === \"input\") {\n      // Label + short stub line; no rectangle.\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"input\" }, [\n          text(\n            {\n              x: 0,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n          el(\"line\", {\n            x1: PORT_SIZE - 12,\n            y1: cy,\n            x2: n.isActiveLow ? PORT_SIZE - 8 : PORT_SIZE,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          n.isActiveLow\n            ? circle({\n                cx: PORT_SIZE - 4,\n                cy,\n                r: 4,\n                class: \"schematex-logic-bubble\",\n              })\n            : \"\",\n        ])\n      );\n    } else if (n.kind === \"output\") {\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"output\" }, [\n          el(\"line\", {\n            x1: 0,\n            y1: cy,\n            x2: 12,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          text(\n            {\n              x: 16,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n        ])\n      );\n    }\n  }\n\n  const wireSvgs = layout.wires.map((w) => {\n    const extras: string[] = [];\n    if (w.isActiveLow) {\n      extras.push(\n        circle({\n          cx: w.toX - 4,\n          cy: w.toY,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n    return [\n      pathEl({\n        d: w.path,\n        class: \"schematex-logic-wire\",\n        \"data-from\": w.fromNode,\n        \"data-to\": w.toNode,\n      }),\n      ...extras,\n    ].join(\"\");\n  });\n\n  const css = `\n.schematex-logic { font-family: system-ui, -apple-system, sans-serif; }\n.schematex-logic-gate-body { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.75; stroke-linejoin: round; }\n.schematex-logic-bubble { fill: ${t.bg}; stroke: ${t.strokeHeavy}; stroke-width: 1.5; }\n.schematex-logic-clock-tri { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.5; stroke-linejoin: round; }\n.schematex-logic-wire { stroke: ${t.strokeHeavy}; stroke-width: 1.5; fill: none; stroke-linecap: square; }\n.schematex-logic-port-label { font: 13px system-ui, sans-serif; fill: ${t.text}; }\n.schematex-logic-pin-label { font: 9px sans-serif; fill: ${t.stroke}; }\n.schematex-logic-gate-type { font: 10px sans-serif; fill: ${t.textMuted}; }\n.schematex-logic-gate-iec-label { font: bold 13px sans-serif; fill: ${t.text}; }\n.schematex-logic-title { font: bold 14px sans-serif; fill: ${t.text}; }\n.schematex-logic-module { fill: none; stroke: ${t.textMuted}; stroke-width: 1.25; stroke-dasharray: 6 4; }\n.schematex-logic-module-label { font: 11px sans-serif; fill: ${t.textMuted}; font-style: italic; }\n[data-gate-type=\"unknown\"] .schematex-logic-gate-body { stroke: ${t.accent}; stroke-dasharray: 5 3; }\n[data-gate-type=\"unknown\"] .schematex-logic-gate-iec-label { fill: ${t.accent}; }\n`.trim();\n\n  const titleSvg = ast.title\n    ? text(\n        {\n          x: width / 2,\n          y: 18,\n          \"text-anchor\": \"middle\",\n          class: \"schematex-logic-title\",\n        },\n        ast.title\n      )\n    : \"\";\n\n  return svgRoot(\n    {\n      class: \"schematex-logic\",\n      viewBox: `0 0 ${width} ${height + (ast.title ? 20 : 0)}`,\n      width,\n      height: height + (ast.title ? 20 : 0),\n      role: \"img\",\n      \"data-diagram-type\": \"logic\",\n    },\n    [\n      titleEl(ast.title ?? \"Logic Gate Diagram\"),\n      desc(\n        `Logic gate diagram with ${ast.gates.length} gates, ${ast.inputs.length} inputs, ${ast.outputs.length} outputs`\n      ),\n      defs([el(\"style\", {}, css)]),\n      group(\n        { transform: `translate(0, ${ast.title ? 20 : 0})` },\n        [\n          group({ class: \"schematex-logic-modules\" }, moduleSvgs),\n          group({ class: \"schematex-logic-wires\" }, wireSvgs),\n          group({ class: \"schematex-logic-gates\" }, gateSvgs),\n          group({ class: \"schematex-logic-ports\" }, portSvgs),\n        ]\n      ),\n      titleSvg,\n    ]\n  );\n}\n","import type { SchematexDiagnostic } from \"../../core/diagnostics\";\nimport type { LogicGateAST } from \"../../core/types\";\nimport { didYouMean } from \"../../core/dsl-suggest\";\nimport { parseLogic } from \"./parser\";\n\n// Canonical gate vocabulary for the did-you-mean suggestion on an unknown gate.\n// Kept in sync with GATE_TYPES in the parser.\nconst KNOWN_GATES = [\n  \"AND\", \"OR\", \"NOT\", \"NAND\", \"NOR\", \"XOR\", \"XNOR\", \"BUF\",\n  \"TRISTATE_BUF\", \"TRISTATE_INV\", \"OPEN_DRAIN\", \"SCHMITT\",\n  \"DFF\", \"JKFF\", \"SRFF\", \"TFF\", \"LATCH_SR\", \"LATCH_D\",\n  \"MUX\", \"DEMUX\", \"DECODER\", \"ENCODER\", \"COUNTER\", \"SHIFT_REG\",\n];\n\nexport function lintLogic(text: string): SchematexDiagnostic[] {\n  let ast: LogicGateAST;\n  try {\n    ast = parseLogic(text);\n  } catch {\n    // Parse failures are reported by the normal error path; lint stays silent.\n    return [];\n  }\n  return lintLogicAst(ast);\n}\n\nexport function lintLogicAst(ast: LogicGateAST): SchematexDiagnostic[] {\n  const out: SchematexDiagnostic[] = [];\n  // Unrecognised gate types are kept (drawn as a flagged placeholder) but\n  // warned about so the partial render is analyzable and the engineer gets a\n  // did-you-mean nudge. The engine never silently substitutes a real gate.\n  for (const g of ast.gates) {\n    if (g.gateType !== \"unknown\") continue;\n    const raw = g.rawType ?? \"\";\n    out.push({\n      severity: \"warning\",\n      code: \"LOGIC_UNKNOWN_GATE\",\n      message: `gate \"${g.id}\" has unrecognised type \"${raw}\"; drawn as a flagged placeholder`,\n      hint: `\"${raw}\" is not a known logic gate.${didYouMean(raw.toUpperCase(), KNOWN_GATES)} Valid gates include AND, OR, NOT, NAND, NOR, XOR, DFF, MUX. See docs/reference.`,\n      fatal: false,\n    });\n  }\n  return out;\n}\n","import type { DiagramPlugin } from \"../../core/types\";\nimport { parseLogic } from \"./parser\";\nimport { renderLogic } from \"./renderer\";\nimport { lintLogic } from \"./lint\";\n\nexport const logic: DiagramPlugin = {\n  type: \"logic\",\n  detect(text: string): boolean {\n    const first = text.trim().split(\"\\n\")[0]?.trim().toLowerCase() ?? \"\";\n    return first.startsWith(\"logic\");\n  },\n  parse: parseLogic,\n  lint: lintLogic,\n\n  render(text: string, config): string {\n    const ast = parseLogic(text);\n    return renderLogic(ast, config);\n  },\n};\n\nexport { parseLogic } from \"./parser\";\nexport { renderLogic } from \"./renderer\";\nexport { layoutLogic } from \"./layout\";\nexport { lintLogic, lintLogicAst } from \"./lint\";\n"]}
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type {\n  LogicGateAST,\n  LogicGateInput,\n  LogicGateOutput,\n  LogicGateNode,\n  LogicGateType,\n  LogicGateStyle,\n  LogicGateModule,\n} from \"../../core/types\";\nimport { matchQuotedTitle } from \"../../core/quotes\";\n\nexport class LogicParseError extends Error {\n  constructor(message: string) {\n    super(message);\n    this.name = \"LogicParseError\";\n  }\n}\n\nconst GATE_TYPES = new Set<string>([\n  \"AND\", \"OR\", \"NOT\", \"NAND\", \"NOR\", \"XOR\", \"XNOR\", \"BUF\",\n  \"TRISTATE_BUF\", \"TRISTATE_INV\", \"OPEN_DRAIN\", \"SCHMITT\",\n  \"DFF\", \"JKFF\", \"SRFF\", \"TFF\", \"LATCH_SR\", \"LATCH_D\",\n  \"MUX\", \"DEMUX\", \"DECODER\", \"ENCODER\", \"COUNTER\", \"SHIFT_REG\",\n]);\n\nfunction splitIds(s: string): string[] {\n  return s\n    .split(\",\")\n    .map((x) => x.trim())\n    .filter(Boolean);\n}\n\nfunction parseInputList(s: string): string[] {\n  // Supports named (D=A) or positional. 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Keep it with\n      // the `unknown` sentinel + the raw token so the renderer draws a flagged\n      // placeholder and the lint pass warns. Blanking the whole diagram on one\n      // bad gate word is hostile to LLM-generated DSL.\n      if (GATE_TYPES.has(rawType)) {\n        gates.push({ id, gateType: rawType as LogicGateType, inputs: gInputs, moduleId });\n      } else {\n        gates.push({ id, gateType: \"unknown\", rawType: gateMatch[2], inputs: gInputs, moduleId });\n        warnings.push(\n          `Gate \"${id}\" has unrecognised type \"${gateMatch[2]}\"; drawn as a flagged placeholder.`\n        );\n      }\n      continue;\n    }\n  }\n\n  if (moduleStack.length > 0) {\n    throw new LogicParseError(`Unclosed module (${moduleStack.length} open)`);\n  }\n\n  // Wire outputs: if output not explicitly mapped, look for gate with same id\n  for (const out of outputs) {\n    const mapped = explicitOutputFrom.get(out.id);\n    if (mapped) out.from = mapped;\n    else if (gates.some((g) => g.id === out.id)) out.from = out.id;\n  }\n\n  // Resolve undefined signal references: auto-declare them as inputs and\n  // emit a warning. Hard-failing here is hostile to LLM-generated DSL where\n  // the model often forgets the explicit `input` line — see playbook.\n  const known = new Set<string>([\n    ...inputs.map((i) => i.id),\n    ...gates.map((g) => g.id),\n  ]);\n  const autoDeclared = new Set<string>();\n  for (const g of gates) {\n    for (const inp of g.inputs) {\n      const isLow = inp.startsWith(\"~\");\n      const clean = isLow ? inp.slice(1) : inp;\n      if (!known.has(clean) && !autoDeclared.has(clean)) {\n        autoDeclared.add(clean);\n        inputs.push({\n          id: clean,\n          label: clean,\n          isActiveLow: isLow || undefined,\n          autoDeclared: true,\n        });\n        warnings.push(\n          `Signal \"${clean}\" referenced in gate ${g.id} was not declared; auto-declared as input.`\n        );\n      }\n    }\n  }\n\n  return {\n    type: \"logic\",\n    title,\n    style: style ?? \"ansi\",\n    inputs,\n    outputs,\n    gates,\n    modules: modules.length > 0 ? modules : undefined,\n    warnings: warnings.length > 0 ? warnings : undefined,\n  };\n}\n","import type { LogicGateType } from \"../../core/types\";\n\n// Normalized gate geometry: combinational gates fit in 100×60; sequential in 60×80.\nexport interface GateGeometry {\n  width: number;\n  height: number;\n  inputPins: Array<{ id: string; x: number; y: number; label?: string }>;\n  outputPins: Array<{ id: string; x: number; y: number; label?: string; bubble?: boolean }>;\n  /** Body SVG path (ANSI) */\n  ansiPath: string;\n  /** Output bubble? */\n  outputBubble?: boolean;\n  /** Clock triangle pin id (sequential) */\n  clockPin?: string;\n  /** IEC label inside rectangle */\n  iecLabel?: string;\n}\n\nfunction combPins(nInputs: number, _width: number, leftX: number): Array<{ id: string; x: number; y: number }> {\n  const pins: Array<{ id: string; x: number; y: number }> = [];\n  if (nInputs === 1) {\n    pins.push({ id: \"in1\", x: leftX, y: 30 });\n  } else if (nInputs === 2) {\n    pins.push({ id: \"in1\", x: leftX, y: 15 });\n    pins.push({ id: \"in2\", x: leftX, y: 45 });\n  } else {\n    const step = 50 / (nInputs - 1);\n    for (let i = 0; i < nInputs; i++) {\n      pins.push({ id: `in${i + 1}`, x: leftX, y: 5 + step * i });\n    }\n  }\n  return pins;\n}\n\nexport function getGateGeometry(\n  gateType: LogicGateType,\n  inputCount: number\n): GateGeometry {\n  switch (gateType) {\n    case \"AND\":\n    case \"NAND\": {\n      const bubble = gateType === \"NAND\";\n      return {\n        width: bubble ? 90 : 80,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 20).map((p) => ({ ...p, x: 20 })),\n        outputPins: [{ id: \"out\", x: bubble ? 90 : 80, y: 30, bubble }],\n        ansiPath: \"M 20,60 L 20,0 Q 80,0 80,30 Q 80,60 20,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"&\",\n      };\n    }\n    case \"OR\":\n    case \"NOR\": {\n      const bubble = gateType === \"NOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 18).map((p) => ({ ...p, x: 18 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath: \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"≥1\",\n      };\n    }\n    case \"XOR\":\n    case \"XNOR\": {\n      const bubble = gateType === \"XNOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 12).map((p) => ({ ...p, x: 12 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath:\n          \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z M 8,60 Q 3,30 8,0\",\n        outputBubble: bubble,\n        iecLabel: \"=1\",\n      };\n    }\n    case \"NOT\": {\n      return {\n        width: 70,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 70, y: 30, bubble: true }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: true,\n        iecLabel: \"1\",\n      };\n    }\n    case \"BUF\":\n    case \"SCHMITT\": {\n      return {\n        width: 60,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 60, y: 30 }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        iecLabel: \"1\",\n      };\n    }\n    case \"TRISTATE_BUF\":\n    case \"TRISTATE_INV\":\n    case \"OPEN_DRAIN\": {\n      const bubble = gateType === \"TRISTATE_INV\";\n      return {\n        width: bubble ? 70 : 60,\n        height: 70,\n        inputPins: [\n          { id: \"in1\", x: 10, y: 30 },\n          { id: \"en\", x: 35, y: 65, label: \"EN\" },\n        ],\n        outputPins: [{ id: \"out\", x: bubble ? 70 : 60, y: 30, bubble }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: bubble,\n        iecLabel: \"1\",\n      };\n    }\n    case \"DFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"CLK\", x: 0, y: 50, label: \"\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"DFF\",\n      };\n    }\n    case \"JKFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"J\", x: 0, y: 15, label: \"J\" },\n          { id: \"CLK\", x: 0, y: 40 },\n          { id: \"K\", x: 0, y: 65, label: \"K\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"JK\",\n      };\n    }\n    case \"SRFF\":\n    case \"LATCH_SR\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"S\", x: 0, y: 20, label: \"S\" },\n          { id: \"R\", x: 0, y: 60, label: \"R\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"SR\",\n      };\n    }\n    case \"TFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"T\", x: 0, y: 20, label: \"T\" },\n          { id: \"CLK\", x: 0, y: 50 },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"T\",\n      };\n    }\n    case \"LATCH_D\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"E\", x: 0, y: 60, label: \"E\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"D\",\n      };\n    }\n    case \"unknown\": {\n      // Visibly-flagged placeholder for an unrecognised gate token. A box with\n      // a \"?\" label — never a real gate shape, so it can't be mistaken for one.\n      const ins = Math.max(inputCount, 1);\n      const inputPins = combPins(ins, 90, 0).map((p) => ({ ...p, x: 0 }));\n      return {\n        width: 90,\n        height: 70,\n        inputPins,\n        outputPins: [{ id: \"out\", x: 90, y: 35 }],\n        ansiPath: \"M 0,0 H 90 V 70 H 0 Z\",\n        iecLabel: \"?\",\n      };\n    }\n    default: {\n      // Generic box for MUX/DEMUX/DECODER/ENCODER/COUNTER/SHIFT_REG\n      const ins = Math.max(inputCount, 2);\n      const inputPins = combPins(ins, 100, 0).map((p, i) => ({\n        ...p,\n        x: 0,\n        label: `I${i}`,\n      }));\n      return {\n        width: 100,\n        height: 80,\n        inputPins,\n        outputPins: [{ id: \"out\", x: 100, y: 40 }],\n        ansiPath: \"M 0,0 H 100 V 80 H 0 Z\",\n        iecLabel: gateType,\n      };\n    }\n  }\n}\n","import type { LogicGateAST } from \"../../core/types\";\nimport { getGateGeometry, type GateGeometry } from \"./symbols\";\n\nexport interface LogicLayoutNode {\n  id: string;\n  kind: \"input\" | \"gate\" | \"output\";\n  x: number;\n  y: number;\n  layer: number;\n  geometry?: GateGeometry;\n  gateType?: string;\n  /** Original (unrecognised) gate token, set only when `gateType === \"unknown\"`. */\n  rawType?: string;\n  label: string;\n  isActiveLow?: boolean;\n}\n\nexport interface LogicLayoutWire {\n  fromNode: string;\n  fromX: number;\n  fromY: number;\n  toNode: string;\n  toX: number;\n  toY: number;\n  isActiveLow?: boolean;\n  path: string;\n}\n\nexport interface LogicLayoutModule {\n  id: string;\n  label: string;\n  x: number;\n  y: number;\n  width: number;\n  height: number;\n}\n\nexport interface LogicLayoutResult {\n  width: number;\n  height: number;\n  nodes: LogicLayoutNode[];\n  wires: LogicLayoutWire[];\n  modules: LogicLayoutModule[];\n}\n\nconst LAYER_GAP = 80; // extra horizontal gap between layers\nconst ROW_GAP = 40;   // vertical gap between rows in same layer\nconst PORT_SIZE = 40; // input/output port pseudo-box width\nconst PORT_H = 30;\n\nexport function layoutLogic(ast: LogicGateAST): LogicLayoutResult {\n  // Determine layer per signal id using longest-path layering\n  const layerOf = new Map<string, number>();\n  for (const inp of ast.inputs) layerOf.set(inp.id, 0);\n\n  // Build dependency map for gates\n  const pending = new Set(ast.gates.map((g) => g.id));\n  let safety = 0;\n  while (pending.size > 0 && safety++ < 1000) {\n    for (const g of ast.gates) {\n      if (!pending.has(g.id)) continue;\n      let maxDep = -1;\n      let ready = true;\n      for (const inp of g.inputs) {\n        const clean = inp.startsWith(\"~\") ? inp.slice(1) : inp;\n        const l = layerOf.get(clean);\n        if (l === undefined) {\n          ready = false;\n          break;\n        }\n        if (l > maxDep) maxDep = l;\n      }\n      if (ready) {\n        layerOf.set(g.id, maxDep + 1);\n        pending.delete(g.id);\n      }\n    }\n  }\n  if (pending.size > 0) {\n    // cycle or unresolved: force layer 1\n    for (const id of pending) layerOf.set(id, 1);\n  }\n\n  const outputLayer =\n    Math.max(0, ...Array.from(layerOf.values())) + 1;\n  // All outputs get a terminal label node. Use synthetic id to avoid colliding\n  // with a gate that shares the output's name (e.g. `output Y; Y = AND(A,B)`).\n  const outTermId = (o: { id: string }) => `$out$${o.id}`;\n  const portOutputs = ast.outputs.map((o) => ({\n    ...o,\n    termId: outTermId(o),\n    source: o.from,\n  }));\n  for (const o of portOutputs) layerOf.set(o.termId, outputLayer);\n\n  // Group ids by layer\n  const layers = new Map<number, string[]>();\n  const addToLayer = (id: string, layer: number) => {\n    if (!layers.has(layer)) layers.set(layer, []);\n    layers.get(layer)!.push(id);\n  };\n  for (const i of ast.inputs) addToLayer(i.id, 0);\n  for (const g of ast.gates) addToLayer(g.id, layerOf.get(g.id)!);\n  for (const o of portOutputs) addToLayer(o.termId, outputLayer);\n\n  // Compute sizes per node (precompute geometries for gates)\n  const gateGeoms = new Map<string, GateGeometry>();\n  for (const g of ast.gates) {\n    gateGeoms.set(g.id, getGateGeometry(g.gateType, g.inputs.length));\n  }\n\n  // Assign coordinates\n  const nodes: LogicLayoutNode[] = [];\n  const sortedLayers = Array.from(layers.keys()).sort((a, b) => a - b);\n\n  // compute each layer's widest node\n  const layerWidth = new Map<number, number>();\n  for (const [layerIdx, ids] of layers) {\n    let maxW = 60;\n    for (const id of ids) {\n      const g = gateGeoms.get(id);\n      if (g && g.width > maxW) maxW = g.width;\n      if (!g && layerIdx === 0) maxW = Math.max(maxW, PORT_SIZE);\n      if (!g && layerIdx === outputLayer) maxW = Math.max(maxW, PORT_SIZE);\n    }\n    layerWidth.set(layerIdx, maxW);\n  }\n\n  let cursorX = 20;\n  const layerStartMap = new Map<number, number>();\n  for (const layerIdx of sortedLayers) {\n    layerStartMap.set(layerIdx, cursorX);\n    cursorX += (layerWidth.get(layerIdx) ?? 60) + LAYER_GAP;\n  }\n  const totalW = cursorX;\n\n  // Compute vertical placement per layer\n  const heightOf = (id: string): number => {\n    const g = gateGeoms.get(id);\n    if (g) return g.height;\n    return PORT_H;\n  };\n\n  // find max column height\n  let maxColH = 0;\n  for (const ids of layers.values()) {\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    if (total > maxColH) maxColH = total;\n  }\n  const totalH = maxColH + 80;\n\n  const nodeInfo = new Map<string, LogicLayoutNode>();\n  for (const [layerIdx, ids] of layers) {\n    const xStart = layerStartMap.get(layerIdx)!;\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    let y = 40 + (maxColH - total) / 2;\n    for (const id of ids) {\n      const h = heightOf(id);\n      const g = gateGeoms.get(id);\n      let node: LogicLayoutNode;\n      if (layerIdx === 0) {\n        const inp = ast.inputs.find((i) => i.id === id)!;\n        node = {\n          id,\n          kind: \"input\",\n          x: xStart,\n          y,\n          layer: 0,\n          label: inp.label,\n          isActiveLow: inp.isActiveLow,\n        };\n      } else if (layerIdx === outputLayer && !g && id.startsWith(\"$out$\")) {\n        const out = portOutputs.find((o) => o.termId === id)!;\n        node = {\n          id,\n          kind: \"output\",\n          x: xStart,\n          y,\n          layer: outputLayer,\n          label: out.label,\n          isActiveLow: out.isActiveLow,\n        };\n      } else {\n        node = {\n          id,\n          kind: \"gate\",\n          x: xStart,\n          y,\n          layer: layerIdx,\n          geometry: g,\n          gateType: ast.gates.find((gg) => gg.id === id)!.gateType,\n          rawType: ast.gates.find((gg) => gg.id === id)!.rawType,\n          label: id,\n        };\n      }\n      nodes.push(node);\n      nodeInfo.set(id, node);\n      y += h + ROW_GAP;\n    }\n  }\n\n  // Wires\n  const wires: LogicLayoutWire[] = [];\n  const getSourcePoint = (id: string) => {\n    const n = nodeInfo.get(id);\n    if (!n) return null;\n    if (n.kind === \"input\") return { x: n.x + PORT_SIZE, y: n.y + PORT_H / 2 };\n    if (n.kind === \"gate\" && n.geometry) {\n      const out = n.geometry.outputPins[0];\n      return { x: n.x + out.x, y: n.y + out.y };\n    }\n    return null;\n  };\n\n  for (const g of ast.gates) {\n    const target = nodeInfo.get(g.id);\n    if (!target || !target.geometry) continue;\n    g.inputs.forEach((rawInp, idx) => {\n      const isLow = rawInp.startsWith(\"~\");\n      const srcId = isLow ? rawInp.slice(1) : rawInp;\n      const src = getSourcePoint(srcId);\n      if (!src) return;\n      const pin = target.geometry!.inputPins[idx];\n      if (!pin) return;\n      const toX = target.x + pin.x;\n      const toY = target.y + pin.y;\n      const midX = (src.x + toX) / 2;\n      const path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n      wires.push({\n        fromNode: srcId,\n        fromX: src.x,\n        fromY: src.y,\n        toNode: g.id,\n        toX,\n        toY,\n        isActiveLow: isLow,\n        path,\n      });\n    });\n  }\n\n  // Output port wires\n  for (const o of portOutputs) {\n    const src = getSourcePoint(o.source);\n    const target = nodeInfo.get(o.termId);\n    if (!src || !target || target.kind !== \"output\") continue;\n    const toX = target.x;\n    const toY = target.y + PORT_H / 2;\n    let path: string;\n    if (Math.abs(src.y - toY) < 0.5) {\n      path = `M ${src.x},${src.y} L ${toX},${toY}`;\n    } else {\n      const midX = (src.x + toX) / 2;\n      path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n    }\n    wires.push({\n      fromNode: o.source,\n      fromX: src.x,\n      fromY: src.y,\n      toNode: o.termId,\n      toX,\n      toY,\n      path,\n    });\n  }\n\n  // Module bounding boxes (dashed enclosure for sub-circuits)\n  const modules: LogicLayoutModule[] = [];\n  if (ast.modules && ast.modules.length > 0) {\n    const PAD = 14;\n    for (const mod of ast.modules) {\n      const memberIds = new Set(\n        ast.gates.filter((g) => g.moduleId === mod.id).map((g) => g.id)\n      );\n      if (memberIds.size === 0) continue;\n      let minX = Infinity, minY = Infinity, maxX = -Infinity, maxY = -Infinity;\n      for (const n of nodes) {\n        if (!memberIds.has(n.id)) continue;\n        const w = n.geometry?.width ?? 60;\n        const h = n.geometry?.height ?? 60;\n        if (n.x < minX) minX = n.x;\n        if (n.y < minY) minY = n.y;\n        if (n.x + w > maxX) maxX = n.x + w;\n        if (n.y + h > maxY) maxY = n.y + h;\n      }\n      if (!isFinite(minX)) continue;\n      modules.push({\n        id: mod.id,\n        label: mod.label,\n        x: minX - PAD,\n        y: minY - PAD - 4,\n        width: maxX - minX + PAD * 2,\n        height: maxY - minY + PAD * 2 + 4,\n      });\n    }\n  }\n\n  return { width: totalW, height: totalH, nodes, wires, modules };\n}\n","import type { LogicGateAST, LogicGateStyle, RenderConfig } from \"../../core/types\";\nimport { layoutLogic } from \"./layout\";\nimport {\n  svgRoot,\n  defs,\n  group,\n  el,\n  circle,\n  path as pathEl,\n  text,\n  title as titleEl,\n  desc,\n  polygon,\n} from \"../../core/svg\";\nimport { resolveIndustrialTheme } from \"../../core/theme\";\n\nconst PORT_SIZE = 40;\nconst PORT_H = 30;\n\nfunction renderGateBody(\n  n: ReturnType<typeof layoutLogic>[\"nodes\"][number],\n  style: LogicGateStyle\n): string[] {\n  const out: string[] = [];\n  if (!n.geometry) return out;\n  const g = n.geometry;\n\n  if (style === \"iec\") {\n    // Rectangle\n    out.push(\n      el(\"rect\", {\n        x: 0,\n        y: 0,\n        width: g.width,\n        height: g.height,\n        class: \"schematex-logic-gate-body\",\n      })\n    );\n    if (g.iecLabel) {\n      out.push(\n        text(\n          {\n            x: g.width / 2,\n            y: g.height / 2 + 4,\n            class: \"schematex-logic-gate-iec-label\",\n            \"text-anchor\": \"middle\",\n          },\n          g.iecLabel\n        )\n      );\n    }\n  } else {\n    out.push(\n      el(\"path\", { d: g.ansiPath, class: \"schematex-logic-gate-body\" })\n    );\n  }\n\n  // Unrecognised gate: stamp a centred \"?\" so the ANSI box reads as a flagged\n  // placeholder (IEC already centres the \"?\" via iecLabel above).\n  if (n.gateType === \"unknown\" && style !== \"iec\") {\n    out.push(\n      text(\n        {\n          x: g.width / 2,\n          y: g.height / 2 + 6,\n          class: \"schematex-logic-gate-iec-label\",\n          \"text-anchor\": \"middle\",\n        },\n        \"?\"\n      )\n    );\n  }\n\n  // Output bubble\n  if (g.outputBubble) {\n    const op = g.outputPins[0];\n    out.push(\n      circle({\n        cx: op.x - 4,\n        cy: op.y,\n        r: 4,\n        class: \"schematex-logic-bubble\",\n      })\n    );\n  }\n\n  // Clock triangle\n  if (g.clockPin) {\n    const cp = g.inputPins.find((p) => p.id === g.clockPin);\n    if (cp) {\n      out.push(\n        polygon({\n          points: `${cp.x},${cp.y - 5} ${cp.x + 8},${cp.y} ${cp.x},${cp.y + 5}`,\n          class: \"schematex-logic-clock-tri\",\n        })\n      );\n    }\n  }\n\n  // Qn bubble (sequential)\n  for (const op of g.outputPins) {\n    if (op.bubble && op.id !== \"out\") {\n      out.push(\n        circle({\n          cx: op.x + 4,\n          cy: op.y,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n  }\n\n  // Pin labels\n  for (const pin of g.inputPins) {\n    if (pin.label && pin.id !== g.clockPin) {\n      out.push(\n        text(\n          {\n            x: pin.x + 5,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n  for (const pin of g.outputPins) {\n    if (pin.label) {\n      out.push(\n        text(\n          {\n            x: pin.x - 6,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n            \"text-anchor\": \"end\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n\n  // Gate type label (center top, small)\n  if (style === \"ansi\" && g.iecLabel && g.height >= 60) {\n    const labelX = g.width / 2;\n    const labelY = g.height + 14;\n    out.push(\n      text(\n        {\n          x: labelX,\n          y: labelY,\n          class: \"schematex-logic-gate-type\",\n          \"text-anchor\": \"middle\",\n        },\n        n.gateType === \"unknown\" ? n.rawType ?? \"?\" : n.gateType ?? \"\"\n      )\n    );\n  }\n\n  return out;\n}\n\nexport function renderLogic(ast: LogicGateAST, config?: RenderConfig): string {\n  const style: LogicGateStyle = ast.style ?? \"ansi\";\n  const layout = layoutLogic(ast);\n  const { width, height } = layout;\n  const t = resolveIndustrialTheme(config?.theme ?? \"default\");\n\n  const gateSvgs: string[] = [];\n  const portSvgs: string[] = [];\n  const moduleSvgs: string[] = [];\n\n  for (const m of layout.modules) {\n    moduleSvgs.push(\n      group({ \"data-module-id\": m.id }, [\n        el(\"rect\", {\n          x: m.x,\n          y: m.y,\n          width: m.width,\n          height: m.height,\n          rx: 6,\n          class: \"schematex-logic-module\",\n        }),\n        text(\n          {\n            x: m.x + 10,\n            y: m.y + 14,\n            class: \"schematex-logic-module-label\",\n          },\n          m.label\n        ),\n      ])\n    );\n  }\n\n  for (const n of layout.nodes) {\n    if (n.kind === \"gate\") {\n      gateSvgs.push(\n        group(\n          {\n            transform: `translate(${n.x}, ${n.y})`,\n            \"data-gate-id\": n.id,\n            \"data-gate-type\": n.gateType ?? \"\",\n          },\n          renderGateBody(n, style)\n        )\n      );\n    } else if (n.kind === \"input\") {\n      // Label + short stub line; no rectangle.\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"input\" }, [\n          text(\n            {\n              x: 0,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n          el(\"line\", {\n            x1: PORT_SIZE - 12,\n            y1: cy,\n            x2: n.isActiveLow ? PORT_SIZE - 8 : PORT_SIZE,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          n.isActiveLow\n            ? circle({\n                cx: PORT_SIZE - 4,\n                cy,\n                r: 4,\n                class: \"schematex-logic-bubble\",\n              })\n            : \"\",\n        ])\n      );\n    } else if (n.kind === \"output\") {\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"output\" }, [\n          el(\"line\", {\n            x1: 0,\n            y1: cy,\n            x2: 12,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          text(\n            {\n              x: 16,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n        ])\n      );\n    }\n  }\n\n  const wireSvgs = layout.wires.map((w) => {\n    const extras: string[] = [];\n    if (w.isActiveLow) {\n      extras.push(\n        circle({\n          cx: w.toX - 4,\n          cy: w.toY,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n    return [\n      pathEl({\n        d: w.path,\n        class: \"schematex-logic-wire\",\n        \"data-from\": w.fromNode,\n        \"data-to\": w.toNode,\n      }),\n      ...extras,\n    ].join(\"\");\n  });\n\n  const css = `\n.schematex-logic { font-family: system-ui, -apple-system, sans-serif; }\n.schematex-logic-gate-body { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.75; stroke-linejoin: round; }\n.schematex-logic-bubble { fill: ${t.bg}; stroke: ${t.strokeHeavy}; stroke-width: 1.5; }\n.schematex-logic-clock-tri { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.5; stroke-linejoin: round; }\n.schematex-logic-wire { stroke: ${t.strokeHeavy}; stroke-width: 1.5; fill: none; stroke-linecap: square; }\n.schematex-logic-port-label { font: 13px system-ui, sans-serif; fill: ${t.text}; }\n.schematex-logic-pin-label { font: 9px sans-serif; fill: ${t.stroke}; }\n.schematex-logic-gate-type { font: 10px sans-serif; fill: ${t.textMuted}; }\n.schematex-logic-gate-iec-label { font: bold 13px sans-serif; fill: ${t.text}; }\n.schematex-logic-title { font: bold 14px sans-serif; fill: ${t.text}; }\n.schematex-logic-module { fill: none; stroke: ${t.textMuted}; stroke-width: 1.25; stroke-dasharray: 6 4; }\n.schematex-logic-module-label { font: 11px sans-serif; fill: ${t.textMuted}; font-style: italic; }\n[data-gate-type=\"unknown\"] .schematex-logic-gate-body { stroke: ${t.accent}; stroke-dasharray: 5 3; }\n[data-gate-type=\"unknown\"] .schematex-logic-gate-iec-label { fill: ${t.accent}; }\n`.trim();\n\n  const titleSvg = ast.title\n    ? text(\n        {\n          x: width / 2,\n          y: 18,\n          \"text-anchor\": \"middle\",\n          class: \"schematex-logic-title\",\n        },\n        ast.title\n      )\n    : \"\";\n\n  return svgRoot(\n    {\n      class: \"schematex-logic\",\n      viewBox: `0 0 ${width} ${height + (ast.title ? 20 : 0)}`,\n      width,\n      height: height + (ast.title ? 20 : 0),\n      role: \"img\",\n      \"data-diagram-type\": \"logic\",\n    },\n    [\n      titleEl(ast.title ?? \"Logic Gate Diagram\"),\n      desc(\n        `Logic gate diagram with ${ast.gates.length} gates, ${ast.inputs.length} inputs, ${ast.outputs.length} outputs`\n      ),\n      defs([el(\"style\", {}, css)]),\n      group(\n        { transform: `translate(0, ${ast.title ? 20 : 0})` },\n        [\n          group({ class: \"schematex-logic-modules\" }, moduleSvgs),\n          group({ class: \"schematex-logic-wires\" }, wireSvgs),\n          group({ class: \"schematex-logic-gates\" }, gateSvgs),\n          group({ class: \"schematex-logic-ports\" }, portSvgs),\n        ]\n      ),\n      titleSvg,\n    ]\n  );\n}\n","import type { SchematexDiagnostic } from \"../../core/diagnostics\";\nimport type { LogicGateAST } from \"../../core/types\";\nimport { didYouMean } from \"../../core/dsl-suggest\";\nimport { parseLogic } from \"./parser\";\n\n// Canonical gate vocabulary for the did-you-mean suggestion on an unknown gate.\n// Kept in sync with GATE_TYPES in the parser.\nconst KNOWN_GATES = [\n  \"AND\", \"OR\", \"NOT\", \"NAND\", \"NOR\", \"XOR\", \"XNOR\", \"BUF\",\n  \"TRISTATE_BUF\", \"TRISTATE_INV\", \"OPEN_DRAIN\", \"SCHMITT\",\n  \"DFF\", \"JKFF\", \"SRFF\", \"TFF\", \"LATCH_SR\", \"LATCH_D\",\n  \"MUX\", \"DEMUX\", \"DECODER\", \"ENCODER\", \"COUNTER\", \"SHIFT_REG\",\n];\n\nexport function lintLogic(text: string): SchematexDiagnostic[] {\n  let ast: LogicGateAST;\n  try {\n    ast = parseLogic(text);\n  } catch {\n    // Parse failures are reported by the normal error path; lint stays silent.\n    return [];\n  }\n  return lintLogicAst(ast);\n}\n\nexport function lintLogicAst(ast: LogicGateAST): SchematexDiagnostic[] {\n  const out: SchematexDiagnostic[] = [];\n  // Unrecognised gate types are kept (drawn as a flagged placeholder) but\n  // warned about so the partial render is analyzable and the engineer gets a\n  // did-you-mean nudge. The engine never silently substitutes a real gate.\n  for (const g of ast.gates) {\n    if (g.gateType !== \"unknown\") continue;\n    const raw = g.rawType ?? \"\";\n    out.push({\n      severity: \"warning\",\n      code: \"LOGIC_UNKNOWN_GATE\",\n      message: `gate \"${g.id}\" has unrecognised type \"${raw}\"; drawn as a flagged placeholder`,\n      hint: `\"${raw}\" is not a known logic gate.${didYouMean(raw.toUpperCase(), KNOWN_GATES)} Valid gates include AND, OR, NOT, NAND, NOR, XOR, DFF, MUX. See docs/reference.`,\n      fatal: false,\n    });\n  }\n  return out;\n}\n","import type { DiagramPlugin } from \"../../core/types\";\nimport { parseLogic } from \"./parser\";\nimport { renderLogic } from \"./renderer\";\nimport { lintLogic } from \"./lint\";\n\nexport const logic: DiagramPlugin = {\n  type: \"logic\",\n  detect(text: string): boolean {\n    const first = text.trim().split(\"\\n\")[0]?.trim().toLowerCase() ?? \"\";\n    return first.startsWith(\"logic\");\n  },\n  parse: parseLogic,\n  lint: lintLogic,\n\n  render(text: string, config): string {\n    const ast = parseLogic(text);\n    return renderLogic(ast, config);\n  },\n};\n\nexport { parseLogic } from \"./parser\";\nexport { renderLogic } from \"./renderer\";\nexport { layoutLogic } from \"./layout\";\nexport { lintLogic, lintLogicAst } from \"./lint\";\n"]}

package/dist/{chunk-ZZHQBAC3.js → chunk-3HZW6K5I.js}

@@ -1,4 +1,4 @@
-import { parseResult, renderResult } from './chunk-MI77LY6A.js';
+import { parseResult, renderResult } from './chunk-FOPOOV2P.js';
 
 // src/ai/registry.ts
 var DIAGRAM_REGISTRY = [
@@ -282,6 +282,15 @@ var DIAGRAM_REGISTRY = [
     standard: "NUREG-0492 Fault Tree Handbook + IEC 61025:2006 + NASA FT Handbook 2002; MOCUS cut sets (Fussell-Vesely 1972); see 37-FAULT-TREE-STANDARD.md",
     syntaxKey: "faulttree"
   },
+  {
+    type: "bowtie",
+    name: "Bowtie risk diagram",
+    tagline: "Barrier-based risk management \u2014 one hazard's top event (the knot) with threats fanning in through preventative barriers on the left and consequences fanning out through mitigative barriers on the right, the whole shaped like a bow tie.",
+    useWhen: 'Use for process-safety / barrier risk analysis (oil & gas, aviation SMS, chemical, rail): one hazard, one top event, the threats that could cause it and the consequences if it happens, with the controls (barriers) in between. Indentation-structured DSL mirrors the CCPS 7-step build: `hazard "\u2026"`, `topevent "\u2026"`, then each `threat "\u2026"` with indented `prevent "\u2026"` barrier chain, each `consequence "\u2026"` with indented `mitigate "\u2026"` chain; `escalation "\u2026"` nests under a barrier it degrades, `barrier "\u2026"` nests under an escalation. Correct-by-construction: the engine *rejects* a threat/consequence with no barrier and an escalation not attached to a barrier (CCPS/EI barrier rule set). Qualitative \u2014 no probability rollup (that is `faulttree`\'s job; a bowtie\'s left wing read backwards IS a fault tree). Distinct from `fishbone` (one-sided causes, no barriers) and `faulttree` (Boolean gates + cut sets, left wing only).',
+    cluster: "risk-reliability",
+    standard: "CCPS / Energy Institute 2018 (Bow Ties in Risk Management) + IEC 31010:2019 \xA7B.4.6 + ICAO Doc 9859; Swiss-cheese lineage (Reason 1990); see 38-BOWTIE-STANDARD.md",
+    syntaxKey: "bowtie"
+  },
   // ── Generic process / flow ───────────────────────────────────
   {
     type: "flowchart",
@@ -377,7 +386,9 @@ var DIAGRAM_SINCE = {
   // 0.6.4
   umlclass: "0.6.4",
   // 0.6.5
-  faulttree: "0.6.5"
+  faulttree: "0.6.5",
+  // 0.6.6
+  bowtie: "0.6.6"
 };
 function getDiagramSince(type) {
   const resolved = resolveDiagramType(type);
@@ -442,6 +453,82 @@ var EXAMPLES = [
     "dsl": 'blockdiagram "PID control loop"\nC = block("PID C(s)") [role: controller]\nG = block("Plant G(s)") [role: plant]\nerr = sum(+r, -y)\nr = signal("r (setpoint)")\ny = signal("y (output)")\nin -> r\nr -> err\nerr -> C\nC -> G\nG -> y\nG -> err',
     "notes": '## Scenario\n\nThe standard closed-loop PID block diagram appears in every control systems textbook (Ogata, Franklin, \xC5str\xF6m) and every control system design spec sheet. Schematex renders it from a signal-flow description \u2014 not a generic flowchart \u2014 using proper summing junction symbols and automatic feedback routing.\n\n## Annotation key\n\n- `block("label") [role: ...]` \u2014 transfer function block; `role: controller` and `role: plant` affect visual styling\n- `sum(+r, -y)` \u2014 summing junction: adds the `+r` (reference) signal and subtracts the `-y` (output feedback)\n- `signal("label")` \u2014 named signal node\n- `G -> err` \u2014 the feedback path: plant output `y` routes back to the summing junction\n\n## How to read\n\nThe setpoint `r` enters the summing junction `err`, which subtracts the plant output `y` to compute the error signal. The PID controller `C(s)` processes the error and drives the plant `G(s)`. The plant output `y` is both the system output and the feedback signal. The loop is closed when `G -> err` feeds `y` back to the summing junction.'
   },
+  {
+    "slug": "bowtie-hot-work-fire",
+    "diagram": "bowtie",
+    "title": "Hot work \u2014 ignition of flammable atmosphere",
+    "description": "A bowtie with escalation factors on both wings \u2014 a preventative and a mitigative barrier are each degraded by a named condition with its own escalation-factor barrier, exercising the full element vocabulary.",
+    "standard": "CCPS / Energy Institute 2018",
+    "tags": [
+      "bowtie",
+      "risk",
+      "escalation-factor",
+      "hot-work",
+      "fire",
+      "barrier"
+    ],
+    "complexity": 3,
+    "featured": false,
+    "dsl": 'bowtie "Hot work \u2014 fire bowtie"\nhazard "Hot work near flammable materials"\ntopevent "Ignition of flammable atmosphere"\nthreat "Sparks / hot slag"\n  prevent "Hot-work permit"\n  prevent "Fire watch"\n    escalation "Fire watch leaves post early"\n      barrier "Post-work monitoring period (60 min)"\nthreat "Static discharge"\n  prevent "Bonding + grounding"\n  prevent "Antistatic PPE"\nconsequence "Flash fire"\n  mitigate "Fixed fire suppression"\n    escalation "Suppression isolated for maintenance"\n      barrier "Impairment register + MoC"\nconsequence "Asset loss"\n  mitigate "Fire-rated separation"\n  mitigate "Business-continuity plan"',
+    "notes": '## What this shows\n\nThe complete element vocabulary, with **escalation factors on both wings** \u2014 because a mitigative barrier can be degraded just as a preventative one can. On the left, the "Fire watch" barrier is defeated if the watch leaves early, controlled by a mandatory post-work monitoring period. On the right, the "Fixed fire suppression" barrier is defeated when isolated for maintenance, controlled by an impairment register and management-of-change.\n\nThe left wing is taller than the right (its escalation drops deeper), so it sets the diagram height while the right wing stays centred about the knot. Each escalation hangs into the whitespace between bands on a muted *degrades* connector, never colliding with the next line.'
+  },
+  {
+    "slug": "bowtie-lpg-loss-of-containment",
+    "diagram": "bowtie",
+    "title": "LPG storage \u2014 loss of containment",
+    "description": "The canonical process-safety bowtie \u2014 three threats fan in through preventative barrier chains, three consequences fan out through mitigative chains, around the central loss-of-containment top event.",
+    "standard": "CCPS / Energy Institute 2018",
+    "tags": [
+      "bowtie",
+      "risk",
+      "process-safety",
+      "barrier",
+      "hazard",
+      "loss-of-containment"
+    ],
+    "complexity": 3,
+    "featured": true,
+    "dsl": 'bowtie "LPG storage \u2014 loss of containment"\nhazard "LPG stored under pressure"\ntopevent "Loss of containment"\nthreat "Corrosion of vessel wall"\n  prevent "Corrosion-resistant coating"\n  prevent "UT thickness inspection"\nthreat "Overpressure during filling"\n  prevent "High-pressure trip (SIL 2)"\n  prevent "Pressure relief valve"\nthreat "Mechanical impact (vehicle)"\n  prevent "Bollards / vehicle barriers"\n  prevent "Site speed limit + banksman"\nconsequence "Jet fire"\n  mitigate "Gas detection + ESD"\n  mitigate "Deluge / water spray"\nconsequence "Vapour cloud explosion"\n  mitigate "Ignition-source control (ATEX)"\n  mitigate "Blast-resistant control room"\nconsequence "Toxic / asphyxiation exposure"\n  mitigate "Personal gas monitors"\n  mitigate "Emergency evacuation plan"',
+    "notes": '## What this shows\n\nThe integrating picture of barrier-based risk management for one major-accident scenario. The **hazard** ("LPG stored under pressure") sits above the central **top event** \u2014 the moment control is lost. To the **left**, three credible **threats** each fan in through a chain of **preventative barriers** (grey, on the line) that stop them reaching the knot. To the **right**, three **consequences** each fan out through a chain of **mitigative barriers** that limit the damage if the top event occurs.\n\nThis is the shape a process-safety reviewer expects on an A3: defence-in-depth depth on both wings, the knot in the middle, the hazard above. **Correct by construction** \u2014 the engine would reject any threat or consequence drawn with no barrier (a Swiss-cheese cartoon), so every line you see genuinely passes through a control.'
+  },
+  {
+    "slug": "bowtie-runway-excursion",
+    "diagram": "bowtie",
+    "title": "Runway excursion (aviation SMS)",
+    "description": "A non-process-industry bowtie \u2014 the same threat / barrier / consequence grammar applied to an aviation safety-management scenario, showing the vocabulary travels across domains.",
+    "standard": "ICAO Doc 9859 + CCPS / EI 2018",
+    "tags": [
+      "bowtie",
+      "risk",
+      "aviation",
+      "SMS",
+      "ICAO",
+      "barrier"
+    ],
+    "complexity": 3,
+    "featured": false,
+    "dsl": 'bowtie "Runway excursion"\nhazard "Aircraft landing in adverse conditions"\ntopevent "Runway excursion on landing"\nthreat "Unstable approach"\n  prevent "Stabilised-approach gate (go-around policy)"\n  prevent "Approach monitoring + callouts"\nthreat "Contaminated runway"\n  prevent "Runway condition reporting (RCR)"\n  prevent "Landing performance assessment"\nthreat "Excessive landing speed"\n  prevent "Speed / energy management SOP"\n  prevent "Autobrake selection"\nconsequence "Hull damage"\n  mitigate "Runway end safety area (RESA)"\n  mitigate "Arrestor bed (EMAS)"\nconsequence "Injuries / fatalities"\n  mitigate "Cabin-crew brace + evacuation"\n  mitigate "Airport emergency response"',
+    "notes": "## What this shows\n\nThe bowtie is mandated well beyond process industries \u2014 ICAO's Safety Management Manual (Doc 9859) makes it a primary hazard-analysis tool for airlines. The grammar is identical: a **hazard** (landing in adverse conditions), a **top event** (the runway excursion), **threats** that could cause it through preventative barrier chains, and **consequences** limited by mitigative chains.\n\nIt reads the same to a non-specialist as a chemical-plant bowtie, which is exactly the point: one A3 puts the entire defence-in-depth story for a single scenario in front of a board or a regulator, regardless of industry."
+  },
+  {
+    "slug": "bowtie-working-at-height",
+    "diagram": "bowtie",
+    "title": "Working at height \u2014 fall from height",
+    "description": "A defence-in-depth bowtie with an escalation factor \u2014 a preventative barrier is degraded by a named condition, which is itself controlled by an escalation-factor barrier dropping below the line.",
+    "standard": "CCPS / Energy Institute 2018",
+    "tags": [
+      "bowtie",
+      "risk",
+      "escalation-factor",
+      "defence-in-depth",
+      "construction",
+      "safety"
+    ],
+    "complexity": 2,
+    "featured": true,
+    "dsl": 'bowtie "Working at height"\nhazard "Working at height"\ntopevent "Person falls from height"\nthreat "Guardrail removed for access"\n  prevent "Permit-to-work system"\n  prevent "Temporary edge protection"\n    escalation "Edge protection not inspected"\n      barrier "Pre-use inspection regime"\n  prevent "Spotter / banksman"\nthreat "Fragile roof surface"\n  prevent "Crawling boards + signage"\n  prevent "Roof-access risk assessment"\nconsequence "Fatality"\n  mitigate "Fall-arrest harness + lanyard"\n  mitigate "Rescue plan + first aid"\nconsequence "Serious injury"\n  mitigate "Safety netting below"\n  mitigate "On-site medic + evacuation"',
+    "notes": '## What this shows\n\nTwo threats, two consequences, multi-barrier chains \u2014 and an **escalation factor**, the element that makes a bowtie an honest defence-in-depth model rather than a wish list. The "Temporary edge protection" barrier is degraded by a specific named condition ("Edge protection not inspected", amber), which drops vertically below the barrier on a muted *degrades* connector. That escalation factor is itself controlled by an **escalation-factor barrier** ("Pre-use inspection regime") one level deeper.\n\nReading order along each line is declaration order: the first barrier is the **outermost** (first line of defence, nearest the threat); the last is the **innermost** (nearest the knot). The escalation hangs into the whitespace below without disturbing the symmetry of the two threat lines.'
+  },
   {
     "slug": "bpmn-incident-response",
     "diagram": "bpmn",
@@ -2898,6 +2985,10 @@ var SYNTAX = {
   "faulttree": {
     "title": "Fault Tree Analysis",
     "content": '## 1. Your first diagram\n\nEvery document starts with the `faulttree` keyword (alias `fta`), an optional title, then a flat list of declarations wired by id:\n\n```\nfaulttree "Both pumps fail"\n  analysis: cutsets, probability\n  top T "Both redundant pumps fail" = AND(PA, PB)\n  basic PA "Pump A fails" p: 0.01\n  basic PB "Pump B fails" p: 0.01\n```\n\n`top` declares the single root event and the gate that produces it; `basic` declares a leaf component failure with a probability. The engine computes the minimal cut set `{PA, PB}` and P(top) = 1.0e-4. The DSL is **flat declaration + reference** (not nested by indentation) \u2014 a fault tree is a DAG, so a shared event is just referenced by id from several gates.\n\nHeader directives:\n\n- `analysis: cutsets, probability` \u2014 what to compute (also `pathsets`, `none`).\n- `prob: rare | mcub | exact` \u2014 the probability method (default `rare`, a conservative upper bound).\n- `layout: tb | bt` \u2014 top-down (default) or bottom-up.\n\n---\n\n## 2. Events\n\n```\ntop  T   "System fails"        = OR(A, B)\ngate G1  "Sub-fault"           = AND(A, B)\nbasic A  "Component A fails"   p: 0.01\nundeveloped EXT "External fire (not modelled)"\nhouse HX "Power on"            state: 1\n```\n\n- **`top`** \u2014 the one undesired event being analysed (rectangle, emphasised border). Exactly one is required.\n- **`gate`** \u2014 an intermediate event that is itself a gate output (rectangle).\n- **`basic`** \u2014 a primary component failure, the leaf that carries `p:` (circle).\n- **`undeveloped`** \u2014 an event not developed further (diamond); may carry `p:`.\n- **`house`** \u2014 a normally-expected event forced `state: 0` or `state: 1` (house glyph) \u2014 switches branches of the tree on/off.\n\nProbabilities accept decimals or scientific notation (`p: 0.004` or `p: 1e-6`); `p:` and `prob:` are interchangeable. An event with no probability is treated symbolically (cut sets still computed; P(top) reported as n/a).\n\n---\n\n## 3. Gates\n\n```\ntop  T1 = AND(A, B, C)            # all inputs occur\ntop  T2 = OR(A, B)                # at least one input occurs\ntop  T3 = XOR(A, B)               # exactly one (treated as OR for cut sets)\ntop  T4 = VOTING(2/3; A, B, C)    # at least k of n\ngate G1 = INHIBIT(A) if COND      # A occurs AND the condition holds\ngate G2 = PAND(A, B) order: A, B  # A then B (order rendered, AND for cut sets)\n```\n\nGates are drawn **output-up, inputs-down** (the mirror of a `logic` gate): AND is a flat-bottomed dome, OR/XOR/VOTING a shield, INHIBIT a hexagon. The conditioning event of an `INHIBIT`/`PAND` renders as an ellipse to the side. A gate may reference another gate or any event \u2014 and the same basic event may feed several gates (a repeated event).\n\n---\n\n## 4. Computed cut sets & probability\n\nThis is the differentiator. With `analysis: cutsets`, the engine runs **MOCUS**: AND gates grow the order of a cut set, OR gates multiply the number of cut sets, then idempotence (`A\u2227A=A`) and absorption (`X \u2286 Y \u21D2 drop Y`) minimise the result.\n\n- Each **minimal cut set** is boxed in red; an **order-1 cut set is a single point of failure** (strongest red, `data-spof`).\n- A **repeated event** (one basic event under several gates) is handled by absorption \u2014 the case a naive expander gets wrong.\n- **P(top)** is computed from per-event probabilities: `rare` (\u03A3 cut-set probs, default), `mcub` (1 \u2212 \u220F(1\u2212P)), or `exact` (inclusion-exclusion, which correctly de-duplicates a shared event). The method is shown next to the top event and noted in `<desc>`.\n- A `house state: 0` can make the top event unsatisfiable \u2014 reported as "no cut sets."\n\n---\n\n## 5. Repeated events\n\n```\nfaulttree "Safety function fails"\n  analysis: cutsets, probability\n  prob: exact\n  top T "Safety function fails" = OR(C1, C2)\n  gate C1 "Channel 1" = AND(S1, L1)\n  gate C2 "Channel 2" = AND(S2, L1)\n  basic S1 "Sensor 1 fails" p: 0.05\n  basic S2 "Sensor 2 fails" p: 0.05\n  basic L1 "Shared logic solver fails" p: 0.05\n```\n\n`L1` feeds both channels \u2014 it is drawn once per reference with a shared-event mark, but the cut-set engine treats every instance as one Boolean variable. Cut sets are `{S1, L1}` and `{S2, L1}`; `prob: exact` subtracts the overlap (L1 counted once over the union), giving 0.004875 rather than the rare-event 0.005.\n\n---\n\n## 6. Transfers\n\n```\ngate OVP "Sustained over-pressure" = INHIBIT(PUMP) if HEATER\ntransfer OVP -> "OVP-detail"\n```\n\nA `transfer ID -> "name"` draws the transfer-out triangle below an event whose development lives elsewhere; a matching `transfer "name" = gate_expr` defines that named subtree and is spliced in for cut-set computation. v0.1 resolves transfers in-document.\n\n---\n\n## 7. Validation\n\nThe parser fails fast with readable errors so the cut-set math is meaningful:\n\n- exactly one `top` is required (zero or several is an error);\n- a gate referencing an undeclared id reports the id by name;\n- cycles are rejected (a fault tree is a DAG);\n- a probability outside `[0, 1]`, a `VOTING k/n` with `k > n` or `n \u2260 input count`, or an `if` condition on a non-INHIBIT/PAND gate are all reported in plain English.\n\n---\n\n## 8. Theming\n\n`default` uses the house palette \u2014 soft slate-blue event boxes, **green gates** ("logic proceeds"), **red cut-set boxes** (the computed risk), blue probability numerals, a yellow house. `monochrome` reproduces the NUREG-0492 black-and-white textbook look, where the dome/shield shape (not colour) carries the gate type. All strokes/fills come from `ReliabilityTokens`; every element carries `data-*` (`data-cutset`, `data-spof`, `data-prob`, `data-gate`) so the computed analysis is inspectable downstream.'
+  },
+  "bowtie": {
+    "title": "Bowtie Risk Diagram",
+    "content": '## 1. Your first diagram\n\nEvery document starts with the `bowtie` keyword, an optional title, then the hazard, the top event, and the two wings:\n\n```\nbowtie\ntopevent "Loss of containment"\nthreat "Corrosion"\n  prevent "Inspection programme"\nconsequence "Release to atmosphere"\n  mitigate "Gas detection + ESD"\n```\n\n`topevent` declares the single knot at the centre (mandatory, exactly one). Each `threat` starts a left-wing line; each `consequence` ends a right-wing line. A barrier under a `threat` is **preventative** (`prevent`); under a `consequence` it is **mitigative** (`mitigate`). The diagram is laid out symmetrically about the knot \u2014 threats fan in from the left, consequences fan out to the right.\n\nThe DSL is **indentation-structured** and mirrors the CCPS 7-step build methodology: identify the hazard \u2192 the top event \u2192 the threats \u2192 the consequences \u2192 the preventative barriers \u2192 the mitigative barriers \u2192 the escalation factors.\n\nHeader directives (any order):\n\n- `layout: symmetric | compact` \u2014 band model (default `symmetric`).\n- `legend: on | off | bottom | top` \u2014 the auto-derived colour legend (default on).\n\n---\n\n## 2. Hazard and top event\n\n```\nhazard "Working at height"\ntopevent "Person falls from height"\n```\n\n- **`hazard`** \u2014 the operation or material with the potential to cause harm: the *context* the bowtie is about (e.g. "Working at height", "Hydrocarbon under pressure"). Optional; renders as a header box above the knot with a tie-line down to it. At most one.\n- **`topevent`** \u2014 the moment control of the hazard is **lost** (e.g. "Loss of containment", "Person falls from height"). The knot of the bowtie, drawn as a green circle. **Mandatory, exactly one.**\n\nA hazard is a *thing/activity*, not a failure; the top event is the precise moment of *loss of control* \u2014 not a cause, and not yet a consequence.\n\n---\n\n## 3. Threats and consequences\n\n```\nthreat "Guardrail removed for access"\n  prevent "Permit-to-work system"\n\nconsequence "Fatality"\n  mitigate "Fall-arrest harness + lanyard"\n```\n\n- A **threat** is a credible cause that, *on its own*, could trigger the top event. Each threat is the start of one left-wing line, drawn as an orange box on the left edge.\n- A **consequence** is a credible outcome *of the top event* (not of the threat), drawn as a red box on the right edge.\n\nThreats and consequences may be declared in any interleaved order \u2014 the parser groups all left-wing blocks and all right-wing blocks regardless of sequence. A bowtie needs **at least one of each**: a one-wing diagram is a fault tree (see `faulttree`) or an event tree, not a bowtie.\n\n---\n\n## 4. Barriers (the controls in between)\n\n```\nthreat "Guardrail removed for access"\n  prevent "Permit-to-work system"\n  prevent "Temporary edge protection"\n  prevent "Spotter / banksman"\n```\n\nA **barrier** is a control that interrupts the threat \u2192 top-event path (preventative) or reduces the consequence after the top event (mitigative). Each is a grey box *on the line*. Chains are free length (1..n) \u2014 the wing simply extends.\n\n**Barrier order is declaration order**: the first declared is the **outermost** (closest to the threat/consequence, the first line of defence); the last declared is the **innermost** (closest to the knot). This matches the left-to-right reading of a real bowtie. Each barrier carries `data-order` (0 = outermost) and `data-side` (`prevent` / `mitigate`) for downstream interactivity.\n\nWhen chains differ in length, barriers are **centre-anchored**: the innermost barriers align in a neat column near the knot, and the threat/consequence boxes are ragged by chain depth \u2014 reading as defence-in-depth.\n\n---\n\n## 5. Escalation factors\n\n```\nthreat "Corrosion"\n  prevent "UT thickness inspection"\n    escalation "Inspection interval too long"\n      barrier "Risk-based inspection scheme"\n```\n\nAn **escalation factor** (or degradation factor) is a condition that *degrades a specific barrier\'s effectiveness* \u2014 e.g. "Edge protection not inspected", "Operator fatigue". It attaches to **one** barrier (not to the line) and drops vertically below it as an amber box, joined by a muted "degrades" connector.\n\nAn **escalation-factor barrier** is a control placed on the escalation factor itself \u2014 it protects the barrier from being degraded (e.g. a pre-use inspection regime). It nests one level deeper, under the escalation factor, and renders as a grey box below it.\n\nIndentation binds the nesting: `prevent`/`mitigate` at 2 spaces, `escalation` at 4, `barrier` at 6.\n\n---\n\n## 6. Correct by construction (the barrier rule set)\n\nBefore it draws a single shape, the engine validates the structural half of the CCPS/EI barrier rule set and **refuses to render** on failure \u2014 exactly as `prisma` refuses missing counts:\n\n- **Exactly one top event** \u2014 zero or several is an error.\n- **Every threat has \u2265 1 preventative barrier** \u2014 a bare threat is a Swiss-cheese cartoon, not a bowtie.\n- **Every consequence has \u2265 1 mitigative barrier** \u2014 the mirror rule.\n- **Every escalation factor is attached to a barrier** \u2014 it cannot float on a line or on the top event.\n- **At least one threat and one consequence** \u2014 a one-wing diagram is an FTA or an ETA.\n\nMessages name the offending element and the rule in plain English, e.g. *"Threat \'Corrosion\' has no preventative barrier \u2014 every threat must reach the top event through at least one barrier (CCPS/EI barrier rule). Add a `prevent` line under it."* This is what separates a real bowtie from a doodle. The engine does **not** judge whether a barrier is truly *effective* or *independent* \u2014 that is the analyst\'s qualitative judgement.\n\n---\n\n## 7. Bowtie vs fault tree\n\nA fully-developed bowtie *is* a fault tree glued to an event tree at the top event: the left wing read backwards is the fault tree whose top event is the bowtie\'s knot, and the right wing is the event tree that propagates it into consequences. Schematex keeps them as two engines because their use differs:\n\n- **`bowtie`** is qualitative and symmetric \u2014 the barrier inventory and the at-a-glance defence-in-depth story; no probability arithmetic.\n- **`faulttree`** is quantitative and Boolean \u2014 AND/OR gates, basic-event probabilities, minimal cut sets, a probability rollup.\n\nWhere you want the gate-level detail behind a single threat, draw a separate `faulttree`.\n\n---\n\n## 8. Theming\n\n`default` uses the recognised BowTieXP / bowtiemaster palette \u2014 **orange threats** (left), **grey barriers** on the line, a **green top-event disc** (centre knot), **red consequences** (right), **amber escalation factors** dropping below \u2014 mapped onto Schematex\'s semantic slots so it stays coherent with `prisma` / `pert` / `petri`. `monochrome` reproduces the regulator-print black-and-white look, where element distinction rides on shape/border + position (escalation factors get a dashed border, the knot a doubled ring) rather than colour. `dark` follows Catppuccin Mocha. All strokes/fills come from `BowtieTokens`; every element carries `data-*` (`data-role`, `data-side`, `data-line`, `data-order`, `data-barrier`) so the structure is inspectable downstream.'
   }
 };
 
@@ -3428,6 +3519,41 @@ var PROFILES = {
       "'VOTING k/n: n must equal the number of inputs' \u2014 make n match the listed inputs.",
       "If P(top) shows 'n/a', a basic event in a cut set is missing its `p:`."
     ]
+  },
+  bowtie: {
+    type: "bowtie",
+    header: 'bowtie "Title"',
+    mode: "indentation-structured: hazard + topevent, then threat/consequence blocks with indented barrier chains",
+    forms: [
+      'hazard "Working at height"',
+      'topevent "Person falls from height"',
+      'threat "Guardrail removed for access"',
+      '  prevent "Permit-to-work system"',
+      '  prevent "Temporary edge protection"',
+      '    escalation "Edge protection not inspected"',
+      '      barrier "Pre-use inspection regime"',
+      'consequence "Fatality"',
+      '  mitigate "Fall-arrest harness"'
+    ],
+    prefer: [
+      "Single-word keyword is `bowtie`. Declare exactly one `topevent` (the knot) and an optional `hazard` header.",
+      "Each `threat` needs \u2265 1 indented `prevent` barrier; each `consequence` needs \u2265 1 indented `mitigate` barrier (the engine rejects a bare threat/consequence).",
+      "Barrier order = declaration order (first = outermost, nearest the threat/consequence; last = innermost, nearest the knot).",
+      "`escalation` nests (4 spaces) under the `prevent`/`mitigate` barrier it degrades; an escalation-factor `barrier` nests (6 spaces) under the escalation.",
+      "Bowtie is qualitative \u2014 no probabilities. For Boolean gates + cut sets behind one threat, use a separate `faulttree`."
+    ],
+    avoid: [
+      "Don't put a `prevent` before any `threat`, or a `mitigate` before any `consequence` \u2014 they bind to the most recent one.",
+      "Don't leave a threat or consequence with no barrier \u2014 that is a Swiss-cheese cartoon, not a bowtie (it is rejected).",
+      "Don't float an `escalation` on its own \u2014 it must follow a barrier line.",
+      "Don't declare more than one `topevent` or more than one `hazard`."
+    ],
+    repair: [
+      "'has no preventative barrier' / 'no mitigative barrier' \u2014 add a `prevent`/`mitigate` line under the threat/consequence.",
+      "'not attached to a barrier' \u2014 move the `escalation` so it follows a `prevent`/`mitigate` line.",
+      "'needs at least one threat/consequence' \u2014 a one-wing diagram is a fault tree or event tree; add the missing wing.",
+      "'exactly one top event' \u2014 keep a single `topevent` line."
+    ]
   }
 };
 function getGenerationProfile(type) {
@@ -3572,5 +3698,5 @@ function repairHint(type) {
 }
 
 export { DIAGRAM_REGISTRY, DIAGRAM_SINCE, getAllDiagramTypes, getDiagramMeta, getDiagramSince, getExamples, getSyntax, listDiagrams, renderDsl, resolveDiagramType, validateDsl };
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