schematex 0.6.1 → 0.6.5

package/dist/chunk-R66QG3XT.cjs.map

@@ -1 +0,0 @@
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type {\n  LogicGateAST,\n  LogicGateInput,\n  LogicGateOutput,\n  LogicGateNode,\n  LogicGateType,\n  LogicGateStyle,\n  LogicGateModule,\n} from \"../../core/types\";\nimport { matchQuotedTitle } from \"../../core/quotes\";\n\nexport class LogicParseError extends Error {\n  constructor(message: string) {\n    super(message);\n    this.name = \"LogicParseError\";\n  }\n}\n\nconst GATE_TYPES = new Set<string>([\n  \"AND\", \"OR\", \"NOT\", \"NAND\", \"NOR\", \"XOR\", \"XNOR\", \"BUF\",\n  \"TRISTATE_BUF\", \"TRISTATE_INV\", \"OPEN_DRAIN\", \"SCHMITT\",\n  \"DFF\", \"JKFF\", \"SRFF\", \"TFF\", \"LATCH_SR\", \"LATCH_D\",\n  \"MUX\", \"DEMUX\", \"DECODER\", \"ENCODER\", \"COUNTER\", \"SHIFT_REG\",\n]);\n\nfunction splitIds(s: string): string[] {\n  return s\n    .split(\",\")\n    .map((x) => x.trim())\n    .filter(Boolean);\n}\n\nfunction parseInputList(s: string): string[] {\n  // Supports named (D=A) or positional. Returns raw tokens (keep ~ prefix for active-low).\n  return s\n    .split(\",\")\n    .map((x) => x.trim())\n    .filter(Boolean)\n    .map((tok) => {\n      const eq = tok.indexOf(\"=\");\n      return eq >= 0 ? tok.slice(eq + 1).trim() : tok;\n    });\n}\n\nexport function parseLogic(text: string): LogicGateAST {\n  const lines = text.split(\"\\n\").map((l) => l.replace(/\\r$/, \"\").trim());\n  let title: string | undefined;\n  let style: LogicGateStyle | undefined;\n  const inputs: LogicGateInput[] = [];\n  const outputs: LogicGateOutput[] = [];\n  const gates: LogicGateNode[] = [];\n  const modules: LogicGateModule[] = [];\n  const moduleStack: string[] = [];\n  let moduleCounter = 0;\n  const explicitOutputFrom = new Map<string, string>();\n\n  for (const rawLine of lines) {\n    // Strip line comments\n    const line = rawLine.replace(/#.*$/, \"\").replace(/--.*$/, \"\").trim();\n    if (!line) continue;\n\n    // module \"Label\" {   or  module Label {\n    const modOpen = line.match(/^module\\s+(?:\"([^\"]+)\"|([a-zA-Z_][\\w]*))\\s*\\{$/);\n    if (modOpen) {\n      const label = modOpen[1] ?? modOpen[2];\n      const id = `mod_${moduleCounter++}`;\n      modules.push({ id, label });\n      moduleStack.push(id);\n      continue;\n    }\n\n    // close module\n    if (line === \"}\") {\n      if (moduleStack.length === 0) {\n        throw new LogicParseError(\"Unmatched `}` — no open module\");\n      }\n      moduleStack.pop();\n      continue;\n    }\n\n    // Header\n    if (/^logic\\b/i.test(line)) {\n      const t = matchQuotedTitle(line);\n      if (t !== undefined) title = t;\n      const s = line.match(/style\\s*:\\s*(ansi|iec)/i);\n      if (s) style = s[1].toLowerCase() as LogicGateStyle;\n      continue;\n    }\n\n    // input A, B, C\n    const inputMatch = line.match(/^input\\s+(.+)$/i);\n    if (inputMatch) {\n      for (const id of splitIds(inputMatch[1])) {\n        const isLow = id.startsWith(\"~\");\n        const clean = isLow ? id.slice(1) : id;\n        inputs.push({ id: clean, label: clean, isActiveLow: isLow || undefined });\n      }\n      continue;\n    }\n\n    // output X, Y\n    const outputMatch = line.match(/^output\\s+(.+)$/i);\n    if (outputMatch) {\n      for (const id of splitIds(outputMatch[1])) {\n        outputs.push({ id, label: id, from: id });\n      }\n      continue;\n    }\n\n    // OUTPUT <- GATE  (map output to gate)\n    const assignMatch = line.match(/^([a-zA-Z_][\\w]*)\\s*<-\\s*([a-zA-Z_][\\w]*)$/);\n    if (assignMatch) {\n      explicitOutputFrom.set(assignMatch[1], assignMatch[2]);\n      continue;\n    }\n\n    // Gate: ID = GATE(a, b, ...)\n    const gateMatch = line.match(/^([a-zA-Z_][\\w]*)\\s*=\\s*([A-Za-z_][\\w]*)\\s*\\(([^)]*)\\)$/);\n    if (gateMatch) {\n      const id = gateMatch[1];\n      const rawType = gateMatch[2].toUpperCase();\n      if (!GATE_TYPES.has(rawType)) {\n        throw new LogicParseError(`Unknown gate type: ${rawType}`);\n      }\n      const gInputs = parseInputList(gateMatch[3]);\n      const moduleId = moduleStack[moduleStack.length - 1];\n      gates.push({ id, gateType: rawType as LogicGateType, inputs: gInputs, moduleId });\n      continue;\n    }\n  }\n\n  if (moduleStack.length > 0) {\n    throw new LogicParseError(`Unclosed module (${moduleStack.length} open)`);\n  }\n\n  // Wire outputs: if output not explicitly mapped, look for gate with same id\n  for (const out of outputs) {\n    const mapped = explicitOutputFrom.get(out.id);\n    if (mapped) out.from = mapped;\n    else if (gates.some((g) => g.id === out.id)) out.from = out.id;\n  }\n\n  // Resolve undefined signal references: auto-declare them as inputs and\n  // emit a warning. Hard-failing here is hostile to LLM-generated DSL where\n  // the model often forgets the explicit `input` line — see playbook.\n  const warnings: string[] = [];\n  const known = new Set<string>([\n    ...inputs.map((i) => i.id),\n    ...gates.map((g) => g.id),\n  ]);\n  const autoDeclared = new Set<string>();\n  for (const g of gates) {\n    for (const inp of g.inputs) {\n      const isLow = inp.startsWith(\"~\");\n      const clean = isLow ? inp.slice(1) : inp;\n      if (!known.has(clean) && !autoDeclared.has(clean)) {\n        autoDeclared.add(clean);\n        inputs.push({\n          id: clean,\n          label: clean,\n          isActiveLow: isLow || undefined,\n          autoDeclared: true,\n        });\n        warnings.push(\n          `Signal \"${clean}\" referenced in gate ${g.id} was not declared; auto-declared as input.`\n        );\n      }\n    }\n  }\n\n  return {\n    type: \"logic\",\n    title,\n    style: style ?? \"ansi\",\n    inputs,\n    outputs,\n    gates,\n    modules: modules.length > 0 ? modules : undefined,\n    warnings: warnings.length > 0 ? warnings : undefined,\n  };\n}\n","import type { LogicGateType } from \"../../core/types\";\n\n// Normalized gate geometry: combinational gates fit in 100×60; sequential in 60×80.\nexport interface GateGeometry {\n  width: number;\n  height: number;\n  inputPins: Array<{ id: string; x: number; y: number; label?: string }>;\n  outputPins: Array<{ id: string; x: number; y: number; label?: string; bubble?: boolean }>;\n  /** Body SVG path (ANSI) */\n  ansiPath: string;\n  /** Output bubble? */\n  outputBubble?: boolean;\n  /** Clock triangle pin id (sequential) */\n  clockPin?: string;\n  /** IEC label inside rectangle */\n  iecLabel?: string;\n}\n\nfunction combPins(nInputs: number, _width: number, leftX: number): Array<{ id: string; x: number; y: number }> {\n  const pins: Array<{ id: string; x: number; y: number }> = [];\n  if (nInputs === 1) {\n    pins.push({ id: \"in1\", x: leftX, y: 30 });\n  } else if (nInputs === 2) {\n    pins.push({ id: \"in1\", x: leftX, y: 15 });\n    pins.push({ id: \"in2\", x: leftX, y: 45 });\n  } else {\n    const step = 50 / (nInputs - 1);\n    for (let i = 0; i < nInputs; i++) {\n      pins.push({ id: `in${i + 1}`, x: leftX, y: 5 + step * i });\n    }\n  }\n  return pins;\n}\n\nexport function getGateGeometry(\n  gateType: LogicGateType,\n  inputCount: number\n): GateGeometry {\n  switch (gateType) {\n    case \"AND\":\n    case \"NAND\": {\n      const bubble = gateType === \"NAND\";\n      return {\n        width: bubble ? 90 : 80,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 20).map((p) => ({ ...p, x: 20 })),\n        outputPins: [{ id: \"out\", x: bubble ? 90 : 80, y: 30, bubble }],\n        ansiPath: \"M 20,60 L 20,0 Q 80,0 80,30 Q 80,60 20,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"&\",\n      };\n    }\n    case \"OR\":\n    case \"NOR\": {\n      const bubble = gateType === \"NOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 18).map((p) => ({ ...p, x: 18 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath: \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"≥1\",\n      };\n    }\n    case \"XOR\":\n    case \"XNOR\": {\n      const bubble = gateType === \"XNOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 12).map((p) => ({ ...p, x: 12 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath:\n          \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z M 8,60 Q 3,30 8,0\",\n        outputBubble: bubble,\n        iecLabel: \"=1\",\n      };\n    }\n    case \"NOT\": {\n      return {\n        width: 70,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 70, y: 30, bubble: true }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: true,\n        iecLabel: \"1\",\n      };\n    }\n    case \"BUF\":\n    case \"SCHMITT\": {\n      return {\n        width: 60,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 60, y: 30 }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        iecLabel: \"1\",\n      };\n    }\n    case \"TRISTATE_BUF\":\n    case \"TRISTATE_INV\":\n    case \"OPEN_DRAIN\": {\n      const bubble = gateType === \"TRISTATE_INV\";\n      return {\n        width: bubble ? 70 : 60,\n        height: 70,\n        inputPins: [\n          { id: \"in1\", x: 10, y: 30 },\n          { id: \"en\", x: 35, y: 65, label: \"EN\" },\n        ],\n        outputPins: [{ id: \"out\", x: bubble ? 70 : 60, y: 30, bubble }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: bubble,\n        iecLabel: \"1\",\n      };\n    }\n    case \"DFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"CLK\", x: 0, y: 50, label: \"\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"DFF\",\n      };\n    }\n    case \"JKFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"J\", x: 0, y: 15, label: \"J\" },\n          { id: \"CLK\", x: 0, y: 40 },\n          { id: \"K\", x: 0, y: 65, label: \"K\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"JK\",\n      };\n    }\n    case \"SRFF\":\n    case \"LATCH_SR\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"S\", x: 0, y: 20, label: \"S\" },\n          { id: \"R\", x: 0, y: 60, label: \"R\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"SR\",\n      };\n    }\n    case \"TFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"T\", x: 0, y: 20, label: \"T\" },\n          { id: \"CLK\", x: 0, y: 50 },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"T\",\n      };\n    }\n    case \"LATCH_D\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"E\", x: 0, y: 60, label: \"E\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"D\",\n      };\n    }\n    default: {\n      // Generic box for MUX/DEMUX/DECODER/ENCODER/COUNTER/SHIFT_REG\n      const ins = Math.max(inputCount, 2);\n      const inputPins = combPins(ins, 100, 0).map((p, i) => ({\n        ...p,\n        x: 0,\n        label: `I${i}`,\n      }));\n      return {\n        width: 100,\n        height: 80,\n        inputPins,\n        outputPins: [{ id: \"out\", x: 100, y: 40 }],\n        ansiPath: \"M 0,0 H 100 V 80 H 0 Z\",\n        iecLabel: gateType,\n      };\n    }\n  }\n}\n","import type { LogicGateAST } from \"../../core/types\";\nimport { getGateGeometry, type GateGeometry } from \"./symbols\";\n\nexport interface LogicLayoutNode {\n  id: string;\n  kind: \"input\" | \"gate\" | \"output\";\n  x: number;\n  y: number;\n  layer: number;\n  geometry?: GateGeometry;\n  gateType?: string;\n  label: string;\n  isActiveLow?: boolean;\n}\n\nexport interface LogicLayoutWire {\n  fromNode: string;\n  fromX: number;\n  fromY: number;\n  toNode: string;\n  toX: number;\n  toY: number;\n  isActiveLow?: boolean;\n  path: string;\n}\n\nexport interface LogicLayoutModule {\n  id: string;\n  label: string;\n  x: number;\n  y: number;\n  width: number;\n  height: number;\n}\n\nexport interface LogicLayoutResult {\n  width: number;\n  height: number;\n  nodes: LogicLayoutNode[];\n  wires: LogicLayoutWire[];\n  modules: LogicLayoutModule[];\n}\n\nconst LAYER_GAP = 80; // extra horizontal gap between layers\nconst ROW_GAP = 40;   // vertical gap between rows in same layer\nconst PORT_SIZE = 40; // input/output port pseudo-box width\nconst PORT_H = 30;\n\nexport function layoutLogic(ast: LogicGateAST): LogicLayoutResult {\n  // Determine layer per signal id using longest-path layering\n  const layerOf = new Map<string, number>();\n  for (const inp of ast.inputs) layerOf.set(inp.id, 0);\n\n  // Build dependency map for gates\n  const pending = new Set(ast.gates.map((g) => g.id));\n  let safety = 0;\n  while (pending.size > 0 && safety++ < 1000) {\n    for (const g of ast.gates) {\n      if (!pending.has(g.id)) continue;\n      let maxDep = -1;\n      let ready = true;\n      for (const inp of g.inputs) {\n        const clean = inp.startsWith(\"~\") ? inp.slice(1) : inp;\n        const l = layerOf.get(clean);\n        if (l === undefined) {\n          ready = false;\n          break;\n        }\n        if (l > maxDep) maxDep = l;\n      }\n      if (ready) {\n        layerOf.set(g.id, maxDep + 1);\n        pending.delete(g.id);\n      }\n    }\n  }\n  if (pending.size > 0) {\n    // cycle or unresolved: force layer 1\n    for (const id of pending) layerOf.set(id, 1);\n  }\n\n  const outputLayer =\n    Math.max(0, ...Array.from(layerOf.values())) + 1;\n  // All outputs get a terminal label node. Use synthetic id to avoid colliding\n  // with a gate that shares the output's name (e.g. `output Y; Y = AND(A,B)`).\n  const outTermId = (o: { id: string }) => `$out$${o.id}`;\n  const portOutputs = ast.outputs.map((o) => ({\n    ...o,\n    termId: outTermId(o),\n    source: o.from,\n  }));\n  for (const o of portOutputs) layerOf.set(o.termId, outputLayer);\n\n  // Group ids by layer\n  const layers = new Map<number, string[]>();\n  const addToLayer = (id: string, layer: number) => {\n    if (!layers.has(layer)) layers.set(layer, []);\n    layers.get(layer)!.push(id);\n  };\n  for (const i of ast.inputs) addToLayer(i.id, 0);\n  for (const g of ast.gates) addToLayer(g.id, layerOf.get(g.id)!);\n  for (const o of portOutputs) addToLayer(o.termId, outputLayer);\n\n  // Compute sizes per node (precompute geometries for gates)\n  const gateGeoms = new Map<string, GateGeometry>();\n  for (const g of ast.gates) {\n    gateGeoms.set(g.id, getGateGeometry(g.gateType, g.inputs.length));\n  }\n\n  // Assign coordinates\n  const nodes: LogicLayoutNode[] = [];\n  const sortedLayers = Array.from(layers.keys()).sort((a, b) => a - b);\n\n  // compute each layer's widest node\n  const layerWidth = new Map<number, number>();\n  for (const [layerIdx, ids] of layers) {\n    let maxW = 60;\n    for (const id of ids) {\n      const g = gateGeoms.get(id);\n      if (g && g.width > maxW) maxW = g.width;\n      if (!g && layerIdx === 0) maxW = Math.max(maxW, PORT_SIZE);\n      if (!g && layerIdx === outputLayer) maxW = Math.max(maxW, PORT_SIZE);\n    }\n    layerWidth.set(layerIdx, maxW);\n  }\n\n  let cursorX = 20;\n  const layerStartMap = new Map<number, number>();\n  for (const layerIdx of sortedLayers) {\n    layerStartMap.set(layerIdx, cursorX);\n    cursorX += (layerWidth.get(layerIdx) ?? 60) + LAYER_GAP;\n  }\n  const totalW = cursorX;\n\n  // Compute vertical placement per layer\n  const heightOf = (id: string): number => {\n    const g = gateGeoms.get(id);\n    if (g) return g.height;\n    return PORT_H;\n  };\n\n  // find max column height\n  let maxColH = 0;\n  for (const ids of layers.values()) {\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    if (total > maxColH) maxColH = total;\n  }\n  const totalH = maxColH + 80;\n\n  const nodeInfo = new Map<string, LogicLayoutNode>();\n  for (const [layerIdx, ids] of layers) {\n    const xStart = layerStartMap.get(layerIdx)!;\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    let y = 40 + (maxColH - total) / 2;\n    for (const id of ids) {\n      const h = heightOf(id);\n      const g = gateGeoms.get(id);\n      let node: LogicLayoutNode;\n      if (layerIdx === 0) {\n        const inp = ast.inputs.find((i) => i.id === id)!;\n        node = {\n          id,\n          kind: \"input\",\n          x: xStart,\n          y,\n          layer: 0,\n          label: inp.label,\n          isActiveLow: inp.isActiveLow,\n        };\n      } else if (layerIdx === outputLayer && !g && id.startsWith(\"$out$\")) {\n        const out = portOutputs.find((o) => o.termId === id)!;\n        node = {\n          id,\n          kind: \"output\",\n          x: xStart,\n          y,\n          layer: outputLayer,\n          label: out.label,\n          isActiveLow: out.isActiveLow,\n        };\n      } else {\n        node = {\n          id,\n          kind: \"gate\",\n          x: xStart,\n          y,\n          layer: layerIdx,\n          geometry: g,\n          gateType: ast.gates.find((gg) => gg.id === id)!.gateType,\n          label: id,\n        };\n      }\n      nodes.push(node);\n      nodeInfo.set(id, node);\n      y += h + ROW_GAP;\n    }\n  }\n\n  // Wires\n  const wires: LogicLayoutWire[] = [];\n  const getSourcePoint = (id: string) => {\n    const n = nodeInfo.get(id);\n    if (!n) return null;\n    if (n.kind === \"input\") return { x: n.x + PORT_SIZE, y: n.y + PORT_H / 2 };\n    if (n.kind === \"gate\" && n.geometry) {\n      const out = n.geometry.outputPins[0];\n      return { x: n.x + out.x, y: n.y + out.y };\n    }\n    return null;\n  };\n\n  for (const g of ast.gates) {\n    const target = nodeInfo.get(g.id);\n    if (!target || !target.geometry) continue;\n    g.inputs.forEach((rawInp, idx) => {\n      const isLow = rawInp.startsWith(\"~\");\n      const srcId = isLow ? rawInp.slice(1) : rawInp;\n      const src = getSourcePoint(srcId);\n      if (!src) return;\n      const pin = target.geometry!.inputPins[idx];\n      if (!pin) return;\n      const toX = target.x + pin.x;\n      const toY = target.y + pin.y;\n      const midX = (src.x + toX) / 2;\n      const path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n      wires.push({\n        fromNode: srcId,\n        fromX: src.x,\n        fromY: src.y,\n        toNode: g.id,\n        toX,\n        toY,\n        isActiveLow: isLow,\n        path,\n      });\n    });\n  }\n\n  // Output port wires\n  for (const o of portOutputs) {\n    const src = getSourcePoint(o.source);\n    const target = nodeInfo.get(o.termId);\n    if (!src || !target || target.kind !== \"output\") continue;\n    const toX = target.x;\n    const toY = target.y + PORT_H / 2;\n    let path: string;\n    if (Math.abs(src.y - toY) < 0.5) {\n      path = `M ${src.x},${src.y} L ${toX},${toY}`;\n    } else {\n      const midX = (src.x + toX) / 2;\n      path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n    }\n    wires.push({\n      fromNode: o.source,\n      fromX: src.x,\n      fromY: src.y,\n      toNode: o.termId,\n      toX,\n      toY,\n      path,\n    });\n  }\n\n  // Module bounding boxes (dashed enclosure for sub-circuits)\n  const modules: LogicLayoutModule[] = [];\n  if (ast.modules && ast.modules.length > 0) {\n    const PAD = 14;\n    for (const mod of ast.modules) {\n      const memberIds = new Set(\n        ast.gates.filter((g) => g.moduleId === mod.id).map((g) => g.id)\n      );\n      if (memberIds.size === 0) continue;\n      let minX = Infinity, minY = Infinity, maxX = -Infinity, maxY = -Infinity;\n      for (const n of nodes) {\n        if (!memberIds.has(n.id)) continue;\n        const w = n.geometry?.width ?? 60;\n        const h = n.geometry?.height ?? 60;\n        if (n.x < minX) minX = n.x;\n        if (n.y < minY) minY = n.y;\n        if (n.x + w > maxX) maxX = n.x + w;\n        if (n.y + h > maxY) maxY = n.y + h;\n      }\n      if (!isFinite(minX)) continue;\n      modules.push({\n        id: mod.id,\n        label: mod.label,\n        x: minX - PAD,\n        y: minY - PAD - 4,\n        width: maxX - minX + PAD * 2,\n        height: maxY - minY + PAD * 2 + 4,\n      });\n    }\n  }\n\n  return { width: totalW, height: totalH, nodes, wires, modules };\n}\n","import type { LogicGateAST, LogicGateStyle, RenderConfig } from \"../../core/types\";\nimport { layoutLogic } from \"./layout\";\nimport {\n  svgRoot,\n  defs,\n  group,\n  el,\n  circle,\n  path as pathEl,\n  text,\n  title as titleEl,\n  desc,\n  polygon,\n} from \"../../core/svg\";\nimport { resolveIndustrialTheme } from \"../../core/theme\";\n\nconst PORT_SIZE = 40;\nconst PORT_H = 30;\n\nfunction renderGateBody(\n  n: ReturnType<typeof layoutLogic>[\"nodes\"][number],\n  style: LogicGateStyle\n): string[] {\n  const out: string[] = [];\n  if (!n.geometry) return out;\n  const g = n.geometry;\n\n  if (style === \"iec\") {\n    // Rectangle\n    out.push(\n      el(\"rect\", {\n        x: 0,\n        y: 0,\n        width: g.width,\n        height: g.height,\n        class: \"schematex-logic-gate-body\",\n      })\n    );\n    if (g.iecLabel) {\n      out.push(\n        text(\n          {\n            x: g.width / 2,\n            y: g.height / 2 + 4,\n            class: \"schematex-logic-gate-iec-label\",\n            \"text-anchor\": \"middle\",\n          },\n          g.iecLabel\n        )\n      );\n    }\n  } else {\n    out.push(\n      el(\"path\", { d: g.ansiPath, class: \"schematex-logic-gate-body\" })\n    );\n  }\n\n  // Output bubble\n  if (g.outputBubble) {\n    const op = g.outputPins[0];\n    out.push(\n      circle({\n        cx: op.x - 4,\n        cy: op.y,\n        r: 4,\n        class: \"schematex-logic-bubble\",\n      })\n    );\n  }\n\n  // Clock triangle\n  if (g.clockPin) {\n    const cp = g.inputPins.find((p) => p.id === g.clockPin);\n    if (cp) {\n      out.push(\n        polygon({\n          points: `${cp.x},${cp.y - 5} ${cp.x + 8},${cp.y} ${cp.x},${cp.y + 5}`,\n          class: \"schematex-logic-clock-tri\",\n        })\n      );\n    }\n  }\n\n  // Qn bubble (sequential)\n  for (const op of g.outputPins) {\n    if (op.bubble && op.id !== \"out\") {\n      out.push(\n        circle({\n          cx: op.x + 4,\n          cy: op.y,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n  }\n\n  // Pin labels\n  for (const pin of g.inputPins) {\n    if (pin.label && pin.id !== g.clockPin) {\n      out.push(\n        text(\n          {\n            x: pin.x + 5,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n  for (const pin of g.outputPins) {\n    if (pin.label) {\n      out.push(\n        text(\n          {\n            x: pin.x - 6,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n            \"text-anchor\": \"end\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n\n  // Gate type label (center top, small)\n  if (style === \"ansi\" && g.iecLabel && g.height >= 60) {\n    const labelX = g.width / 2;\n    const labelY = g.height + 14;\n    out.push(\n      text(\n        {\n          x: labelX,\n          y: labelY,\n          class: \"schematex-logic-gate-type\",\n          \"text-anchor\": \"middle\",\n        },\n        n.gateType ?? \"\"\n      )\n    );\n  }\n\n  return out;\n}\n\nexport function renderLogic(ast: LogicGateAST, config?: RenderConfig): string {\n  const style: LogicGateStyle = ast.style ?? \"ansi\";\n  const layout = layoutLogic(ast);\n  const { width, height } = layout;\n  const t = resolveIndustrialTheme(config?.theme ?? \"default\");\n\n  const gateSvgs: string[] = [];\n  const portSvgs: string[] = [];\n  const moduleSvgs: string[] = [];\n\n  for (const m of layout.modules) {\n    moduleSvgs.push(\n      group({ \"data-module-id\": m.id }, [\n        el(\"rect\", {\n          x: m.x,\n          y: m.y,\n          width: m.width,\n          height: m.height,\n          rx: 6,\n          class: \"schematex-logic-module\",\n        }),\n        text(\n          {\n            x: m.x + 10,\n            y: m.y + 14,\n            class: \"schematex-logic-module-label\",\n          },\n          m.label\n        ),\n      ])\n    );\n  }\n\n  for (const n of layout.nodes) {\n    if (n.kind === \"gate\") {\n      gateSvgs.push(\n        group(\n          {\n            transform: `translate(${n.x}, ${n.y})`,\n            \"data-gate-id\": n.id,\n            \"data-gate-type\": n.gateType ?? \"\",\n          },\n          renderGateBody(n, style)\n        )\n      );\n    } else if (n.kind === \"input\") {\n      // Label + short stub line; no rectangle.\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"input\" }, [\n          text(\n            {\n              x: 0,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n          el(\"line\", {\n            x1: PORT_SIZE - 12,\n            y1: cy,\n            x2: n.isActiveLow ? PORT_SIZE - 8 : PORT_SIZE,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          n.isActiveLow\n            ? circle({\n                cx: PORT_SIZE - 4,\n                cy,\n                r: 4,\n                class: \"schematex-logic-bubble\",\n              })\n            : \"\",\n        ])\n      );\n    } else if (n.kind === \"output\") {\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"output\" }, [\n          el(\"line\", {\n            x1: 0,\n            y1: cy,\n            x2: 12,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          text(\n            {\n              x: 16,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n        ])\n      );\n    }\n  }\n\n  const wireSvgs = layout.wires.map((w) => {\n    const extras: string[] = [];\n    if (w.isActiveLow) {\n      extras.push(\n        circle({\n          cx: w.toX - 4,\n          cy: w.toY,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n    return [\n      pathEl({\n        d: w.path,\n        class: \"schematex-logic-wire\",\n        \"data-from\": w.fromNode,\n        \"data-to\": w.toNode,\n      }),\n      ...extras,\n    ].join(\"\");\n  });\n\n  const css = `\n.schematex-logic { font-family: system-ui, -apple-system, sans-serif; }\n.schematex-logic-gate-body { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.75; stroke-linejoin: round; }\n.schematex-logic-bubble { fill: ${t.bg}; stroke: ${t.strokeHeavy}; stroke-width: 1.5; }\n.schematex-logic-clock-tri { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.5; stroke-linejoin: round; }\n.schematex-logic-wire { stroke: ${t.strokeHeavy}; stroke-width: 1.5; fill: none; stroke-linecap: square; }\n.schematex-logic-port-label { font: 13px system-ui, sans-serif; fill: ${t.text}; }\n.schematex-logic-pin-label { font: 9px sans-serif; fill: ${t.stroke}; }\n.schematex-logic-gate-type { font: 10px sans-serif; fill: ${t.textMuted}; }\n.schematex-logic-gate-iec-label { font: bold 13px sans-serif; fill: ${t.text}; }\n.schematex-logic-title { font: bold 14px sans-serif; fill: ${t.text}; }\n.schematex-logic-module { fill: none; stroke: ${t.textMuted}; stroke-width: 1.25; stroke-dasharray: 6 4; }\n.schematex-logic-module-label { font: 11px sans-serif; fill: ${t.textMuted}; font-style: italic; }\n`.trim();\n\n  const titleSvg = ast.title\n    ? text(\n        {\n          x: width / 2,\n          y: 18,\n          \"text-anchor\": \"middle\",\n          class: \"schematex-logic-title\",\n        },\n        ast.title\n      )\n    : \"\";\n\n  return svgRoot(\n    {\n      class: \"schematex-logic\",\n      viewBox: `0 0 ${width} ${height + (ast.title ? 20 : 0)}`,\n      width,\n      height: height + (ast.title ? 20 : 0),\n      role: \"img\",\n      \"data-diagram-type\": \"logic\",\n    },\n    [\n      titleEl(ast.title ?? \"Logic Gate Diagram\"),\n      desc(\n        `Logic gate diagram with ${ast.gates.length} gates, ${ast.inputs.length} inputs, ${ast.outputs.length} outputs`\n      ),\n      defs([el(\"style\", {}, css)]),\n      group(\n        { transform: `translate(0, ${ast.title ? 20 : 0})` },\n        [\n          group({ class: \"schematex-logic-modules\" }, moduleSvgs),\n          group({ class: \"schematex-logic-wires\" }, wireSvgs),\n          group({ class: \"schematex-logic-gates\" }, gateSvgs),\n          group({ class: \"schematex-logic-ports\" }, portSvgs),\n        ]\n      ),\n      titleSvg,\n    ]\n  );\n}\n","import type { DiagramPlugin } from \"../../core/types\";\nimport { parseLogic } from \"./parser\";\nimport { renderLogic } from \"./renderer\";\n\nexport const logic: DiagramPlugin = {\n  type: \"logic\",\n  detect(text: string): boolean {\n    const first = text.trim().split(\"\\n\")[0]?.trim().toLowerCase() ?? \"\";\n    return first.startsWith(\"logic\");\n  },\n  parse: parseLogic,\n\n  render(text: string, config): string {\n    const ast = parseLogic(text);\n    return renderLogic(ast, config);\n  },\n};\n\nexport { parseLogic } from \"./parser\";\nexport { renderLogic } from \"./renderer\";\nexport { layoutLogic } from \"./layout\";\n"]}