schematex 0.3.2 → 0.3.3

package/dist/{chunk-M5ZC3LFJ.js.map → chunk-IQRRZPVZ.js.map}

@@ -1 +1 @@
-{"version":3,"sources":["../src/diagrams/logic/parser.ts","../src/diagrams/logic/symbols.ts","../src/diagrams/logic/layout.ts","../src/diagrams/logic/renderer.ts","../src/diagrams/logic/index.ts"],"names":["text","title","path","PORT_SIZE","PORT_H"],"mappings":";;;;AAUO,IAAM,eAAA,GAAN,cAA8B,KAAA,CAAM;AAAA,EACzC,YAAY,OAAA,EAAiB;AAC3B,IAAA,KAAA,CAAM,OAAO,CAAA;AACb,IAAA,IAAA,CAAK,IAAA,GAAO,iBAAA;AAAA,EACd;AACF,CAAA;AAEA,IAAM,UAAA,uBAAiB,GAAA,CAAY;AAAA,EACjC,KAAA;AAAA,EAAO,IAAA;AAAA,EAAM,KAAA;AAAA,EAAO,MAAA;AAAA,EAAQ,KAAA;AAAA,EAAO,KAAA;AAAA,EAAO,MAAA;AAAA,EAAQ,KAAA;AAAA,EAClD,cAAA;AAAA,EAAgB,cAAA;AAAA,EAAgB,YAAA;AAAA,EAAc,SAAA;AAAA,EAC9C,KAAA;AAAA,EAAO,MAAA;AAAA,EAAQ,MAAA;AAAA,EAAQ,KAAA;AAAA,EAAO,UAAA;AAAA,EAAY,SAAA;AAAA,EAC1C,KAAA;AAAA,EAAO,OAAA;AAAA,EAAS,SAAA;AAAA,EAAW,SAAA;AAAA,EAAW,SAAA;AAAA,EAAW;AACnD,CAAC,CAAA;AAED,SAAS,SAAS,CAAA,EAAqB;AACrC,EAAA,OAAO,CAAA,CACJ,KAAA,CAAM,GAAG,CAAA,CACT,GAAA,CAAI,CAAC,CAAA,KAAM,CAAA,CAAE,IAAA,EAAM,CAAA,CACnB,MAAA,CAAO,OAAO,CAAA;AACnB;AAEA,SAAS,eAAe,CAAA,EAAqB;AAE3C,EAAA,OAAO,EACJ,KAAA,CAAM,GAAG,CAAA,CACT,GAAA,CAAI,CAAC,CAAA,KAAM,CAAA,CAAE,IAAA,EAAM,EACnB,MAAA,CAAO,OAAO,CAAA,CACd,GAAA,CAAI,CAAC,GAAA,KAAQ;AACZ,IAAA,MAAM,EAAA,GAAK,GAAA,CAAI,OAAA,CAAQ,GAAG,CAAA;AAC1B,IAAA,OAAO,EAAA,IAAM,IAAI,GAAA,CAAI,KAAA,CAAM,KAAK,CAAC,CAAA,CAAE,MAAK,GAAI,GAAA;AAAA,EAC9C,CAAC,CAAA;AACL;AAEO,SAAS,WAAWA,KAAAA,EAA4B;AACrD,EAAA,MAAM,KAAA,GAAQA,KAAAA,CAAK,KAAA,CAAM,IAAI,EAAE,GAAA,CAAI,CAAC,CAAA,KAAM,CAAA,CAAE,OAAA,CAAQ,KAAA,EAAO,EAAE,CAAA,CAAE,MAAM,CAAA;AACrE,EAAA,IAAIC,MAAAA;AACJ,EAAA,IAAI,KAAA;AACJ,EAAA,MAAM,SAA2B,EAAC;AAClC,EAAA,MAAM,UAA6B,EAAC;AACpC,EAAA,MAAM,QAAyB,EAAC;AAChC,EAAA,MAAM,UAA6B,EAAC;AACpC,EAAA,MAAM,cAAwB,EAAC;AAC/B,EAAA,IAAI,aAAA,GAAgB,CAAA;AACpB,EAAA,MAAM,kBAAA,uBAAyB,GAAA,EAAoB;AAEnD,EAAA,KAAA,MAAW,WAAW,KAAA,EAAO;AAE3B,IAAA,MAAM,IAAA,GAAO,OAAA,CAAQ,OAAA,CAAQ,MAAA,EAAQ,EAAE,EAAE,OAAA,CAAQ,OAAA,EAAS,EAAE,CAAA,CAAE,IAAA,EAAK;AACnE,IAAA,IAAI,CAAC,IAAA,EAAM;AAGX,IAAA,MAAM,OAAA,GAAU,IAAA,CAAK,KAAA,CAAM,gDAAgD,CAAA;AAC3E,IAAA,IAAI,OAAA,EAAS;AACX,MAAA,MAAM,KAAA,GAAQ,OAAA,CAAQ,CAAC,CAAA,IAAK,QAAQ,CAAC,CAAA;AACrC,MAAA,MAAM,EAAA,GAAK,OAAO,aAAA,EAAe,CAAA,CAAA;AACjC,MAAA,OAAA,CAAQ,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA;AAC1B,MAAA,WAAA,CAAY,KAAK,EAAE,CAAA;AACnB,MAAA;AAAA,IACF;AAGA,IAAA,IAAI,SAAS,GAAA,EAAK;AAChB,MAAA,IAAI,WAAA,CAAY,WAAW,CAAA,EAAG;AAC5B,QAAA,MAAM,IAAI,gBAAgB,qCAAgC,CAAA;AAAA,MAC5D;AACA,MAAA,WAAA,CAAY,GAAA,EAAI;AAChB,MAAA;AAAA,IACF;AAGA,IAAA,IAAI,WAAA,CAAY,IAAA,CAAK,IAAI,CAAA,EAAG;AAC1B,MAAA,MAAM,CAAA,GAAI,IAAA,CAAK,KAAA,CAAM,WAAW,CAAA;AAChC,MAAA,IAAI,CAAA,EAAGA,MAAAA,GAAQ,CAAA,CAAE,CAAC,CAAA;AAClB,MAAA,MAAM,CAAA,GAAI,IAAA,CAAK,KAAA,CAAM,yBAAyB,CAAA;AAC9C,MAAA,IAAI,CAAA,EAAG,KAAA,GAAQ,CAAA,CAAE,CAAC,EAAE,WAAA,EAAY;AAChC,MAAA;AAAA,IACF;AAGA,IAAA,MAAM,UAAA,GAAa,IAAA,CAAK,KAAA,CAAM,iBAAiB,CAAA;AAC/C,IAAA,IAAI,UAAA,EAAY;AACd,MAAA,KAAA,MAAW,EAAA,IAAM,QAAA,CAAS,UAAA,CAAW,CAAC,CAAC,CAAA,EAAG;AACxC,QAAA,MAAM,KAAA,GAAQ,EAAA,CAAG,UAAA,CAAW,GAAG,CAAA;AAC/B,QAAA,MAAM,KAAA,GAAQ,KAAA,GAAQ,EAAA,CAAG,KAAA,CAAM,CAAC,CAAA,GAAI,EAAA;AACpC,QAAA,MAAA,CAAO,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,OAAO,KAAA,EAAO,WAAA,EAAa,KAAA,IAAS,MAAA,EAAW,CAAA;AAAA,MAC1E;AACA,MAAA;AAAA,IACF;AAGA,IAAA,MAAM,WAAA,GAAc,IAAA,CAAK,KAAA,CAAM,kBAAkB,CAAA;AACjD,IAAA,IAAI,WAAA,EAAa;AACf,MAAA,KAAA,MAAW,EAAA,IAAM,QAAA,CAAS,WAAA,CAAY,CAAC,CAAC,CAAA,EAAG;AACzC,QAAA,OAAA,CAAQ,KAAK,EAAE,EAAA,EAAI,OAAO,EAAA,EAAI,IAAA,EAAM,IAAI,CAAA;AAAA,MAC1C;AACA,MAAA;AAAA,IACF;AAGA,IAAA,MAAM,WAAA,GAAc,IAAA,CAAK,KAAA,CAAM,4CAA4C,CAAA;AAC3E,IAAA,IAAI,WAAA,EAAa;AACf,MAAA,kBAAA,CAAmB,IAAI,WAAA,CAAY,CAAC,CAAA,EAAG,WAAA,CAAY,CAAC,CAAC,CAAA;AACrD,MAAA;AAAA,IACF;AAGA,IAAA,MAAM,SAAA,GAAY,IAAA,CAAK,KAAA,CAAM,yDAAyD,CAAA;AACtF,IAAA,IAAI,SAAA,EAAW;AACb,MAAA,MAAM,EAAA,GAAK,UAAU,CAAC,CAAA;AACtB,MAAA,MAAM,OAAA,GAAU,SAAA,CAAU,CAAC,CAAA,CAAE,WAAA,EAAY;AACzC,MAAA,IAAI,CAAC,UAAA,CAAW,GAAA,CAAI,OAAO,CAAA,EAAG;AAC5B,QAAA,MAAM,IAAI,eAAA,CAAgB,CAAA,mBAAA,EAAsB,OAAO,CAAA,CAAE,CAAA;AAAA,MAC3D;AACA,MAAA,MAAM,OAAA,GAAU,cAAA,CAAe,SAAA,CAAU,CAAC,CAAC,CAAA;AAC3C,MAAA,MAAM,QAAA,GAAW,WAAA,CAAY,WAAA,CAAY,MAAA,GAAS,CAAC,CAAA;AACnD,MAAA,KAAA,CAAM,IAAA,CAAK,EAAE,EAAA,EAAI,QAAA,EAAU,SAA0B,MAAA,EAAQ,OAAA,EAAS,UAAU,CAAA;AAChF,MAAA;AAAA,IACF;AAAA,EACF;AAEA,EAAA,IAAI,WAAA,CAAY,SAAS,CAAA,EAAG;AAC1B,IAAA,MAAM,IAAI,eAAA,CAAgB,CAAA,iBAAA,EAAoB,WAAA,CAAY,MAAM,CAAA,MAAA,CAAQ,CAAA;AAAA,EAC1E;AAGA,EAAA,KAAA,MAAW,OAAO,OAAA,EAAS;AACzB,IAAA,MAAM,MAAA,GAAS,kBAAA,CAAmB,GAAA,CAAI,GAAA,CAAI,EAAE,CAAA;AAC5C,IAAA,IAAI,MAAA,MAAY,IAAA,GAAO,MAAA;AAAA,SAAA,IACd,KAAA,CAAM,IAAA,CAAK,CAAC,CAAA,KAAM,CAAA,CAAE,EAAA,KAAO,GAAA,CAAI,EAAE,CAAA,EAAG,GAAA,CAAI,IAAA,GAAO,GAAA,CAAI,EAAA;AAAA,EAC9D;AAGA,EAAA,MAAM,KAAA,uBAAY,GAAA,CAAY;AAAA,IAC5B,GAAG,MAAA,CAAO,GAAA,CAAI,CAAC,CAAA,KAAM,EAAE,EAAE,CAAA;AAAA,IACzB,GAAG,KAAA,CAAM,GAAA,CAAI,CAAC,CAAA,KAAM,EAAE,EAAE;AAAA,GACzB,CAAA;AACD,EAAA,KAAA,MAAW,KAAK,KAAA,EAAO;AACrB,IAAA,KAAA,MAAW,GAAA,IAAO,EAAE,MAAA,EAAQ;AAC1B,MAAA,MAAM,KAAA,GAAQ,IAAI,UAAA,CAAW,GAAG,IAAI,GAAA,CAAI,KAAA,CAAM,CAAC,CAAA,GAAI,GAAA;AACnD,MAAA,IAAI,CAAC,KAAA,CAAM,GAAA,CAAI,KAAK,CAAA,EAAG;AACrB,QAAA,MAAM,IAAI,eAAA,CAAgB,CAAA,gBAAA,EAAmB,KAAK,CAAA,UAAA,EAAa,CAAA,CAAE,EAAE,CAAA,CAAE,CAAA;AAAA,MACvE;AAAA,IACF;AAAA,EACF;AAEA,EAAA,OAAO;AAAA,IACL,IAAA,EAAM,OAAA;AAAA,IACN,KAAA,EAAAA,MAAAA;AAAA,IACA,OAAO,KAAA,IAAS,MAAA;AAAA,IAChB,MAAA;AAAA,IACA,OAAA;AAAA,IACA,KAAA;AAAA,IACA,OAAA,EAAS,OAAA,CAAQ,MAAA,GAAS,CAAA,GAAI,OAAA,GAAU;AAAA,GAC1C;AACF;;;AClJA,SAAS,QAAA,CAAS,OAAA,EAAiB,MAAA,EAAgB,KAAA,EAA4D;AAC7G,EAAA,MAAM,OAAoD,EAAC;AAC3D,EAAA,IAAI,YAAY,CAAA,EAAG;AACjB,IAAA,IAAA,CAAK,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,GAAG,KAAA,EAAO,CAAA,EAAG,IAAI,CAAA;AAAA,EAC1C,CAAA,MAAA,IAAW,YAAY,CAAA,EAAG;AACxB,IAAA,IAAA,CAAK,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,GAAG,KAAA,EAAO,CAAA,EAAG,IAAI,CAAA;AACxC,IAAA,IAAA,CAAK,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,GAAG,KAAA,EAAO,CAAA,EAAG,IAAI,CAAA;AAAA,EAC1C,CAAA,MAAO;AACL,IAAA,MAAM,IAAA,GAAO,MAAM,OAAA,GAAU,CAAA,CAAA;AAC7B,IAAA,KAAA,IAAS,CAAA,GAAI,CAAA,EAAG,CAAA,GAAI,OAAA,EAAS,CAAA,EAAA,EAAK;AAChC,MAAA,IAAA,CAAK,IAAA,CAAK,EAAE,EAAA,EAAI,CAAA,EAAA,EAAK,CAAA,GAAI,CAAC,CAAA,CAAA,EAAI,CAAA,EAAG,KAAA,EAAO,CAAA,EAAG,CAAA,GAAI,IAAA,GAAO,GAAG,CAAA;AAAA,IAC3D;AAAA,EACF;AACA,EAAA,OAAO,IAAA;AACT;AAEO,SAAS,eAAA,CACd,UACA,UAAA,EACc;AACd,EAAA,QAAQ,QAAA;AAAU,IAChB,KAAK,KAAA;AAAA,IACL,KAAK,MAAA,EAAQ;AACX,MAAA,MAAM,SAAS,QAAA,KAAa,MAAA;AAC5B,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,SAAS,EAAA,GAAK,EAAA;AAAA,QACrB,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,QAAA,CAAS,UAAA,EAAY,EAAA,EAAI,EAAE,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,MAAO,EAAE,GAAG,CAAA,EAAG,CAAA,EAAG,IAAG,CAAE,CAAA;AAAA,QACpE,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,MAAA,GAAS,EAAA,GAAK,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,CAAA;AAAA,QAC9D,QAAA,EAAU,6CAAA;AAAA,QACV,YAAA,EAAc,MAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,IAAA;AAAA,IACL,KAAK,KAAA,EAAO;AACV,MAAA,MAAM,SAAS,QAAA,KAAa,KAAA;AAC5B,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,SAAS,EAAA,GAAK,EAAA;AAAA,QACrB,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,QAAA,CAAS,UAAA,EAAY,EAAA,EAAI,EAAE,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,MAAO,EAAE,GAAG,CAAA,EAAG,CAAA,EAAG,IAAG,CAAE,CAAA;AAAA,QACpE,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,MAAA,GAAS,EAAA,GAAK,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,CAAA;AAAA,QAC9D,QAAA,EAAU,oDAAA;AAAA,QACV,YAAA,EAAc,MAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA;AAAA,IACL,KAAK,MAAA,EAAQ;AACX,MAAA,MAAM,SAAS,QAAA,KAAa,MAAA;AAC5B,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,SAAS,EAAA,GAAK,EAAA;AAAA,QACrB,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,QAAA,CAAS,UAAA,EAAY,EAAA,EAAI,EAAE,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,MAAO,EAAE,GAAG,CAAA,EAAG,CAAA,EAAG,IAAG,CAAE,CAAA;AAAA,QACpE,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,MAAA,GAAS,EAAA,GAAK,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,CAAA;AAAA,QAC9D,QAAA,EACE,sEAAA;AAAA,QACF,YAAA,EAAc,MAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA,EAAO;AACV,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,CAAC,EAAE,EAAA,EAAI,OAAO,CAAA,EAAG,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,CAAA;AAAA,QACvC,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,IAAA,EAAM,CAAA;AAAA,QACtD,QAAA,EAAU,0BAAA;AAAA,QACV,YAAA,EAAc,IAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA;AAAA,IACL,KAAK,SAAA,EAAW;AACd,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,CAAC,EAAE,EAAA,EAAI,OAAO,CAAA,EAAG,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,CAAA;AAAA,QACvC,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,OAAO,CAAA,EAAG,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,CAAA;AAAA,QACxC,QAAA,EAAU,0BAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,cAAA;AAAA,IACL,KAAK,cAAA;AAAA,IACL,KAAK,YAAA,EAAc;AACjB,MAAA,MAAM,SAAS,QAAA,KAAa,cAAA;AAC5B,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,SAAS,EAAA,GAAK,EAAA;AAAA,QACrB,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAG;AAAA,UAC1B,EAAE,IAAI,IAAA,EAAM,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,IAAA;AAAK,SACxC;AAAA,QACA,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,MAAA,GAAS,EAAA,GAAK,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,CAAA;AAAA,QAC9D,QAAA,EAAU,0BAAA;AAAA,QACV,YAAA,EAAc,MAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA,EAAO;AACV,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,IAAI,KAAA,EAAO,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,EAAA;AAAG,SACtC;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU,KAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,MAAA,EAAQ;AACX,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,CAAA,EAAG,GAAG,EAAA,EAAG;AAAA,UACzB,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA;AAAI,SACrC;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU,KAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,MAAA;AAAA,IACL,KAAK,UAAA,EAAY;AACf,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA;AAAI,SACrC;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA,EAAO;AACV,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,CAAA,EAAG,GAAG,EAAA;AAAG,SAC3B;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU,KAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,SAAA,EAAW;AACd,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA;AAAI,SACrC;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,SAAS;AAEP,MAAA,MAAM,GAAA,GAAM,IAAA,CAAK,GAAA,CAAI,UAAA,EAAY,CAAC,CAAA;AAClC,MAAA,MAAM,SAAA,GAAY,SAAS,GAAA,EAAK,GAAA,EAAK,CAAC,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,EAAG,CAAA,MAAO;AAAA,QACrD,GAAG,CAAA;AAAA,QACH,CAAA,EAAG,CAAA;AAAA,QACH,KAAA,EAAO,IAAI,CAAC,CAAA;AAAA,OACd,CAAE,CAAA;AACF,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,GAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA;AAAA,QACA,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,OAAO,CAAA,EAAG,GAAA,EAAK,CAAA,EAAG,EAAA,EAAI,CAAA;AAAA,QACzC,QAAA,EAAU,wBAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA;AAEJ;;;AClLA,IAAM,SAAA,GAAY,EAAA;AAClB,IAAM,OAAA,GAAU,EAAA;AAChB,IAAM,SAAA,GAAY,EAAA;AAClB,IAAM,MAAA,GAAS,EAAA;AAER,SAAS,YAAY,GAAA,EAAsC;AAEhE,EAAA,MAAM,OAAA,uBAAc,GAAA,EAAoB;AACxC,EAAA,KAAA,MAAW,OAAO,GAAA,CAAI,MAAA,UAAgB,GAAA,CAAI,GAAA,CAAI,IAAI,CAAC,CAAA;AAGnD,EAAA,MAAM,OAAA,GAAU,IAAI,GAAA,CAAI,GAAA,CAAI,KAAA,CAAM,IAAI,CAAC,CAAA,KAAM,CAAA,CAAE,EAAE,CAAC,CAAA;AAClD,EAAA,IAAI,MAAA,GAAS,CAAA;AACb,EAAA,OAAO,OAAA,CAAQ,IAAA,GAAO,CAAA,IAAK,MAAA,EAAA,GAAW,GAAA,EAAM;AAC1C,IAAA,KAAA,MAAW,CAAA,IAAK,IAAI,KAAA,EAAO;AACzB,MAAA,IAAI,CAAC,OAAA,CAAQ,GAAA,CAAI,CAAA,CAAE,EAAE,CAAA,EAAG;AACxB,MAAA,IAAI,MAAA,GAAS,EAAA;AACb,MAAA,IAAI,KAAA,GAAQ,IAAA;AACZ,MAAA,KAAA,MAAW,GAAA,IAAO,EAAE,MAAA,EAAQ;AAC1B,QAAA,MAAM,KAAA,GAAQ,IAAI,UAAA,CAAW,GAAG,IAAI,GAAA,CAAI,KAAA,CAAM,CAAC,CAAA,GAAI,GAAA;AACnD,QAAA,MAAM,CAAA,GAAI,OAAA,CAAQ,GAAA,CAAI,KAAK,CAAA;AAC3B,QAAA,IAAI,MAAM,MAAA,EAAW;AACnB,UAAA,KAAA,GAAQ,KAAA;AACR,UAAA;AAAA,QACF;AACA,QAAA,IAAI,CAAA,GAAI,QAAQ,MAAA,GAAS,CAAA;AAAA,MAC3B;AACA,MAAA,IAAI,KAAA,EAAO;AACT,QAAA,OAAA,CAAQ,GAAA,CAAI,CAAA,CAAE,EAAA,EAAI,MAAA,GAAS,CAAC,CAAA;AAC5B,QAAA,OAAA,CAAQ,MAAA,CAAO,EAAE,EAAE,CAAA;AAAA,MACrB;AAAA,IACF;AAAA,EACF;AACA,EAAA,IAAI,OAAA,CAAQ,OAAO,CAAA,EAAG;AAEpB,IAAA,KAAA,MAAW,EAAA,IAAM,OAAA,EAAS,OAAA,CAAQ,GAAA,CAAI,IAAI,CAAC,CAAA;AAAA,EAC7C;AAEA,EAAA,MAAM,WAAA,GACJ,IAAA,CAAK,GAAA,CAAI,CAAA,EAAG,GAAG,KAAA,CAAM,IAAA,CAAK,OAAA,CAAQ,MAAA,EAAQ,CAAC,CAAA,GAAI,CAAA;AAGjD,EAAA,MAAM,SAAA,GAAY,CAAC,CAAA,KAAsB,CAAA,KAAA,EAAQ,EAAE,EAAE,CAAA,CAAA;AACrD,EAAA,MAAM,WAAA,GAAc,GAAA,CAAI,OAAA,CAAQ,GAAA,CAAI,CAAC,CAAA,MAAO;AAAA,IAC1C,GAAG,CAAA;AAAA,IACH,MAAA,EAAQ,UAAU,CAAC,CAAA;AAAA,IACnB,QAAQ,CAAA,CAAE;AAAA,GACZ,CAAE,CAAA;AACF,EAAA,KAAA,MAAW,KAAK,WAAA,EAAa,OAAA,CAAQ,GAAA,CAAI,CAAA,CAAE,QAAQ,WAAW,CAAA;AAG9D,EAAA,MAAM,MAAA,uBAAa,GAAA,EAAsB;AACzC,EAAA,MAAM,UAAA,GAAa,CAAC,EAAA,EAAY,KAAA,KAAkB;AAChD,IAAA,IAAI,CAAC,OAAO,GAAA,CAAI,KAAK,GAAG,MAAA,CAAO,GAAA,CAAI,KAAA,EAAO,EAAE,CAAA;AAC5C,IAAA,MAAA,CAAO,GAAA,CAAI,KAAK,CAAA,CAAG,IAAA,CAAK,EAAE,CAAA;AAAA,EAC5B,CAAA;AACA,EAAA,KAAA,MAAW,KAAK,GAAA,CAAI,MAAA,EAAQ,UAAA,CAAW,CAAA,CAAE,IAAI,CAAC,CAAA;AAC9C,EAAA,KAAA,MAAW,CAAA,IAAK,GAAA,CAAI,KAAA,EAAO,UAAA,CAAW,CAAA,CAAE,IAAI,OAAA,CAAQ,GAAA,CAAI,CAAA,CAAE,EAAE,CAAE,CAAA;AAC9D,EAAA,KAAA,MAAW,CAAA,IAAK,WAAA,EAAa,UAAA,CAAW,CAAA,CAAE,QAAQ,WAAW,CAAA;AAG7D,EAAA,MAAM,SAAA,uBAAgB,GAAA,EAA0B;AAChD,EAAA,KAAA,MAAW,CAAA,IAAK,IAAI,KAAA,EAAO;AACzB,IAAA,SAAA,CAAU,GAAA,CAAI,EAAE,EAAA,EAAI,eAAA,CAAgB,EAAE,QAAA,EAAU,CAAA,CAAE,MAAA,CAAO,MAAM,CAAC,CAAA;AAAA,EAClE;AAGA,EAAA,MAAM,QAA2B,EAAC;AAClC,EAAA,MAAM,YAAA,GAAe,KAAA,CAAM,IAAA,CAAK,MAAA,CAAO,IAAA,EAAM,CAAA,CAAE,IAAA,CAAK,CAAC,CAAA,EAAG,CAAA,KAAM,CAAA,GAAI,CAAC,CAAA;AAGnE,EAAA,MAAM,UAAA,uBAAiB,GAAA,EAAoB;AAC3C,EAAA,KAAA,MAAW,CAAC,QAAA,EAAU,GAAG,CAAA,IAAK,MAAA,EAAQ;AACpC,IAAA,IAAI,IAAA,GAAO,EAAA;AACX,IAAA,KAAA,MAAW,MAAM,GAAA,EAAK;AACpB,MAAA,MAAM,CAAA,GAAI,SAAA,CAAU,GAAA,CAAI,EAAE,CAAA;AAC1B,MAAA,IAAI,CAAA,IAAK,CAAA,CAAE,KAAA,GAAQ,IAAA,SAAa,CAAA,CAAE,KAAA;AAClC,MAAA,IAAI,CAAC,KAAK,QAAA,KAAa,CAAA,SAAU,IAAA,CAAK,GAAA,CAAI,MAAM,SAAS,CAAA;AACzD,MAAA,IAAI,CAAC,KAAK,QAAA,KAAa,WAAA,SAAoB,IAAA,CAAK,GAAA,CAAI,MAAM,SAAS,CAAA;AAAA,IACrE;AACA,IAAA,UAAA,CAAW,GAAA,CAAI,UAAU,IAAI,CAAA;AAAA,EAC/B;AAEA,EAAA,IAAI,OAAA,GAAU,EAAA;AACd,EAAA,MAAM,aAAA,uBAAoB,GAAA,EAAoB;AAC9C,EAAA,KAAA,MAAW,YAAY,YAAA,EAAc;AACnC,IAAA,aAAA,CAAc,GAAA,CAAI,UAAU,OAAO,CAAA;AACnC,IAAA,OAAA,IAAA,CAAY,UAAA,CAAW,GAAA,CAAI,QAAQ,CAAA,IAAK,EAAA,IAAM,SAAA;AAAA,EAChD;AACA,EAAA,MAAM,MAAA,GAAS,OAAA;AAGf,EAAA,MAAM,QAAA,GAAW,CAAC,EAAA,KAAuB;AACvC,IAAA,MAAM,CAAA,GAAI,SAAA,CAAU,GAAA,CAAI,EAAE,CAAA;AAC1B,IAAA,IAAI,CAAA,SAAU,CAAA,CAAE,MAAA;AAChB,IAAA,OAAO,MAAA;AAAA,EACT,CAAA;AAGA,EAAA,IAAI,OAAA,GAAU,CAAA;AACd,EAAA,KAAA,MAAW,GAAA,IAAO,MAAA,CAAO,MAAA,EAAO,EAAG;AACjC,IAAA,MAAM,KAAA,GAAQ,GAAA,CAAI,MAAA,CAAO,CAAC,GAAG,EAAA,KAAO,CAAA,GAAI,QAAA,CAAS,EAAE,CAAA,EAAG,CAAC,CAAA,GAAA,CAAK,GAAA,CAAI,SAAS,CAAA,IAAK,OAAA;AAC9E,IAAA,IAAI,KAAA,GAAQ,SAAS,OAAA,GAAU,KAAA;AAAA,EACjC;AACA,EAAA,MAAM,SAAS,OAAA,GAAU,EAAA;AAEzB,EAAA,MAAM,QAAA,uBAAe,GAAA,EAA6B;AAClD,EAAA,KAAA,MAAW,CAAC,QAAA,EAAU,GAAG,CAAA,IAAK,MAAA,EAAQ;AACpC,IAAA,MAAM,MAAA,GAAS,aAAA,CAAc,GAAA,CAAI,QAAQ,CAAA;AACzC,IAAA,MAAM,KAAA,GAAQ,GAAA,CAAI,MAAA,CAAO,CAAC,GAAG,EAAA,KAAO,CAAA,GAAI,QAAA,CAAS,EAAE,CAAA,EAAG,CAAC,CAAA,GAAA,CAAK,GAAA,CAAI,SAAS,CAAA,IAAK,OAAA;AAC9E,IAAA,IAAI,CAAA,GAAI,EAAA,GAAA,CAAM,OAAA,GAAU,KAAA,IAAS,CAAA;AACjC,IAAA,KAAA,MAAW,MAAM,GAAA,EAAK;AACpB,MAAA,MAAM,CAAA,GAAI,SAAS,EAAE,CAAA;AACrB,MAAA,MAAM,CAAA,GAAI,SAAA,CAAU,GAAA,CAAI,EAAE,CAAA;AAC1B,MAAA,IAAI,IAAA;AACJ,MAAA,IAAI,aAAa,CAAA,EAAG;AAClB,QAAA,MAAM,GAAA,GAAM,IAAI,MAAA,CAAO,IAAA,CAAK,CAAC,CAAA,KAAM,CAAA,CAAE,OAAO,EAAE,CAAA;AAC9C,QAAA,IAAA,GAAO;AAAA,UACL,EAAA;AAAA,UACA,IAAA,EAAM,OAAA;AAAA,UACN,CAAA,EAAG,MAAA;AAAA,UACH,CAAA;AAAA,UACA,KAAA,EAAO,CAAA;AAAA,UACP,OAAO,GAAA,CAAI,KAAA;AAAA,UACX,aAAa,GAAA,CAAI;AAAA,SACnB;AAAA,MACF,CAAA,MAAA,IAAW,aAAa,WAAA,IAAe,CAAC,KAAK,EAAA,CAAG,UAAA,CAAW,OAAO,CAAA,EAAG;AACnE,QAAA,MAAM,MAAM,WAAA,CAAY,IAAA,CAAK,CAAC,CAAA,KAAM,CAAA,CAAE,WAAW,EAAE,CAAA;AACnD,QAAA,IAAA,GAAO;AAAA,UACL,EAAA;AAAA,UACA,IAAA,EAAM,QAAA;AAAA,UACN,CAAA,EAAG,MAAA;AAAA,UACH,CAAA;AAAA,UACA,KAAA,EAAO,WAAA;AAAA,UACP,OAAO,GAAA,CAAI,KAAA;AAAA,UACX,aAAa,GAAA,CAAI;AAAA,SACnB;AAAA,MACF,CAAA,MAAO;AACL,QAAA,IAAA,GAAO;AAAA,UACL,EAAA;AAAA,UACA,IAAA,EAAM,MAAA;AAAA,UACN,CAAA,EAAG,MAAA;AAAA,UACH,CAAA;AAAA,UACA,KAAA,EAAO,QAAA;AAAA,UACP,QAAA,EAAU,CAAA;AAAA,UACV,QAAA,EAAU,IAAI,KAAA,CAAM,IAAA,CAAK,CAAC,EAAA,KAAO,EAAA,CAAG,EAAA,KAAO,EAAE,CAAA,CAAG,QAAA;AAAA,UAChD,KAAA,EAAO;AAAA,SACT;AAAA,MACF;AACA,MAAA,KAAA,CAAM,KAAK,IAAI,CAAA;AACf,MAAA,QAAA,CAAS,GAAA,CAAI,IAAI,IAAI,CAAA;AACrB,MAAA,CAAA,IAAK,CAAA,GAAI,OAAA;AAAA,IACX;AAAA,EACF;AAGA,EAAA,MAAM,QAA2B,EAAC;AAClC,EAAA,MAAM,cAAA,GAAiB,CAAC,EAAA,KAAe;AACrC,IAAA,MAAM,CAAA,GAAI,QAAA,CAAS,GAAA,CAAI,EAAE,CAAA;AACzB,IAAA,IAAI,CAAC,GAAG,OAAO,IAAA;AACf,IAAA,IAAI,CAAA,CAAE,IAAA,KAAS,OAAA,EAAS,OAAO,EAAE,CAAA,EAAG,CAAA,CAAE,CAAA,GAAI,SAAA,EAAW,CAAA,EAAG,CAAA,CAAE,CAAA,GAAI,SAAS,CAAA,EAAE;AACzE,IAAA,IAAI,CAAA,CAAE,IAAA,KAAS,MAAA,IAAU,CAAA,CAAE,QAAA,EAAU;AACnC,MAAA,MAAM,GAAA,GAAM,CAAA,CAAE,QAAA,CAAS,UAAA,CAAW,CAAC,CAAA;AACnC,MAAA,OAAO,EAAE,CAAA,EAAG,CAAA,CAAE,CAAA,GAAI,GAAA,CAAI,GAAG,CAAA,EAAG,CAAA,CAAE,CAAA,GAAI,GAAA,CAAI,CAAA,EAAE;AAAA,IAC1C;AACA,IAAA,OAAO,IAAA;AAAA,EACT,CAAA;AAEA,EAAA,KAAA,MAAW,CAAA,IAAK,IAAI,KAAA,EAAO;AACzB,IAAA,MAAM,MAAA,GAAS,QAAA,CAAS,GAAA,CAAI,CAAA,CAAE,EAAE,CAAA;AAChC,IAAA,IAAI,CAAC,MAAA,IAAU,CAAC,MAAA,CAAO,QAAA,EAAU;AACjC,IAAA,CAAA,CAAE,MAAA,CAAO,OAAA,CAAQ,CAAC,MAAA,EAAQ,GAAA,KAAQ;AAChC,MAAA,MAAM,KAAA,GAAQ,MAAA,CAAO,UAAA,CAAW,GAAG,CAAA;AACnC,MAAA,MAAM,KAAA,GAAQ,KAAA,GAAQ,MAAA,CAAO,KAAA,CAAM,CAAC,CAAA,GAAI,MAAA;AACxC,MAAA,MAAM,GAAA,GAAM,eAAe,KAAK,CAAA;AAChC,MAAA,IAAI,CAAC,GAAA,EAAK;AACV,MAAA,MAAM,GAAA,GAAM,MAAA,CAAO,QAAA,CAAU,SAAA,CAAU,GAAG,CAAA;AAC1C,MAAA,IAAI,CAAC,GAAA,EAAK;AACV,MAAA,MAAM,GAAA,GAAM,MAAA,CAAO,CAAA,GAAI,GAAA,CAAI,CAAA;AAC3B,MAAA,MAAM,GAAA,GAAM,MAAA,CAAO,CAAA,GAAI,GAAA,CAAI,CAAA;AAC3B,MAAA,MAAM,IAAA,GAAA,CAAQ,GAAA,CAAI,CAAA,GAAI,GAAA,IAAO,CAAA;AAC7B,MAAA,MAAMC,QAAO,CAAA,EAAA,EAAK,GAAA,CAAI,CAAC,CAAA,CAAA,EAAI,GAAA,CAAI,CAAC,CAAA,GAAA,EAAM,IAAI,IAAI,GAAA,CAAI,CAAC,MAAM,IAAI,CAAA,CAAA,EAAI,GAAG,CAAA,GAAA,EAAM,GAAG,IAAI,GAAG,CAAA,CAAA;AACpF,MAAA,KAAA,CAAM,IAAA,CAAK;AAAA,QACT,QAAA,EAAU,KAAA;AAAA,QACV,OAAO,GAAA,CAAI,CAAA;AAAA,QACX,OAAO,GAAA,CAAI,CAAA;AAAA,QACX,QAAQ,CAAA,CAAE,EAAA;AAAA,QACV,GAAA;AAAA,QACA,GAAA;AAAA,QACA,WAAA,EAAa,KAAA;AAAA,QACb,IAAA,EAAAA;AAAA,OACD,CAAA;AAAA,IACH,CAAC,CAAA;AAAA,EACH;AAGA,EAAA,KAAA,MAAW,KAAK,WAAA,EAAa;AAC3B,IAAA,MAAM,GAAA,GAAM,cAAA,CAAe,CAAA,CAAE,MAAM,CAAA;AACnC,IAAA,MAAM,MAAA,GAAS,QAAA,CAAS,GAAA,CAAI,CAAA,CAAE,MAAM,CAAA;AACpC,IAAA,IAAI,CAAC,GAAA,IAAO,CAAC,MAAA,IAAU,MAAA,CAAO,SAAS,QAAA,EAAU;AACjD,IAAA,MAAM,MAAM,MAAA,CAAO,CAAA;AACnB,IAAA,MAAM,GAAA,GAAM,MAAA,CAAO,CAAA,GAAI,MAAA,GAAS,CAAA;AAChC,IAAA,IAAIA,KAAAA;AACJ,IAAA,IAAI,KAAK,GAAA,CAAI,GAAA,CAAI,CAAA,GAAI,GAAG,IAAI,GAAA,EAAK;AAC/B,MAAAA,KAAAA,GAAO,CAAA,EAAA,EAAK,GAAA,CAAI,CAAC,CAAA,CAAA,EAAI,IAAI,CAAC,CAAA,GAAA,EAAM,GAAG,CAAA,CAAA,EAAI,GAAG,CAAA,CAAA;AAAA,IAC5C,CAAA,MAAO;AACL,MAAA,MAAM,IAAA,GAAA,CAAQ,GAAA,CAAI,CAAA,GAAI,GAAA,IAAO,CAAA;AAC7B,MAAAA,QAAO,CAAA,EAAA,EAAK,GAAA,CAAI,CAAC,CAAA,CAAA,EAAI,GAAA,CAAI,CAAC,CAAA,GAAA,EAAM,IAAI,IAAI,GAAA,CAAI,CAAC,MAAM,IAAI,CAAA,CAAA,EAAI,GAAG,CAAA,GAAA,EAAM,GAAG,IAAI,GAAG,CAAA,CAAA;AAAA,IAChF;AACA,IAAA,KAAA,CAAM,IAAA,CAAK;AAAA,MACT,UAAU,CAAA,CAAE,MAAA;AAAA,MACZ,OAAO,GAAA,CAAI,CAAA;AAAA,MACX,OAAO,GAAA,CAAI,CAAA;AAAA,MACX,QAAQ,CAAA,CAAE,MAAA;AAAA,MACV,GAAA;AAAA,MACA,GAAA;AAAA,MACA,IAAA,EAAAA;AAAA,KACD,CAAA;AAAA,EACH;AAGA,EAAA,MAAM,UAA+B,EAAC;AACtC,EAAA,IAAI,GAAA,CAAI,OAAA,IAAW,GAAA,CAAI,OAAA,CAAQ,SAAS,CAAA,EAAG;AACzC,IAAA,MAAM,GAAA,GAAM,EAAA;AACZ,IAAA,KAAA,MAAW,GAAA,IAAO,IAAI,OAAA,EAAS;AAC7B,MAAA,MAAM,YAAY,IAAI,GAAA;AAAA,QACpB,GAAA,CAAI,KAAA,CAAM,MAAA,CAAO,CAAC,MAAM,CAAA,CAAE,QAAA,KAAa,GAAA,CAAI,EAAE,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,KAAM,EAAE,EAAE;AAAA,OAChE;AACA,MAAA,IAAI,SAAA,CAAU,SAAS,CAAA,EAAG;AAC1B,MAAA,IAAI,OAAO,QAAA,EAAU,IAAA,GAAO,QAAA,EAAU,IAAA,GAAO,WAAW,IAAA,GAAO,CAAA,QAAA;AAC/D,MAAA,KAAA,MAAW,KAAK,KAAA,EAAO;AACrB,QAAA,IAAI,CAAC,SAAA,CAAU,GAAA,CAAI,CAAA,CAAE,EAAE,CAAA,EAAG;AAC1B,QAAA,MAAM,CAAA,GAAI,CAAA,CAAE,QAAA,EAAU,KAAA,IAAS,EAAA;AAC/B,QAAA,MAAM,CAAA,GAAI,CAAA,CAAE,QAAA,EAAU,MAAA,IAAU,EAAA;AAChC,QAAA,IAAI,CAAA,CAAE,CAAA,GAAI,IAAA,EAAM,IAAA,GAAO,CAAA,CAAE,CAAA;AACzB,QAAA,IAAI,CAAA,CAAE,CAAA,GAAI,IAAA,EAAM,IAAA,GAAO,CAAA,CAAE,CAAA;AACzB,QAAA,IAAI,EAAE,CAAA,GAAI,CAAA,GAAI,IAAA,EAAM,IAAA,GAAO,EAAE,CAAA,GAAI,CAAA;AACjC,QAAA,IAAI,EAAE,CAAA,GAAI,CAAA,GAAI,IAAA,EAAM,IAAA,GAAO,EAAE,CAAA,GAAI,CAAA;AAAA,MACnC;AACA,MAAA,IAAI,CAAC,QAAA,CAAS,IAAI,CAAA,EAAG;AACrB,MAAA,OAAA,CAAQ,IAAA,CAAK;AAAA,QACX,IAAI,GAAA,CAAI,EAAA;AAAA,QACR,OAAO,GAAA,CAAI,KAAA;AAAA,QACX,GAAG,IAAA,GAAO,GAAA;AAAA,QACV,CAAA,EAAG,OAAO,GAAA,GAAM,CAAA;AAAA,QAChB,KAAA,EAAO,IAAA,GAAO,IAAA,GAAO,GAAA,GAAM,CAAA;AAAA,QAC3B,MAAA,EAAQ,IAAA,GAAO,IAAA,GAAO,GAAA,GAAM,CAAA,GAAI;AAAA,OACjC,CAAA;AAAA,IACH;AAAA,EACF;AAEA,EAAA,OAAO,EAAE,KAAA,EAAO,MAAA,EAAQ,QAAQ,MAAA,EAAQ,KAAA,EAAO,OAAO,OAAA,EAAQ;AAChE;;;ACvRA,IAAMC,UAAAA,GAAY,EAAA;AAClB,IAAMC,OAAAA,GAAS,EAAA;AAEf,SAAS,cAAA,CACP,GACA,KAAA,EACU;AACV,EAAA,MAAM,MAAgB,EAAC;AACvB,EAAA,IAAI,CAAC,CAAA,CAAE,QAAA,EAAU,OAAO,GAAA;AACxB,EAAA,MAAM,IAAI,CAAA,CAAE,QAAA;AAEZ,EAAA,IAAI,UAAU,KAAA,EAAO;AAEnB,IAAA,GAAA,CAAI,IAAA;AAAA,MACF,GAAG,MAAA,EAAQ;AAAA,QACT,CAAA,EAAG,CAAA;AAAA,QACH,CAAA,EAAG,CAAA;AAAA,QACH,OAAO,CAAA,CAAE,KAAA;AAAA,QACT,QAAQ,CAAA,CAAE,MAAA;AAAA,QACV,KAAA,EAAO;AAAA,OACR;AAAA,KACH;AACA,IAAA,IAAI,EAAE,QAAA,EAAU;AACd,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,IAAA;AAAA,UACE;AAAA,YACE,CAAA,EAAG,EAAE,KAAA,GAAQ,CAAA;AAAA,YACb,CAAA,EAAG,CAAA,CAAE,MAAA,GAAS,CAAA,GAAI,CAAA;AAAA,YAClB,KAAA,EAAO,gCAAA;AAAA,YACP,aAAA,EAAe;AAAA,WACjB;AAAA,UACA,CAAA,CAAE;AAAA;AACJ,OACF;AAAA,IACF;AAAA,EACF,CAAA,MAAO;AACL,IAAA,GAAA,CAAI,IAAA;AAAA,MACF,EAAA,CAAG,QAAQ,EAAE,CAAA,EAAG,EAAE,QAAA,EAAU,KAAA,EAAO,6BAA6B;AAAA,KAClE;AAAA,EACF;AAGA,EAAA,IAAI,EAAE,YAAA,EAAc;AAClB,IAAA,MAAM,EAAA,GAAK,CAAA,CAAE,UAAA,CAAW,CAAC,CAAA;AACzB,IAAA,GAAA,CAAI,IAAA;AAAA,MACF,MAAA,CAAO;AAAA,QACL,EAAA,EAAI,GAAG,CAAA,GAAI,CAAA;AAAA,QACX,IAAI,EAAA,CAAG,CAAA;AAAA,QACP,CAAA,EAAG,CAAA;AAAA,QACH,KAAA,EAAO;AAAA,OACR;AAAA,KACH;AAAA,EACF;AAGA,EAAA,IAAI,EAAE,QAAA,EAAU;AACd,IAAA,MAAM,EAAA,GAAK,EAAE,SAAA,CAAU,IAAA,CAAK,CAAC,CAAA,KAAM,CAAA,CAAE,EAAA,KAAO,CAAA,CAAE,QAAQ,CAAA;AACtD,IAAA,IAAI,EAAA,EAAI;AACN,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,OAAA,CAAQ;AAAA,UACN,MAAA,EAAQ,GAAG,EAAA,CAAG,CAAC,IAAI,EAAA,CAAG,CAAA,GAAI,CAAC,CAAA,CAAA,EAAI,EAAA,CAAG,IAAI,CAAC,CAAA,CAAA,EAAI,GAAG,CAAC,CAAA,CAAA,EAAI,GAAG,CAAC,CAAA,CAAA,EAAI,EAAA,CAAG,CAAA,GAAI,CAAC,CAAA,CAAA;AAAA,UACnE,KAAA,EAAO;AAAA,SACR;AAAA,OACH;AAAA,IACF;AAAA,EACF;AAGA,EAAA,KAAA,MAAW,EAAA,IAAM,EAAE,UAAA,EAAY;AAC7B,IAAA,IAAI,EAAA,CAAG,MAAA,IAAU,EAAA,CAAG,EAAA,KAAO,KAAA,EAAO;AAChC,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,MAAA,CAAO;AAAA,UACL,EAAA,EAAI,GAAG,CAAA,GAAI,CAAA;AAAA,UACX,IAAI,EAAA,CAAG,CAAA;AAAA,UACP,CAAA,EAAG,CAAA;AAAA,UACH,KAAA,EAAO;AAAA,SACR;AAAA,OACH;AAAA,IACF;AAAA,EACF;AAGA,EAAA,KAAA,MAAW,GAAA,IAAO,EAAE,SAAA,EAAW;AAC7B,IAAA,IAAI,GAAA,CAAI,KAAA,IAAS,GAAA,CAAI,EAAA,KAAO,EAAE,QAAA,EAAU;AACtC,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,IAAA;AAAA,UACE;AAAA,YACE,CAAA,EAAG,IAAI,CAAA,GAAI,CAAA;AAAA,YACX,CAAA,EAAG,IAAI,CAAA,GAAI,CAAA;AAAA,YACX,KAAA,EAAO;AAAA,WACT;AAAA,UACA,GAAA,CAAI;AAAA;AACN,OACF;AAAA,IACF;AAAA,EACF;AACA,EAAA,KAAA,MAAW,GAAA,IAAO,EAAE,UAAA,EAAY;AAC9B,IAAA,IAAI,IAAI,KAAA,EAAO;AACb,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,IAAA;AAAA,UACE;AAAA,YACE,CAAA,EAAG,IAAI,CAAA,GAAI,CAAA;AAAA,YACX,CAAA,EAAG,IAAI,CAAA,GAAI,CAAA;AAAA,YACX,KAAA,EAAO,2BAAA;AAAA,YACP,aAAA,EAAe;AAAA,WACjB;AAAA,UACA,GAAA,CAAI;AAAA;AACN,OACF;AAAA,IACF;AAAA,EACF;AAGA,EAAA,IAAI,UAAU,MAAA,IAAU,CAAA,CAAE,QAAA,IAAY,CAAA,CAAE,UAAU,EAAA,EAAI;AACpD,IAAA,MAAM,MAAA,GAAS,EAAE,KAAA,GAAQ,CAAA;AACzB,IAAA,MAAM,MAAA,GAAS,EAAE,MAAA,GAAS,EAAA;AAC1B,IAAA,GAAA,CAAI,IAAA;AAAA,MACF,IAAA;AAAA,QACE;AAAA,UACE,CAAA,EAAG,MAAA;AAAA,UACH,CAAA,EAAG,MAAA;AAAA,UACH,KAAA,EAAO,2BAAA;AAAA,UACP,aAAA,EAAe;AAAA,SACjB;AAAA,QACA,EAAE,QAAA,IAAY;AAAA;AAChB,KACF;AAAA,EACF;AAEA,EAAA,OAAO,GAAA;AACT;AAEO,SAAS,WAAA,CAAY,KAAmB,MAAA,EAA+B;AAC5E,EAAA,MAAM,KAAA,GAAwB,IAAI,KAAA,IAAS,MAAA;AAC3C,EAAA,MAAM,MAAA,GAAS,YAAY,GAAG,CAAA;AAC9B,EAAA,MAAM,EAAE,KAAA,EAAO,MAAA,EAAO,GAAI,MAAA;AAC1B,EAAA,MAAM,CAAA,GAAI,sBAAA,CAAuB,MAAA,EAAQ,KAAA,IAAS,SAAS,CAAA;AAE3D,EAAA,MAAM,WAAqB,EAAC;AAC5B,EAAA,MAAM,WAAqB,EAAC;AAC5B,EAAA,MAAM,aAAuB,EAAC;AAE9B,EAAA,KAAA,MAAW,CAAA,IAAK,OAAO,OAAA,EAAS;AAC9B,IAAA,UAAA,CAAW,IAAA;AAAA,MACT,KAAA,CAAM,EAAE,gBAAA,EAAkB,CAAA,CAAE,IAAG,EAAG;AAAA,QAChC,GAAG,MAAA,EAAQ;AAAA,UACT,GAAG,CAAA,CAAE,CAAA;AAAA,UACL,GAAG,CAAA,CAAE,CAAA;AAAA,UACL,OAAO,CAAA,CAAE,KAAA;AAAA,UACT,QAAQ,CAAA,CAAE,MAAA;AAAA,UACV,EAAA,EAAI,CAAA;AAAA,UACJ,KAAA,EAAO;AAAA,SACR,CAAA;AAAA,QACD,IAAA;AAAA,UACE;AAAA,YACE,CAAA,EAAG,EAAE,CAAA,GAAI,EAAA;AAAA,YACT,CAAA,EAAG,EAAE,CAAA,GAAI,EAAA;AAAA,YACT,KAAA,EAAO;AAAA,WACT;AAAA,UACA,CAAA,CAAE;AAAA;AACJ,OACD;AAAA,KACH;AAAA,EACF;AAEA,EAAA,KAAA,MAAW,CAAA,IAAK,OAAO,KAAA,EAAO;AAC5B,IAAA,IAAI,CAAA,CAAE,SAAS,MAAA,EAAQ;AACrB,MAAA,QAAA,CAAS,IAAA;AAAA,QACP,KAAA;AAAA,UACE;AAAA,YACE,WAAW,CAAA,UAAA,EAAa,CAAA,CAAE,CAAC,CAAA,EAAA,EAAK,EAAE,CAAC,CAAA,CAAA,CAAA;AAAA,YACnC,gBAAgB,CAAA,CAAE,EAAA;AAAA,YAClB,gBAAA,EAAkB,EAAE,QAAA,IAAY;AAAA,WAClC;AAAA,UACA,cAAA,CAAe,GAAG,KAAK;AAAA;AACzB,OACF;AAAA,IACF,CAAA,MAAA,IAAW,CAAA,CAAE,IAAA,KAAS,OAAA,EAAS;AAE7B,MAAA,MAAM,KAAKA,OAAAA,GAAS,CAAA;AACpB,MAAA,QAAA,CAAS,IAAA;AAAA,QACP,KAAA,CAAM,EAAE,SAAA,EAAW,CAAA,UAAA,EAAa,CAAA,CAAE,CAAC,CAAA,EAAA,EAAK,CAAA,CAAE,CAAC,CAAA,CAAA,CAAA,EAAK,WAAA,EAAa,OAAA,EAAQ,EAAG;AAAA,UACtE,IAAA;AAAA,YACE;AAAA,cACE,CAAA,EAAG,CAAA;AAAA,cACH,GAAG,EAAA,GAAK,CAAA;AAAA,cACR,aAAA,EAAe,OAAA;AAAA,cACf,KAAA,EAAO;AAAA,aACT;AAAA,YACA,CAAA,CAAE;AAAA,WACJ;AAAA,UACA,GAAG,MAAA,EAAQ;AAAA,YACT,IAAID,UAAAA,GAAY,EAAA;AAAA,YAChB,EAAA,EAAI,EAAA;AAAA,YACJ,EAAA,EAAI,CAAA,CAAE,WAAA,GAAcA,UAAAA,GAAY,CAAA,GAAIA,UAAAA;AAAA,YACpC,EAAA,EAAI,EAAA;AAAA,YACJ,KAAA,EAAO;AAAA,WACR,CAAA;AAAA,UACD,CAAA,CAAE,cACE,MAAA,CAAO;AAAA,YACL,IAAIA,UAAAA,GAAY,CAAA;AAAA,YAChB,EAAA;AAAA,YACA,CAAA,EAAG,CAAA;AAAA,YACH,KAAA,EAAO;AAAA,WACR,CAAA,GACD;AAAA,SACL;AAAA,OACH;AAAA,IACF,CAAA,MAAA,IAAW,CAAA,CAAE,IAAA,KAAS,QAAA,EAAU;AAC9B,MAAA,MAAM,KAAKC,OAAAA,GAAS,CAAA;AACpB,MAAA,QAAA,CAAS,IAAA;AAAA,QACP,KAAA,CAAM,EAAE,SAAA,EAAW,CAAA,UAAA,EAAa,CAAA,CAAE,CAAC,CAAA,EAAA,EAAK,CAAA,CAAE,CAAC,CAAA,CAAA,CAAA,EAAK,WAAA,EAAa,QAAA,EAAS,EAAG;AAAA,UACvE,GAAG,MAAA,EAAQ;AAAA,YACT,EAAA,EAAI,CAAA;AAAA,YACJ,EAAA,EAAI,EAAA;AAAA,YACJ,EAAA,EAAI,EAAA;AAAA,YACJ,EAAA,EAAI,EAAA;AAAA,YACJ,KAAA,EAAO;AAAA,WACR,CAAA;AAAA,UACD,IAAA;AAAA,YACE;AAAA,cACE,CAAA,EAAG,EAAA;AAAA,cACH,GAAG,EAAA,GAAK,CAAA;AAAA,cACR,aAAA,EAAe,OAAA;AAAA,cACf,KAAA,EAAO;AAAA,aACT;AAAA,YACA,CAAA,CAAE;AAAA;AACJ,SACD;AAAA,OACH;AAAA,IACF;AAAA,EACF;AAEA,EAAA,MAAM,QAAA,GAAW,MAAA,CAAO,KAAA,CAAM,GAAA,CAAI,CAAC,CAAA,KAAM;AACvC,IAAA,MAAM,SAAmB,EAAC;AAC1B,IAAA,IAAI,EAAE,WAAA,EAAa;AACjB,MAAA,MAAA,CAAO,IAAA;AAAA,QACL,MAAA,CAAO;AAAA,UACL,EAAA,EAAI,EAAE,GAAA,GAAM,CAAA;AAAA,UACZ,IAAI,CAAA,CAAE,GAAA;AAAA,UACN,CAAA,EAAG,CAAA;AAAA,UACH,KAAA,EAAO;AAAA,SACR;AAAA,OACH;AAAA,IACF;AACA,IAAA,OAAO;AAAA,MACL,IAAA,CAAO;AAAA,QACL,GAAG,CAAA,CAAE,IAAA;AAAA,QACL,KAAA,EAAO,sBAAA;AAAA,QACP,aAAa,CAAA,CAAE,QAAA;AAAA,QACf,WAAW,CAAA,CAAE;AAAA,OACd,CAAA;AAAA,MACD,GAAG;AAAA,KACL,CAAE,KAAK,EAAE,CAAA;AAAA,EACX,CAAC,CAAA;AAED,EAAA,MAAM,GAAA,GAAM;AAAA,+BAAA,EACmB,EAAE,EAAE,CAAA;AAAA,iDAAA,EACc,EAAE,WAAW,CAAA;AAAA,gCAAA,EAC9B,CAAA,CAAE,EAAE,CAAA,UAAA,EAAa,CAAA,CAAE,WAAW,CAAA;AAAA,iDAAA,EACb,EAAE,WAAW,CAAA;AAAA,gCAAA,EAC9B,EAAE,WAAW,CAAA;AAAA,sEAAA,EACyB,EAAE,IAAI,CAAA;AAAA,yDAAA,EACnB,EAAE,MAAM,CAAA;AAAA,0DAAA,EACP,EAAE,SAAS,CAAA;AAAA,oEAAA,EACD,EAAE,IAAI,CAAA;AAAA,2DAAA,EACf,EAAE,IAAI,CAAA;AAAA,8CAAA,EACnB,EAAE,SAAS,CAAA;AAAA,6DAAA,EACI,EAAE,SAAS,CAAA;AAAA,CAAA,CACxE,IAAA,EAAK;AAEL,EAAA,MAAM,QAAA,GAAW,IAAI,KAAA,GACjB,IAAA;AAAA,IACE;AAAA,MACE,GAAG,KAAA,GAAQ,CAAA;AAAA,MACX,CAAA,EAAG,EAAA;AAAA,MACH,aAAA,EAAe,QAAA;AAAA,MACf,KAAA,EAAO;AAAA,KACT;AAAA,IACA,GAAA,CAAI;AAAA,GACN,GACA,EAAA;AAEJ,EAAA,OAAO,OAAA;AAAA,IACL;AAAA,MACE,KAAA,EAAO,iBAAA;AAAA,MACP,OAAA,EAAS,OAAO,KAAK,CAAA,CAAA,EAAI,UAAU,GAAA,CAAI,KAAA,GAAQ,KAAK,CAAA,CAAE,CAAA,CAAA;AAAA,MACtD,KAAA;AAAA,MACA,MAAA,EAAQ,MAAA,IAAU,GAAA,CAAI,KAAA,GAAQ,EAAA,GAAK,CAAA,CAAA;AAAA,MACnC,IAAA,EAAM,KAAA;AAAA,MACN,mBAAA,EAAqB;AAAA,KACvB;AAAA,IACA;AAAA,MACE,KAAA,CAAQ,GAAA,CAAI,KAAA,IAAS,oBAAoB,CAAA;AAAA,MACzC,IAAA;AAAA,QACE,CAAA,wBAAA,EAA2B,GAAA,CAAI,KAAA,CAAM,MAAM,CAAA,QAAA,EAAW,GAAA,CAAI,MAAA,CAAO,MAAM,CAAA,SAAA,EAAY,GAAA,CAAI,OAAA,CAAQ,MAAM,CAAA,QAAA;AAAA,OACvG;AAAA,MACA,IAAA,CAAK,CAAC,EAAA,CAAG,OAAA,EAAS,EAAC,EAAG,GAAG,CAAC,CAAC,CAAA;AAAA,MAC3B,KAAA;AAAA,QACE,EAAE,SAAA,EAAW,CAAA,aAAA,EAAgB,IAAI,KAAA,GAAQ,EAAA,GAAK,CAAC,CAAA,CAAA,CAAA,EAAI;AAAA,QACnD;AAAA,UACE,KAAA,CAAM,EAAE,KAAA,EAAO,yBAAA,IAA6B,UAAU,CAAA;AAAA,UACtD,KAAA,CAAM,EAAE,KAAA,EAAO,uBAAA,IAA2B,QAAQ,CAAA;AAAA,UAClD,KAAA,CAAM,EAAE,KAAA,EAAO,uBAAA,IAA2B,QAAQ,CAAA;AAAA,UAClD,KAAA,CAAM,EAAE,KAAA,EAAO,uBAAA,IAA2B,QAAQ;AAAA;AACpD,OACF;AAAA,MACA;AAAA;AACF,GACF;AACF;;;AClUO,IAAM,KAAA,GAAuB;AAAA,EAClC,IAAA,EAAM,OAAA;AAAA,EACN,OAAOJ,KAAAA,EAAuB;AAC5B,IAAA,MAAM,KAAA,GAAQA,KAAAA,CAAK,IAAA,EAAK,CAAE,KAAA,CAAM,IAAI,CAAA,CAAE,CAAC,CAAA,EAAG,IAAA,EAAK,CAAE,WAAA,EAAY,IAAK,EAAA;AAClE,IAAA,OAAO,KAAA,CAAM,WAAW,OAAO,CAAA;AAAA,EACjC,CAAA;AAAA,EACA,KAAA,EAAO,UAAA;AAAA,EAEP,MAAA,CAAOA,OAAc,MAAA,EAAgB;AACnC,IAAA,MAAM,GAAA,GAAM,WAAWA,KAAI,CAAA;AAC3B,IAAA,OAAO,WAAA,CAAY,KAAK,MAAM,CAAA;AAAA,EAChC;AACF","file":"chunk-M5ZC3LFJ.js","sourcesContent":["import type {\n  LogicGateAST,\n  LogicGateInput,\n  LogicGateOutput,\n  LogicGateNode,\n  LogicGateType,\n  LogicGateStyle,\n  LogicGateModule,\n} from \"../../core/types\";\n\nexport class LogicParseError extends Error {\n  constructor(message: string) {\n    super(message);\n    this.name = \"LogicParseError\";\n  }\n}\n\nconst GATE_TYPES = new Set<string>([\n  \"AND\", \"OR\", \"NOT\", \"NAND\", \"NOR\", \"XOR\", \"XNOR\", \"BUF\",\n  \"TRISTATE_BUF\", \"TRISTATE_INV\", \"OPEN_DRAIN\", \"SCHMITT\",\n  \"DFF\", \"JKFF\", \"SRFF\", \"TFF\", \"LATCH_SR\", \"LATCH_D\",\n  \"MUX\", \"DEMUX\", \"DECODER\", \"ENCODER\", \"COUNTER\", \"SHIFT_REG\",\n]);\n\nfunction splitIds(s: string): string[] {\n  return s\n    .split(\",\")\n    .map((x) => x.trim())\n    .filter(Boolean);\n}\n\nfunction parseInputList(s: string): string[] {\n  // Supports named (D=A) or positional. Returns raw tokens (keep ~ prefix for active-low).\n  return s\n    .split(\",\")\n    .map((x) => x.trim())\n    .filter(Boolean)\n    .map((tok) => {\n      const eq = tok.indexOf(\"=\");\n      return eq >= 0 ? tok.slice(eq + 1).trim() : tok;\n    });\n}\n\nexport function parseLogic(text: string): LogicGateAST {\n  const lines = text.split(\"\\n\").map((l) => l.replace(/\\r$/, \"\").trim());\n  let title: string | undefined;\n  let style: LogicGateStyle | undefined;\n  const inputs: LogicGateInput[] = [];\n  const outputs: LogicGateOutput[] = [];\n  const gates: LogicGateNode[] = [];\n  const modules: LogicGateModule[] = [];\n  const moduleStack: string[] = [];\n  let moduleCounter = 0;\n  const explicitOutputFrom = new Map<string, string>();\n\n  for (const rawLine of lines) {\n    // Strip line comments\n    const line = rawLine.replace(/#.*$/, \"\").replace(/--.*$/, \"\").trim();\n    if (!line) continue;\n\n    // module \"Label\" {   or  module Label {\n    const modOpen = line.match(/^module\\s+(?:\"([^\"]+)\"|([a-zA-Z_][\\w]*))\\s*\\{$/);\n    if (modOpen) {\n      const label = modOpen[1] ?? modOpen[2];\n      const id = `mod_${moduleCounter++}`;\n      modules.push({ id, label });\n      moduleStack.push(id);\n      continue;\n    }\n\n    // close module\n    if (line === \"}\") {\n      if (moduleStack.length === 0) {\n        throw new LogicParseError(\"Unmatched `}` — no open module\");\n      }\n      moduleStack.pop();\n      continue;\n    }\n\n    // Header\n    if (/^logic\\b/i.test(line)) {\n      const t = line.match(/\"([^\"]*)\"/);\n      if (t) title = t[1];\n      const s = line.match(/style\\s*:\\s*(ansi|iec)/i);\n      if (s) style = s[1].toLowerCase() as LogicGateStyle;\n      continue;\n    }\n\n    // input A, B, C\n    const inputMatch = line.match(/^input\\s+(.+)$/i);\n    if (inputMatch) {\n      for (const id of splitIds(inputMatch[1])) {\n        const isLow = id.startsWith(\"~\");\n        const clean = isLow ? id.slice(1) : id;\n        inputs.push({ id: clean, label: clean, isActiveLow: isLow || undefined });\n      }\n      continue;\n    }\n\n    // output X, Y\n    const outputMatch = line.match(/^output\\s+(.+)$/i);\n    if (outputMatch) {\n      for (const id of splitIds(outputMatch[1])) {\n        outputs.push({ id, label: id, from: id });\n      }\n      continue;\n    }\n\n    // OUTPUT <- GATE  (map output to gate)\n    const assignMatch = line.match(/^([a-zA-Z_][\\w]*)\\s*<-\\s*([a-zA-Z_][\\w]*)$/);\n    if (assignMatch) {\n      explicitOutputFrom.set(assignMatch[1], assignMatch[2]);\n      continue;\n    }\n\n    // Gate: ID = GATE(a, b, ...)\n    const gateMatch = line.match(/^([a-zA-Z_][\\w]*)\\s*=\\s*([A-Za-z_][\\w]*)\\s*\\(([^)]*)\\)$/);\n    if (gateMatch) {\n      const id = gateMatch[1];\n      const rawType = gateMatch[2].toUpperCase();\n      if (!GATE_TYPES.has(rawType)) {\n        throw new LogicParseError(`Unknown gate type: ${rawType}`);\n      }\n      const gInputs = parseInputList(gateMatch[3]);\n      const moduleId = moduleStack[moduleStack.length - 1];\n      gates.push({ id, gateType: rawType as LogicGateType, inputs: gInputs, moduleId });\n      continue;\n    }\n  }\n\n  if (moduleStack.length > 0) {\n    throw new LogicParseError(`Unclosed module (${moduleStack.length} open)`);\n  }\n\n  // Wire outputs: if output not explicitly mapped, look for gate with same id\n  for (const out of outputs) {\n    const mapped = explicitOutputFrom.get(out.id);\n    if (mapped) out.from = mapped;\n    else if (gates.some((g) => g.id === out.id)) out.from = out.id;\n  }\n\n  // Validate: undefined input references\n  const known = new Set<string>([\n    ...inputs.map((i) => i.id),\n    ...gates.map((g) => g.id),\n  ]);\n  for (const g of gates) {\n    for (const inp of g.inputs) {\n      const clean = inp.startsWith(\"~\") ? inp.slice(1) : inp;\n      if (!known.has(clean)) {\n        throw new LogicParseError(`Unknown signal \"${clean}\" in gate ${g.id}`);\n      }\n    }\n  }\n\n  return {\n    type: \"logic\",\n    title,\n    style: style ?? \"ansi\",\n    inputs,\n    outputs,\n    gates,\n    modules: modules.length > 0 ? modules : undefined,\n  };\n}\n","import type { LogicGateType } from \"../../core/types\";\n\n// Normalized gate geometry: combinational gates fit in 100×60; sequential in 60×80.\nexport interface GateGeometry {\n  width: number;\n  height: number;\n  inputPins: Array<{ id: string; x: number; y: number; label?: string }>;\n  outputPins: Array<{ id: string; x: number; y: number; label?: string; bubble?: boolean }>;\n  /** Body SVG path (ANSI) */\n  ansiPath: string;\n  /** Output bubble? */\n  outputBubble?: boolean;\n  /** Clock triangle pin id (sequential) */\n  clockPin?: string;\n  /** IEC label inside rectangle */\n  iecLabel?: string;\n}\n\nfunction combPins(nInputs: number, _width: number, leftX: number): Array<{ id: string; x: number; y: number }> {\n  const pins: Array<{ id: string; x: number; y: number }> = [];\n  if (nInputs === 1) {\n    pins.push({ id: \"in1\", x: leftX, y: 30 });\n  } else if (nInputs === 2) {\n    pins.push({ id: \"in1\", x: leftX, y: 15 });\n    pins.push({ id: \"in2\", x: leftX, y: 45 });\n  } else {\n    const step = 50 / (nInputs - 1);\n    for (let i = 0; i < nInputs; i++) {\n      pins.push({ id: `in${i + 1}`, x: leftX, y: 5 + step * i });\n    }\n  }\n  return pins;\n}\n\nexport function getGateGeometry(\n  gateType: LogicGateType,\n  inputCount: number\n): GateGeometry {\n  switch (gateType) {\n    case \"AND\":\n    case \"NAND\": {\n      const bubble = gateType === \"NAND\";\n      return {\n        width: bubble ? 90 : 80,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 20).map((p) => ({ ...p, x: 20 })),\n        outputPins: [{ id: \"out\", x: bubble ? 90 : 80, y: 30, bubble }],\n        ansiPath: \"M 20,60 L 20,0 Q 80,0 80,30 Q 80,60 20,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"&\",\n      };\n    }\n    case \"OR\":\n    case \"NOR\": {\n      const bubble = gateType === \"NOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 18).map((p) => ({ ...p, x: 18 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath: \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"≥1\",\n      };\n    }\n    case \"XOR\":\n    case \"XNOR\": {\n      const bubble = gateType === \"XNOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 12).map((p) => ({ ...p, x: 12 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath:\n          \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z M 8,60 Q 3,30 8,0\",\n        outputBubble: bubble,\n        iecLabel: \"=1\",\n      };\n    }\n    case \"NOT\": {\n      return {\n        width: 70,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 70, y: 30, bubble: true }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: true,\n        iecLabel: \"1\",\n      };\n    }\n    case \"BUF\":\n    case \"SCHMITT\": {\n      return {\n        width: 60,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 60, y: 30 }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        iecLabel: \"1\",\n      };\n    }\n    case \"TRISTATE_BUF\":\n    case \"TRISTATE_INV\":\n    case \"OPEN_DRAIN\": {\n      const bubble = gateType === \"TRISTATE_INV\";\n      return {\n        width: bubble ? 70 : 60,\n        height: 70,\n        inputPins: [\n          { id: \"in1\", x: 10, y: 30 },\n          { id: \"en\", x: 35, y: 65, label: \"EN\" },\n        ],\n        outputPins: [{ id: \"out\", x: bubble ? 70 : 60, y: 30, bubble }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: bubble,\n        iecLabel: \"1\",\n      };\n    }\n    case \"DFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"CLK\", x: 0, y: 50, label: \"\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"DFF\",\n      };\n    }\n    case \"JKFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"J\", x: 0, y: 15, label: \"J\" },\n          { id: \"CLK\", x: 0, y: 40 },\n          { id: \"K\", x: 0, y: 65, label: \"K\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"JK\",\n      };\n    }\n    case \"SRFF\":\n    case \"LATCH_SR\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"S\", x: 0, y: 20, label: \"S\" },\n          { id: \"R\", x: 0, y: 60, label: \"R\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"SR\",\n      };\n    }\n    case \"TFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"T\", x: 0, y: 20, label: \"T\" },\n          { id: \"CLK\", x: 0, y: 50 },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"T\",\n      };\n    }\n    case \"LATCH_D\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"E\", x: 0, y: 60, label: \"E\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"D\",\n      };\n    }\n    default: {\n      // Generic box for MUX/DEMUX/DECODER/ENCODER/COUNTER/SHIFT_REG\n      const ins = Math.max(inputCount, 2);\n      const inputPins = combPins(ins, 100, 0).map((p, i) => ({\n        ...p,\n        x: 0,\n        label: `I${i}`,\n      }));\n      return {\n        width: 100,\n        height: 80,\n        inputPins,\n        outputPins: [{ id: \"out\", x: 100, y: 40 }],\n        ansiPath: \"M 0,0 H 100 V 80 H 0 Z\",\n        iecLabel: gateType,\n      };\n    }\n  }\n}\n","import type { LogicGateAST } from \"../../core/types\";\nimport { getGateGeometry, type GateGeometry } from \"./symbols\";\n\nexport interface LogicLayoutNode {\n  id: string;\n  kind: \"input\" | \"gate\" | \"output\";\n  x: number;\n  y: number;\n  layer: number;\n  geometry?: GateGeometry;\n  gateType?: string;\n  label: string;\n  isActiveLow?: boolean;\n}\n\nexport interface LogicLayoutWire {\n  fromNode: string;\n  fromX: number;\n  fromY: number;\n  toNode: string;\n  toX: number;\n  toY: number;\n  isActiveLow?: boolean;\n  path: string;\n}\n\nexport interface LogicLayoutModule {\n  id: string;\n  label: string;\n  x: number;\n  y: number;\n  width: number;\n  height: number;\n}\n\nexport interface LogicLayoutResult {\n  width: number;\n  height: number;\n  nodes: LogicLayoutNode[];\n  wires: LogicLayoutWire[];\n  modules: LogicLayoutModule[];\n}\n\nconst LAYER_GAP = 80; // extra horizontal gap between layers\nconst ROW_GAP = 40;   // vertical gap between rows in same layer\nconst PORT_SIZE = 40; // input/output port pseudo-box width\nconst PORT_H = 30;\n\nexport function layoutLogic(ast: LogicGateAST): LogicLayoutResult {\n  // Determine layer per signal id using longest-path layering\n  const layerOf = new Map<string, number>();\n  for (const inp of ast.inputs) layerOf.set(inp.id, 0);\n\n  // Build dependency map for gates\n  const pending = new Set(ast.gates.map((g) => g.id));\n  let safety = 0;\n  while (pending.size > 0 && safety++ < 1000) {\n    for (const g of ast.gates) {\n      if (!pending.has(g.id)) continue;\n      let maxDep = -1;\n      let ready = true;\n      for (const inp of g.inputs) {\n        const clean = inp.startsWith(\"~\") ? inp.slice(1) : inp;\n        const l = layerOf.get(clean);\n        if (l === undefined) {\n          ready = false;\n          break;\n        }\n        if (l > maxDep) maxDep = l;\n      }\n      if (ready) {\n        layerOf.set(g.id, maxDep + 1);\n        pending.delete(g.id);\n      }\n    }\n  }\n  if (pending.size > 0) {\n    // cycle or unresolved: force layer 1\n    for (const id of pending) layerOf.set(id, 1);\n  }\n\n  const outputLayer =\n    Math.max(0, ...Array.from(layerOf.values())) + 1;\n  // All outputs get a terminal label node. Use synthetic id to avoid colliding\n  // with a gate that shares the output's name (e.g. `output Y; Y = AND(A,B)`).\n  const outTermId = (o: { id: string }) => `$out$${o.id}`;\n  const portOutputs = ast.outputs.map((o) => ({\n    ...o,\n    termId: outTermId(o),\n    source: o.from,\n  }));\n  for (const o of portOutputs) layerOf.set(o.termId, outputLayer);\n\n  // Group ids by layer\n  const layers = new Map<number, string[]>();\n  const addToLayer = (id: string, layer: number) => {\n    if (!layers.has(layer)) layers.set(layer, []);\n    layers.get(layer)!.push(id);\n  };\n  for (const i of ast.inputs) addToLayer(i.id, 0);\n  for (const g of ast.gates) addToLayer(g.id, layerOf.get(g.id)!);\n  for (const o of portOutputs) addToLayer(o.termId, outputLayer);\n\n  // Compute sizes per node (precompute geometries for gates)\n  const gateGeoms = new Map<string, GateGeometry>();\n  for (const g of ast.gates) {\n    gateGeoms.set(g.id, getGateGeometry(g.gateType, g.inputs.length));\n  }\n\n  // Assign coordinates\n  const nodes: LogicLayoutNode[] = [];\n  const sortedLayers = Array.from(layers.keys()).sort((a, b) => a - b);\n\n  // compute each layer's widest node\n  const layerWidth = new Map<number, number>();\n  for (const [layerIdx, ids] of layers) {\n    let maxW = 60;\n    for (const id of ids) {\n      const g = gateGeoms.get(id);\n      if (g && g.width > maxW) maxW = g.width;\n      if (!g && layerIdx === 0) maxW = Math.max(maxW, PORT_SIZE);\n      if (!g && layerIdx === outputLayer) maxW = Math.max(maxW, PORT_SIZE);\n    }\n    layerWidth.set(layerIdx, maxW);\n  }\n\n  let cursorX = 20;\n  const layerStartMap = new Map<number, number>();\n  for (const layerIdx of sortedLayers) {\n    layerStartMap.set(layerIdx, cursorX);\n    cursorX += (layerWidth.get(layerIdx) ?? 60) + LAYER_GAP;\n  }\n  const totalW = cursorX;\n\n  // Compute vertical placement per layer\n  const heightOf = (id: string): number => {\n    const g = gateGeoms.get(id);\n    if (g) return g.height;\n    return PORT_H;\n  };\n\n  // find max column height\n  let maxColH = 0;\n  for (const ids of layers.values()) {\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    if (total > maxColH) maxColH = total;\n  }\n  const totalH = maxColH + 80;\n\n  const nodeInfo = new Map<string, LogicLayoutNode>();\n  for (const [layerIdx, ids] of layers) {\n    const xStart = layerStartMap.get(layerIdx)!;\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    let y = 40 + (maxColH - total) / 2;\n    for (const id of ids) {\n      const h = heightOf(id);\n      const g = gateGeoms.get(id);\n      let node: LogicLayoutNode;\n      if (layerIdx === 0) {\n        const inp = ast.inputs.find((i) => i.id === id)!;\n        node = {\n          id,\n          kind: \"input\",\n          x: xStart,\n          y,\n          layer: 0,\n          label: inp.label,\n          isActiveLow: inp.isActiveLow,\n        };\n      } else if (layerIdx === outputLayer && !g && id.startsWith(\"$out$\")) {\n        const out = portOutputs.find((o) => o.termId === id)!;\n        node = {\n          id,\n          kind: \"output\",\n          x: xStart,\n          y,\n          layer: outputLayer,\n          label: out.label,\n          isActiveLow: out.isActiveLow,\n        };\n      } else {\n        node = {\n          id,\n          kind: \"gate\",\n          x: xStart,\n          y,\n          layer: layerIdx,\n          geometry: g,\n          gateType: ast.gates.find((gg) => gg.id === id)!.gateType,\n          label: id,\n        };\n      }\n      nodes.push(node);\n      nodeInfo.set(id, node);\n      y += h + ROW_GAP;\n    }\n  }\n\n  // Wires\n  const wires: LogicLayoutWire[] = [];\n  const getSourcePoint = (id: string) => {\n    const n = nodeInfo.get(id);\n    if (!n) return null;\n    if (n.kind === \"input\") return { x: n.x + PORT_SIZE, y: n.y + PORT_H / 2 };\n    if (n.kind === \"gate\" && n.geometry) {\n      const out = n.geometry.outputPins[0];\n      return { x: n.x + out.x, y: n.y + out.y };\n    }\n    return null;\n  };\n\n  for (const g of ast.gates) {\n    const target = nodeInfo.get(g.id);\n    if (!target || !target.geometry) continue;\n    g.inputs.forEach((rawInp, idx) => {\n      const isLow = rawInp.startsWith(\"~\");\n      const srcId = isLow ? rawInp.slice(1) : rawInp;\n      const src = getSourcePoint(srcId);\n      if (!src) return;\n      const pin = target.geometry!.inputPins[idx];\n      if (!pin) return;\n      const toX = target.x + pin.x;\n      const toY = target.y + pin.y;\n      const midX = (src.x + toX) / 2;\n      const path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n      wires.push({\n        fromNode: srcId,\n        fromX: src.x,\n        fromY: src.y,\n        toNode: g.id,\n        toX,\n        toY,\n        isActiveLow: isLow,\n        path,\n      });\n    });\n  }\n\n  // Output port wires\n  for (const o of portOutputs) {\n    const src = getSourcePoint(o.source);\n    const target = nodeInfo.get(o.termId);\n    if (!src || !target || target.kind !== \"output\") continue;\n    const toX = target.x;\n    const toY = target.y + PORT_H / 2;\n    let path: string;\n    if (Math.abs(src.y - toY) < 0.5) {\n      path = `M ${src.x},${src.y} L ${toX},${toY}`;\n    } else {\n      const midX = (src.x + toX) / 2;\n      path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n    }\n    wires.push({\n      fromNode: o.source,\n      fromX: src.x,\n      fromY: src.y,\n      toNode: o.termId,\n      toX,\n      toY,\n      path,\n    });\n  }\n\n  // Module bounding boxes (dashed enclosure for sub-circuits)\n  const modules: LogicLayoutModule[] = [];\n  if (ast.modules && ast.modules.length > 0) {\n    const PAD = 14;\n    for (const mod of ast.modules) {\n      const memberIds = new Set(\n        ast.gates.filter((g) => g.moduleId === mod.id).map((g) => g.id)\n      );\n      if (memberIds.size === 0) continue;\n      let minX = Infinity, minY = Infinity, maxX = -Infinity, maxY = -Infinity;\n      for (const n of nodes) {\n        if (!memberIds.has(n.id)) continue;\n        const w = n.geometry?.width ?? 60;\n        const h = n.geometry?.height ?? 60;\n        if (n.x < minX) minX = n.x;\n        if (n.y < minY) minY = n.y;\n        if (n.x + w > maxX) maxX = n.x + w;\n        if (n.y + h > maxY) maxY = n.y + h;\n      }\n      if (!isFinite(minX)) continue;\n      modules.push({\n        id: mod.id,\n        label: mod.label,\n        x: minX - PAD,\n        y: minY - PAD - 4,\n        width: maxX - minX + PAD * 2,\n        height: maxY - minY + PAD * 2 + 4,\n      });\n    }\n  }\n\n  return { width: totalW, height: totalH, nodes, wires, modules };\n}\n","import type { LogicGateAST, LogicGateStyle, RenderConfig } from \"../../core/types\";\nimport { layoutLogic } from \"./layout\";\nimport {\n  svgRoot,\n  defs,\n  group,\n  el,\n  circle,\n  path as pathEl,\n  text,\n  title as titleEl,\n  desc,\n  polygon,\n} from \"../../core/svg\";\nimport { resolveIndustrialTheme } from \"../../core/theme\";\n\nconst PORT_SIZE = 40;\nconst PORT_H = 30;\n\nfunction renderGateBody(\n  n: ReturnType<typeof layoutLogic>[\"nodes\"][number],\n  style: LogicGateStyle\n): string[] {\n  const out: string[] = [];\n  if (!n.geometry) return out;\n  const g = n.geometry;\n\n  if (style === \"iec\") {\n    // Rectangle\n    out.push(\n      el(\"rect\", {\n        x: 0,\n        y: 0,\n        width: g.width,\n        height: g.height,\n        class: \"schematex-logic-gate-body\",\n      })\n    );\n    if (g.iecLabel) {\n      out.push(\n        text(\n          {\n            x: g.width / 2,\n            y: g.height / 2 + 4,\n            class: \"schematex-logic-gate-iec-label\",\n            \"text-anchor\": \"middle\",\n          },\n          g.iecLabel\n        )\n      );\n    }\n  } else {\n    out.push(\n      el(\"path\", { d: g.ansiPath, class: \"schematex-logic-gate-body\" })\n    );\n  }\n\n  // Output bubble\n  if (g.outputBubble) {\n    const op = g.outputPins[0];\n    out.push(\n      circle({\n        cx: op.x - 4,\n        cy: op.y,\n        r: 4,\n        class: \"schematex-logic-bubble\",\n      })\n    );\n  }\n\n  // Clock triangle\n  if (g.clockPin) {\n    const cp = g.inputPins.find((p) => p.id === g.clockPin);\n    if (cp) {\n      out.push(\n        polygon({\n          points: `${cp.x},${cp.y - 5} ${cp.x + 8},${cp.y} ${cp.x},${cp.y + 5}`,\n          class: \"schematex-logic-clock-tri\",\n        })\n      );\n    }\n  }\n\n  // Qn bubble (sequential)\n  for (const op of g.outputPins) {\n    if (op.bubble && op.id !== \"out\") {\n      out.push(\n        circle({\n          cx: op.x + 4,\n          cy: op.y,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n  }\n\n  // Pin labels\n  for (const pin of g.inputPins) {\n    if (pin.label && pin.id !== g.clockPin) {\n      out.push(\n        text(\n          {\n            x: pin.x + 5,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n  for (const pin of g.outputPins) {\n    if (pin.label) {\n      out.push(\n        text(\n          {\n            x: pin.x - 6,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n            \"text-anchor\": \"end\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n\n  // Gate type label (center top, small)\n  if (style === \"ansi\" && g.iecLabel && g.height >= 60) {\n    const labelX = g.width / 2;\n    const labelY = g.height + 14;\n    out.push(\n      text(\n        {\n          x: labelX,\n          y: labelY,\n          class: \"schematex-logic-gate-type\",\n          \"text-anchor\": \"middle\",\n        },\n        n.gateType ?? \"\"\n      )\n    );\n  }\n\n  return out;\n}\n\nexport function renderLogic(ast: LogicGateAST, config?: RenderConfig): string {\n  const style: LogicGateStyle = ast.style ?? \"ansi\";\n  const layout = layoutLogic(ast);\n  const { width, height } = layout;\n  const t = resolveIndustrialTheme(config?.theme ?? \"default\");\n\n  const gateSvgs: string[] = [];\n  const portSvgs: string[] = [];\n  const moduleSvgs: string[] = [];\n\n  for (const m of layout.modules) {\n    moduleSvgs.push(\n      group({ \"data-module-id\": m.id }, [\n        el(\"rect\", {\n          x: m.x,\n          y: m.y,\n          width: m.width,\n          height: m.height,\n          rx: 6,\n          class: \"schematex-logic-module\",\n        }),\n        text(\n          {\n            x: m.x + 10,\n            y: m.y + 14,\n            class: \"schematex-logic-module-label\",\n          },\n          m.label\n        ),\n      ])\n    );\n  }\n\n  for (const n of layout.nodes) {\n    if (n.kind === \"gate\") {\n      gateSvgs.push(\n        group(\n          {\n            transform: `translate(${n.x}, ${n.y})`,\n            \"data-gate-id\": n.id,\n            \"data-gate-type\": n.gateType ?? \"\",\n          },\n          renderGateBody(n, style)\n        )\n      );\n    } else if (n.kind === \"input\") {\n      // Label + short stub line; no rectangle.\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"input\" }, [\n          text(\n            {\n              x: 0,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n          el(\"line\", {\n            x1: PORT_SIZE - 12,\n            y1: cy,\n            x2: n.isActiveLow ? PORT_SIZE - 8 : PORT_SIZE,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          n.isActiveLow\n            ? circle({\n                cx: PORT_SIZE - 4,\n                cy,\n                r: 4,\n                class: \"schematex-logic-bubble\",\n              })\n            : \"\",\n        ])\n      );\n    } else if (n.kind === \"output\") {\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"output\" }, [\n          el(\"line\", {\n            x1: 0,\n            y1: cy,\n            x2: 12,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          text(\n            {\n              x: 16,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n        ])\n      );\n    }\n  }\n\n  const wireSvgs = layout.wires.map((w) => {\n    const extras: string[] = [];\n    if (w.isActiveLow) {\n      extras.push(\n        circle({\n          cx: w.toX - 4,\n          cy: w.toY,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n    return [\n      pathEl({\n        d: w.path,\n        class: \"schematex-logic-wire\",\n        \"data-from\": w.fromNode,\n        \"data-to\": w.toNode,\n      }),\n      ...extras,\n    ].join(\"\");\n  });\n\n  const css = `\n.schematex-logic { background: ${t.bg}; font-family: system-ui, -apple-system, sans-serif; }\n.schematex-logic-gate-body { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.75; stroke-linejoin: round; }\n.schematex-logic-bubble { fill: ${t.bg}; stroke: ${t.strokeHeavy}; stroke-width: 1.5; }\n.schematex-logic-clock-tri { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.5; stroke-linejoin: round; }\n.schematex-logic-wire { stroke: ${t.strokeHeavy}; stroke-width: 1.5; fill: none; stroke-linecap: square; }\n.schematex-logic-port-label { font: 13px system-ui, sans-serif; fill: ${t.text}; }\n.schematex-logic-pin-label { font: 9px sans-serif; fill: ${t.stroke}; }\n.schematex-logic-gate-type { font: 10px sans-serif; fill: ${t.textMuted}; }\n.schematex-logic-gate-iec-label { font: bold 13px sans-serif; fill: ${t.text}; }\n.schematex-logic-title { font: bold 14px sans-serif; fill: ${t.text}; }\n.schematex-logic-module { fill: none; stroke: ${t.textMuted}; stroke-width: 1.25; stroke-dasharray: 6 4; }\n.schematex-logic-module-label { font: 11px sans-serif; fill: ${t.textMuted}; font-style: italic; }\n`.trim();\n\n  const titleSvg = ast.title\n    ? text(\n        {\n          x: width / 2,\n          y: 18,\n          \"text-anchor\": \"middle\",\n          class: \"schematex-logic-title\",\n        },\n        ast.title\n      )\n    : \"\";\n\n  return svgRoot(\n    {\n      class: \"schematex-logic\",\n      viewBox: `0 0 ${width} ${height + (ast.title ? 20 : 0)}`,\n      width,\n      height: height + (ast.title ? 20 : 0),\n      role: \"img\",\n      \"data-diagram-type\": \"logic\",\n    },\n    [\n      titleEl(ast.title ?? \"Logic Gate Diagram\"),\n      desc(\n        `Logic gate diagram with ${ast.gates.length} gates, ${ast.inputs.length} inputs, ${ast.outputs.length} outputs`\n      ),\n      defs([el(\"style\", {}, css)]),\n      group(\n        { transform: `translate(0, ${ast.title ? 20 : 0})` },\n        [\n          group({ class: \"schematex-logic-modules\" }, moduleSvgs),\n          group({ class: \"schematex-logic-wires\" }, wireSvgs),\n          group({ class: \"schematex-logic-gates\" }, gateSvgs),\n          group({ class: \"schematex-logic-ports\" }, portSvgs),\n        ]\n      ),\n      titleSvg,\n    ]\n  );\n}\n","import type { DiagramPlugin } from \"../../core/types\";\nimport { parseLogic } from \"./parser\";\nimport { renderLogic } from \"./renderer\";\n\nexport const logic: DiagramPlugin = {\n  type: \"logic\",\n  detect(text: string): boolean {\n    const first = text.trim().split(\"\\n\")[0]?.trim().toLowerCase() ?? \"\";\n    return first.startsWith(\"logic\");\n  },\n  parse: parseLogic,\n\n  render(text: string, config): string {\n    const ast = parseLogic(text);\n    return renderLogic(ast, config);\n  },\n};\n\nexport { parseLogic } from \"./parser\";\nexport { renderLogic } from \"./renderer\";\nexport { layoutLogic } from \"./layout\";\n"]}
+{"version":3,"sources":["../src/diagrams/logic/parser.ts","../src/diagrams/logic/symbols.ts","../src/diagrams/logic/layout.ts","../src/diagrams/logic/renderer.ts","../src/diagrams/logic/index.ts"],"names":["text","title","path","PORT_SIZE","PORT_H"],"mappings":";;;;AAUO,IAAM,eAAA,GAAN,cAA8B,KAAA,CAAM;AAAA,EACzC,YAAY,OAAA,EAAiB;AAC3B,IAAA,KAAA,CAAM,OAAO,CAAA;AACb,IAAA,IAAA,CAAK,IAAA,GAAO,iBAAA;AAAA,EACd;AACF,CAAA;AAEA,IAAM,UAAA,uBAAiB,GAAA,CAAY;AAAA,EACjC,KAAA;AAAA,EAAO,IAAA;AAAA,EAAM,KAAA;AAAA,EAAO,MAAA;AAAA,EAAQ,KAAA;AAAA,EAAO,KAAA;AAAA,EAAO,MAAA;AAAA,EAAQ,KAAA;AAAA,EAClD,cAAA;AAAA,EAAgB,cAAA;AAAA,EAAgB,YAAA;AAAA,EAAc,SAAA;AAAA,EAC9C,KAAA;AAAA,EAAO,MAAA;AAAA,EAAQ,MAAA;AAAA,EAAQ,KAAA;AAAA,EAAO,UAAA;AAAA,EAAY,SAAA;AAAA,EAC1C,KAAA;AAAA,EAAO,OAAA;AAAA,EAAS,SAAA;AAAA,EAAW,SAAA;AAAA,EAAW,SAAA;AAAA,EAAW;AACnD,CAAC,CAAA;AAED,SAAS,SAAS,CAAA,EAAqB;AACrC,EAAA,OAAO,CAAA,CACJ,KAAA,CAAM,GAAG,CAAA,CACT,GAAA,CAAI,CAAC,CAAA,KAAM,CAAA,CAAE,IAAA,EAAM,CAAA,CACnB,MAAA,CAAO,OAAO,CAAA;AACnB;AAEA,SAAS,eAAe,CAAA,EAAqB;AAE3C,EAAA,OAAO,EACJ,KAAA,CAAM,GAAG,CAAA,CACT,GAAA,CAAI,CAAC,CAAA,KAAM,CAAA,CAAE,IAAA,EAAM,EACnB,MAAA,CAAO,OAAO,CAAA,CACd,GAAA,CAAI,CAAC,GAAA,KAAQ;AACZ,IAAA,MAAM,EAAA,GAAK,GAAA,CAAI,OAAA,CAAQ,GAAG,CAAA;AAC1B,IAAA,OAAO,EAAA,IAAM,IAAI,GAAA,CAAI,KAAA,CAAM,KAAK,CAAC,CAAA,CAAE,MAAK,GAAI,GAAA;AAAA,EAC9C,CAAC,CAAA;AACL;AAEO,SAAS,WAAWA,KAAAA,EAA4B;AACrD,EAAA,MAAM,KAAA,GAAQA,KAAAA,CAAK,KAAA,CAAM,IAAI,EAAE,GAAA,CAAI,CAAC,CAAA,KAAM,CAAA,CAAE,OAAA,CAAQ,KAAA,EAAO,EAAE,CAAA,CAAE,MAAM,CAAA;AACrE,EAAA,IAAIC,MAAAA;AACJ,EAAA,IAAI,KAAA;AACJ,EAAA,MAAM,SAA2B,EAAC;AAClC,EAAA,MAAM,UAA6B,EAAC;AACpC,EAAA,MAAM,QAAyB,EAAC;AAChC,EAAA,MAAM,UAA6B,EAAC;AACpC,EAAA,MAAM,cAAwB,EAAC;AAC/B,EAAA,IAAI,aAAA,GAAgB,CAAA;AACpB,EAAA,MAAM,kBAAA,uBAAyB,GAAA,EAAoB;AAEnD,EAAA,KAAA,MAAW,WAAW,KAAA,EAAO;AAE3B,IAAA,MAAM,IAAA,GAAO,OAAA,CAAQ,OAAA,CAAQ,MAAA,EAAQ,EAAE,EAAE,OAAA,CAAQ,OAAA,EAAS,EAAE,CAAA,CAAE,IAAA,EAAK;AACnE,IAAA,IAAI,CAAC,IAAA,EAAM;AAGX,IAAA,MAAM,OAAA,GAAU,IAAA,CAAK,KAAA,CAAM,gDAAgD,CAAA;AAC3E,IAAA,IAAI,OAAA,EAAS;AACX,MAAA,MAAM,KAAA,GAAQ,OAAA,CAAQ,CAAC,CAAA,IAAK,QAAQ,CAAC,CAAA;AACrC,MAAA,MAAM,EAAA,GAAK,OAAO,aAAA,EAAe,CAAA,CAAA;AACjC,MAAA,OAAA,CAAQ,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA;AAC1B,MAAA,WAAA,CAAY,KAAK,EAAE,CAAA;AACnB,MAAA;AAAA,IACF;AAGA,IAAA,IAAI,SAAS,GAAA,EAAK;AAChB,MAAA,IAAI,WAAA,CAAY,WAAW,CAAA,EAAG;AAC5B,QAAA,MAAM,IAAI,gBAAgB,qCAAgC,CAAA;AAAA,MAC5D;AACA,MAAA,WAAA,CAAY,GAAA,EAAI;AAChB,MAAA;AAAA,IACF;AAGA,IAAA,IAAI,WAAA,CAAY,IAAA,CAAK,IAAI,CAAA,EAAG;AAC1B,MAAA,MAAM,CAAA,GAAI,IAAA,CAAK,KAAA,CAAM,WAAW,CAAA;AAChC,MAAA,IAAI,CAAA,EAAGA,MAAAA,GAAQ,CAAA,CAAE,CAAC,CAAA;AAClB,MAAA,MAAM,CAAA,GAAI,IAAA,CAAK,KAAA,CAAM,yBAAyB,CAAA;AAC9C,MAAA,IAAI,CAAA,EAAG,KAAA,GAAQ,CAAA,CAAE,CAAC,EAAE,WAAA,EAAY;AAChC,MAAA;AAAA,IACF;AAGA,IAAA,MAAM,UAAA,GAAa,IAAA,CAAK,KAAA,CAAM,iBAAiB,CAAA;AAC/C,IAAA,IAAI,UAAA,EAAY;AACd,MAAA,KAAA,MAAW,EAAA,IAAM,QAAA,CAAS,UAAA,CAAW,CAAC,CAAC,CAAA,EAAG;AACxC,QAAA,MAAM,KAAA,GAAQ,EAAA,CAAG,UAAA,CAAW,GAAG,CAAA;AAC/B,QAAA,MAAM,KAAA,GAAQ,KAAA,GAAQ,EAAA,CAAG,KAAA,CAAM,CAAC,CAAA,GAAI,EAAA;AACpC,QAAA,MAAA,CAAO,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,OAAO,KAAA,EAAO,WAAA,EAAa,KAAA,IAAS,MAAA,EAAW,CAAA;AAAA,MAC1E;AACA,MAAA;AAAA,IACF;AAGA,IAAA,MAAM,WAAA,GAAc,IAAA,CAAK,KAAA,CAAM,kBAAkB,CAAA;AACjD,IAAA,IAAI,WAAA,EAAa;AACf,MAAA,KAAA,MAAW,EAAA,IAAM,QAAA,CAAS,WAAA,CAAY,CAAC,CAAC,CAAA,EAAG;AACzC,QAAA,OAAA,CAAQ,KAAK,EAAE,EAAA,EAAI,OAAO,EAAA,EAAI,IAAA,EAAM,IAAI,CAAA;AAAA,MAC1C;AACA,MAAA;AAAA,IACF;AAGA,IAAA,MAAM,WAAA,GAAc,IAAA,CAAK,KAAA,CAAM,4CAA4C,CAAA;AAC3E,IAAA,IAAI,WAAA,EAAa;AACf,MAAA,kBAAA,CAAmB,IAAI,WAAA,CAAY,CAAC,CAAA,EAAG,WAAA,CAAY,CAAC,CAAC,CAAA;AACrD,MAAA;AAAA,IACF;AAGA,IAAA,MAAM,SAAA,GAAY,IAAA,CAAK,KAAA,CAAM,yDAAyD,CAAA;AACtF,IAAA,IAAI,SAAA,EAAW;AACb,MAAA,MAAM,EAAA,GAAK,UAAU,CAAC,CAAA;AACtB,MAAA,MAAM,OAAA,GAAU,SAAA,CAAU,CAAC,CAAA,CAAE,WAAA,EAAY;AACzC,MAAA,IAAI,CAAC,UAAA,CAAW,GAAA,CAAI,OAAO,CAAA,EAAG;AAC5B,QAAA,MAAM,IAAI,eAAA,CAAgB,CAAA,mBAAA,EAAsB,OAAO,CAAA,CAAE,CAAA;AAAA,MAC3D;AACA,MAAA,MAAM,OAAA,GAAU,cAAA,CAAe,SAAA,CAAU,CAAC,CAAC,CAAA;AAC3C,MAAA,MAAM,QAAA,GAAW,WAAA,CAAY,WAAA,CAAY,MAAA,GAAS,CAAC,CAAA;AACnD,MAAA,KAAA,CAAM,IAAA,CAAK,EAAE,EAAA,EAAI,QAAA,EAAU,SAA0B,MAAA,EAAQ,OAAA,EAAS,UAAU,CAAA;AAChF,MAAA;AAAA,IACF;AAAA,EACF;AAEA,EAAA,IAAI,WAAA,CAAY,SAAS,CAAA,EAAG;AAC1B,IAAA,MAAM,IAAI,eAAA,CAAgB,CAAA,iBAAA,EAAoB,WAAA,CAAY,MAAM,CAAA,MAAA,CAAQ,CAAA;AAAA,EAC1E;AAGA,EAAA,KAAA,MAAW,OAAO,OAAA,EAAS;AACzB,IAAA,MAAM,MAAA,GAAS,kBAAA,CAAmB,GAAA,CAAI,GAAA,CAAI,EAAE,CAAA;AAC5C,IAAA,IAAI,MAAA,MAAY,IAAA,GAAO,MAAA;AAAA,SAAA,IACd,KAAA,CAAM,IAAA,CAAK,CAAC,CAAA,KAAM,CAAA,CAAE,EAAA,KAAO,GAAA,CAAI,EAAE,CAAA,EAAG,GAAA,CAAI,IAAA,GAAO,GAAA,CAAI,EAAA;AAAA,EAC9D;AAGA,EAAA,MAAM,KAAA,uBAAY,GAAA,CAAY;AAAA,IAC5B,GAAG,MAAA,CAAO,GAAA,CAAI,CAAC,CAAA,KAAM,EAAE,EAAE,CAAA;AAAA,IACzB,GAAG,KAAA,CAAM,GAAA,CAAI,CAAC,CAAA,KAAM,EAAE,EAAE;AAAA,GACzB,CAAA;AACD,EAAA,KAAA,MAAW,KAAK,KAAA,EAAO;AACrB,IAAA,KAAA,MAAW,GAAA,IAAO,EAAE,MAAA,EAAQ;AAC1B,MAAA,MAAM,KAAA,GAAQ,IAAI,UAAA,CAAW,GAAG,IAAI,GAAA,CAAI,KAAA,CAAM,CAAC,CAAA,GAAI,GAAA;AACnD,MAAA,IAAI,CAAC,KAAA,CAAM,GAAA,CAAI,KAAK,CAAA,EAAG;AACrB,QAAA,MAAM,IAAI,eAAA,CAAgB,CAAA,gBAAA,EAAmB,KAAK,CAAA,UAAA,EAAa,CAAA,CAAE,EAAE,CAAA,CAAE,CAAA;AAAA,MACvE;AAAA,IACF;AAAA,EACF;AAEA,EAAA,OAAO;AAAA,IACL,IAAA,EAAM,OAAA;AAAA,IACN,KAAA,EAAAA,MAAAA;AAAA,IACA,OAAO,KAAA,IAAS,MAAA;AAAA,IAChB,MAAA;AAAA,IACA,OAAA;AAAA,IACA,KAAA;AAAA,IACA,OAAA,EAAS,OAAA,CAAQ,MAAA,GAAS,CAAA,GAAI,OAAA,GAAU;AAAA,GAC1C;AACF;;;AClJA,SAAS,QAAA,CAAS,OAAA,EAAiB,MAAA,EAAgB,KAAA,EAA4D;AAC7G,EAAA,MAAM,OAAoD,EAAC;AAC3D,EAAA,IAAI,YAAY,CAAA,EAAG;AACjB,IAAA,IAAA,CAAK,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,GAAG,KAAA,EAAO,CAAA,EAAG,IAAI,CAAA;AAAA,EAC1C,CAAA,MAAA,IAAW,YAAY,CAAA,EAAG;AACxB,IAAA,IAAA,CAAK,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,GAAG,KAAA,EAAO,CAAA,EAAG,IAAI,CAAA;AACxC,IAAA,IAAA,CAAK,IAAA,CAAK,EAAE,EAAA,EAAI,KAAA,EAAO,GAAG,KAAA,EAAO,CAAA,EAAG,IAAI,CAAA;AAAA,EAC1C,CAAA,MAAO;AACL,IAAA,MAAM,IAAA,GAAO,MAAM,OAAA,GAAU,CAAA,CAAA;AAC7B,IAAA,KAAA,IAAS,CAAA,GAAI,CAAA,EAAG,CAAA,GAAI,OAAA,EAAS,CAAA,EAAA,EAAK;AAChC,MAAA,IAAA,CAAK,IAAA,CAAK,EAAE,EAAA,EAAI,CAAA,EAAA,EAAK,CAAA,GAAI,CAAC,CAAA,CAAA,EAAI,CAAA,EAAG,KAAA,EAAO,CAAA,EAAG,CAAA,GAAI,IAAA,GAAO,GAAG,CAAA;AAAA,IAC3D;AAAA,EACF;AACA,EAAA,OAAO,IAAA;AACT;AAEO,SAAS,eAAA,CACd,UACA,UAAA,EACc;AACd,EAAA,QAAQ,QAAA;AAAU,IAChB,KAAK,KAAA;AAAA,IACL,KAAK,MAAA,EAAQ;AACX,MAAA,MAAM,SAAS,QAAA,KAAa,MAAA;AAC5B,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,SAAS,EAAA,GAAK,EAAA;AAAA,QACrB,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,QAAA,CAAS,UAAA,EAAY,EAAA,EAAI,EAAE,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,MAAO,EAAE,GAAG,CAAA,EAAG,CAAA,EAAG,IAAG,CAAE,CAAA;AAAA,QACpE,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,MAAA,GAAS,EAAA,GAAK,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,CAAA;AAAA,QAC9D,QAAA,EAAU,6CAAA;AAAA,QACV,YAAA,EAAc,MAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,IAAA;AAAA,IACL,KAAK,KAAA,EAAO;AACV,MAAA,MAAM,SAAS,QAAA,KAAa,KAAA;AAC5B,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,SAAS,EAAA,GAAK,EAAA;AAAA,QACrB,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,QAAA,CAAS,UAAA,EAAY,EAAA,EAAI,EAAE,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,MAAO,EAAE,GAAG,CAAA,EAAG,CAAA,EAAG,IAAG,CAAE,CAAA;AAAA,QACpE,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,MAAA,GAAS,EAAA,GAAK,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,CAAA;AAAA,QAC9D,QAAA,EAAU,oDAAA;AAAA,QACV,YAAA,EAAc,MAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA;AAAA,IACL,KAAK,MAAA,EAAQ;AACX,MAAA,MAAM,SAAS,QAAA,KAAa,MAAA;AAC5B,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,SAAS,EAAA,GAAK,EAAA;AAAA,QACrB,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,QAAA,CAAS,UAAA,EAAY,EAAA,EAAI,EAAE,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,MAAO,EAAE,GAAG,CAAA,EAAG,CAAA,EAAG,IAAG,CAAE,CAAA;AAAA,QACpE,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,MAAA,GAAS,EAAA,GAAK,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,CAAA;AAAA,QAC9D,QAAA,EACE,sEAAA;AAAA,QACF,YAAA,EAAc,MAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA,EAAO;AACV,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,CAAC,EAAE,EAAA,EAAI,OAAO,CAAA,EAAG,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,CAAA;AAAA,QACvC,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,IAAA,EAAM,CAAA;AAAA,QACtD,QAAA,EAAU,0BAAA;AAAA,QACV,YAAA,EAAc,IAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA;AAAA,IACL,KAAK,SAAA,EAAW;AACd,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW,CAAC,EAAE,EAAA,EAAI,OAAO,CAAA,EAAG,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,CAAA;AAAA,QACvC,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,OAAO,CAAA,EAAG,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,CAAA;AAAA,QACxC,QAAA,EAAU,0BAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,cAAA;AAAA,IACL,KAAK,cAAA;AAAA,IACL,KAAK,YAAA,EAAc;AACjB,MAAA,MAAM,SAAS,QAAA,KAAa,cAAA;AAC5B,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,SAAS,EAAA,GAAK,EAAA;AAAA,QACrB,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAG;AAAA,UAC1B,EAAE,IAAI,IAAA,EAAM,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,IAAA;AAAK,SACxC;AAAA,QACA,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,MAAA,GAAS,EAAA,GAAK,EAAA,EAAI,CAAA,EAAG,EAAA,EAAI,MAAA,EAAQ,CAAA;AAAA,QAC9D,QAAA,EAAU,0BAAA;AAAA,QACV,YAAA,EAAc,MAAA;AAAA,QACd,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA,EAAO;AACV,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,IAAI,KAAA,EAAO,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,EAAA;AAAG,SACtC;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU,KAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,MAAA,EAAQ;AACX,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,CAAA,EAAG,GAAG,EAAA,EAAG;AAAA,UACzB,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA;AAAI,SACrC;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU,KAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,MAAA;AAAA,IACL,KAAK,UAAA,EAAY;AACf,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA;AAAI,SACrC;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,KAAA,EAAO;AACV,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,EAAA,EAAI,KAAA,EAAO,CAAA,EAAG,CAAA,EAAG,GAAG,EAAA;AAAG,SAC3B;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU,KAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,KAAK,SAAA,EAAW;AACd,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,EAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA,EAAW;AAAA,UACT,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACnC,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,GAAG,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA;AAAI,SACrC;AAAA,QACA,UAAA,EAAY;AAAA,UACV,EAAE,IAAI,GAAA,EAAK,CAAA,EAAG,IAAI,CAAA,EAAG,EAAA,EAAI,OAAO,GAAA,EAAI;AAAA,UACpC,EAAE,EAAA,EAAI,IAAA,EAAM,CAAA,EAAG,EAAA,EAAI,GAAG,EAAA,EAAI,KAAA,EAAO,SAAA,EAAM,MAAA,EAAQ,IAAA;AAAK,SACtD;AAAA,QACA,QAAA,EAAU,uBAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA,IACA,SAAS;AAEP,MAAA,MAAM,GAAA,GAAM,IAAA,CAAK,GAAA,CAAI,UAAA,EAAY,CAAC,CAAA;AAClC,MAAA,MAAM,SAAA,GAAY,SAAS,GAAA,EAAK,GAAA,EAAK,CAAC,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,EAAG,CAAA,MAAO;AAAA,QACrD,GAAG,CAAA;AAAA,QACH,CAAA,EAAG,CAAA;AAAA,QACH,KAAA,EAAO,IAAI,CAAC,CAAA;AAAA,OACd,CAAE,CAAA;AACF,MAAA,OAAO;AAAA,QACL,KAAA,EAAO,GAAA;AAAA,QACP,MAAA,EAAQ,EAAA;AAAA,QACR,SAAA;AAAA,QACA,UAAA,EAAY,CAAC,EAAE,EAAA,EAAI,OAAO,CAAA,EAAG,GAAA,EAAK,CAAA,EAAG,EAAA,EAAI,CAAA;AAAA,QACzC,QAAA,EAAU,wBAAA;AAAA,QACV,QAAA,EAAU;AAAA,OACZ;AAAA,IACF;AAAA;AAEJ;;;AClLA,IAAM,SAAA,GAAY,EAAA;AAClB,IAAM,OAAA,GAAU,EAAA;AAChB,IAAM,SAAA,GAAY,EAAA;AAClB,IAAM,MAAA,GAAS,EAAA;AAER,SAAS,YAAY,GAAA,EAAsC;AAEhE,EAAA,MAAM,OAAA,uBAAc,GAAA,EAAoB;AACxC,EAAA,KAAA,MAAW,OAAO,GAAA,CAAI,MAAA,UAAgB,GAAA,CAAI,GAAA,CAAI,IAAI,CAAC,CAAA;AAGnD,EAAA,MAAM,OAAA,GAAU,IAAI,GAAA,CAAI,GAAA,CAAI,KAAA,CAAM,IAAI,CAAC,CAAA,KAAM,CAAA,CAAE,EAAE,CAAC,CAAA;AAClD,EAAA,IAAI,MAAA,GAAS,CAAA;AACb,EAAA,OAAO,OAAA,CAAQ,IAAA,GAAO,CAAA,IAAK,MAAA,EAAA,GAAW,GAAA,EAAM;AAC1C,IAAA,KAAA,MAAW,CAAA,IAAK,IAAI,KAAA,EAAO;AACzB,MAAA,IAAI,CAAC,OAAA,CAAQ,GAAA,CAAI,CAAA,CAAE,EAAE,CAAA,EAAG;AACxB,MAAA,IAAI,MAAA,GAAS,EAAA;AACb,MAAA,IAAI,KAAA,GAAQ,IAAA;AACZ,MAAA,KAAA,MAAW,GAAA,IAAO,EAAE,MAAA,EAAQ;AAC1B,QAAA,MAAM,KAAA,GAAQ,IAAI,UAAA,CAAW,GAAG,IAAI,GAAA,CAAI,KAAA,CAAM,CAAC,CAAA,GAAI,GAAA;AACnD,QAAA,MAAM,CAAA,GAAI,OAAA,CAAQ,GAAA,CAAI,KAAK,CAAA;AAC3B,QAAA,IAAI,MAAM,MAAA,EAAW;AACnB,UAAA,KAAA,GAAQ,KAAA;AACR,UAAA;AAAA,QACF;AACA,QAAA,IAAI,CAAA,GAAI,QAAQ,MAAA,GAAS,CAAA;AAAA,MAC3B;AACA,MAAA,IAAI,KAAA,EAAO;AACT,QAAA,OAAA,CAAQ,GAAA,CAAI,CAAA,CAAE,EAAA,EAAI,MAAA,GAAS,CAAC,CAAA;AAC5B,QAAA,OAAA,CAAQ,MAAA,CAAO,EAAE,EAAE,CAAA;AAAA,MACrB;AAAA,IACF;AAAA,EACF;AACA,EAAA,IAAI,OAAA,CAAQ,OAAO,CAAA,EAAG;AAEpB,IAAA,KAAA,MAAW,EAAA,IAAM,OAAA,EAAS,OAAA,CAAQ,GAAA,CAAI,IAAI,CAAC,CAAA;AAAA,EAC7C;AAEA,EAAA,MAAM,WAAA,GACJ,IAAA,CAAK,GAAA,CAAI,CAAA,EAAG,GAAG,KAAA,CAAM,IAAA,CAAK,OAAA,CAAQ,MAAA,EAAQ,CAAC,CAAA,GAAI,CAAA;AAGjD,EAAA,MAAM,SAAA,GAAY,CAAC,CAAA,KAAsB,CAAA,KAAA,EAAQ,EAAE,EAAE,CAAA,CAAA;AACrD,EAAA,MAAM,WAAA,GAAc,GAAA,CAAI,OAAA,CAAQ,GAAA,CAAI,CAAC,CAAA,MAAO;AAAA,IAC1C,GAAG,CAAA;AAAA,IACH,MAAA,EAAQ,UAAU,CAAC,CAAA;AAAA,IACnB,QAAQ,CAAA,CAAE;AAAA,GACZ,CAAE,CAAA;AACF,EAAA,KAAA,MAAW,KAAK,WAAA,EAAa,OAAA,CAAQ,GAAA,CAAI,CAAA,CAAE,QAAQ,WAAW,CAAA;AAG9D,EAAA,MAAM,MAAA,uBAAa,GAAA,EAAsB;AACzC,EAAA,MAAM,UAAA,GAAa,CAAC,EAAA,EAAY,KAAA,KAAkB;AAChD,IAAA,IAAI,CAAC,OAAO,GAAA,CAAI,KAAK,GAAG,MAAA,CAAO,GAAA,CAAI,KAAA,EAAO,EAAE,CAAA;AAC5C,IAAA,MAAA,CAAO,GAAA,CAAI,KAAK,CAAA,CAAG,IAAA,CAAK,EAAE,CAAA;AAAA,EAC5B,CAAA;AACA,EAAA,KAAA,MAAW,KAAK,GAAA,CAAI,MAAA,EAAQ,UAAA,CAAW,CAAA,CAAE,IAAI,CAAC,CAAA;AAC9C,EAAA,KAAA,MAAW,CAAA,IAAK,GAAA,CAAI,KAAA,EAAO,UAAA,CAAW,CAAA,CAAE,IAAI,OAAA,CAAQ,GAAA,CAAI,CAAA,CAAE,EAAE,CAAE,CAAA;AAC9D,EAAA,KAAA,MAAW,CAAA,IAAK,WAAA,EAAa,UAAA,CAAW,CAAA,CAAE,QAAQ,WAAW,CAAA;AAG7D,EAAA,MAAM,SAAA,uBAAgB,GAAA,EAA0B;AAChD,EAAA,KAAA,MAAW,CAAA,IAAK,IAAI,KAAA,EAAO;AACzB,IAAA,SAAA,CAAU,GAAA,CAAI,EAAE,EAAA,EAAI,eAAA,CAAgB,EAAE,QAAA,EAAU,CAAA,CAAE,MAAA,CAAO,MAAM,CAAC,CAAA;AAAA,EAClE;AAGA,EAAA,MAAM,QAA2B,EAAC;AAClC,EAAA,MAAM,YAAA,GAAe,KAAA,CAAM,IAAA,CAAK,MAAA,CAAO,IAAA,EAAM,CAAA,CAAE,IAAA,CAAK,CAAC,CAAA,EAAG,CAAA,KAAM,CAAA,GAAI,CAAC,CAAA;AAGnE,EAAA,MAAM,UAAA,uBAAiB,GAAA,EAAoB;AAC3C,EAAA,KAAA,MAAW,CAAC,QAAA,EAAU,GAAG,CAAA,IAAK,MAAA,EAAQ;AACpC,IAAA,IAAI,IAAA,GAAO,EAAA;AACX,IAAA,KAAA,MAAW,MAAM,GAAA,EAAK;AACpB,MAAA,MAAM,CAAA,GAAI,SAAA,CAAU,GAAA,CAAI,EAAE,CAAA;AAC1B,MAAA,IAAI,CAAA,IAAK,CAAA,CAAE,KAAA,GAAQ,IAAA,SAAa,CAAA,CAAE,KAAA;AAClC,MAAA,IAAI,CAAC,KAAK,QAAA,KAAa,CAAA,SAAU,IAAA,CAAK,GAAA,CAAI,MAAM,SAAS,CAAA;AACzD,MAAA,IAAI,CAAC,KAAK,QAAA,KAAa,WAAA,SAAoB,IAAA,CAAK,GAAA,CAAI,MAAM,SAAS,CAAA;AAAA,IACrE;AACA,IAAA,UAAA,CAAW,GAAA,CAAI,UAAU,IAAI,CAAA;AAAA,EAC/B;AAEA,EAAA,IAAI,OAAA,GAAU,EAAA;AACd,EAAA,MAAM,aAAA,uBAAoB,GAAA,EAAoB;AAC9C,EAAA,KAAA,MAAW,YAAY,YAAA,EAAc;AACnC,IAAA,aAAA,CAAc,GAAA,CAAI,UAAU,OAAO,CAAA;AACnC,IAAA,OAAA,IAAA,CAAY,UAAA,CAAW,GAAA,CAAI,QAAQ,CAAA,IAAK,EAAA,IAAM,SAAA;AAAA,EAChD;AACA,EAAA,MAAM,MAAA,GAAS,OAAA;AAGf,EAAA,MAAM,QAAA,GAAW,CAAC,EAAA,KAAuB;AACvC,IAAA,MAAM,CAAA,GAAI,SAAA,CAAU,GAAA,CAAI,EAAE,CAAA;AAC1B,IAAA,IAAI,CAAA,SAAU,CAAA,CAAE,MAAA;AAChB,IAAA,OAAO,MAAA;AAAA,EACT,CAAA;AAGA,EAAA,IAAI,OAAA,GAAU,CAAA;AACd,EAAA,KAAA,MAAW,GAAA,IAAO,MAAA,CAAO,MAAA,EAAO,EAAG;AACjC,IAAA,MAAM,KAAA,GAAQ,GAAA,CAAI,MAAA,CAAO,CAAC,GAAG,EAAA,KAAO,CAAA,GAAI,QAAA,CAAS,EAAE,CAAA,EAAG,CAAC,CAAA,GAAA,CAAK,GAAA,CAAI,SAAS,CAAA,IAAK,OAAA;AAC9E,IAAA,IAAI,KAAA,GAAQ,SAAS,OAAA,GAAU,KAAA;AAAA,EACjC;AACA,EAAA,MAAM,SAAS,OAAA,GAAU,EAAA;AAEzB,EAAA,MAAM,QAAA,uBAAe,GAAA,EAA6B;AAClD,EAAA,KAAA,MAAW,CAAC,QAAA,EAAU,GAAG,CAAA,IAAK,MAAA,EAAQ;AACpC,IAAA,MAAM,MAAA,GAAS,aAAA,CAAc,GAAA,CAAI,QAAQ,CAAA;AACzC,IAAA,MAAM,KAAA,GAAQ,GAAA,CAAI,MAAA,CAAO,CAAC,GAAG,EAAA,KAAO,CAAA,GAAI,QAAA,CAAS,EAAE,CAAA,EAAG,CAAC,CAAA,GAAA,CAAK,GAAA,CAAI,SAAS,CAAA,IAAK,OAAA;AAC9E,IAAA,IAAI,CAAA,GAAI,EAAA,GAAA,CAAM,OAAA,GAAU,KAAA,IAAS,CAAA;AACjC,IAAA,KAAA,MAAW,MAAM,GAAA,EAAK;AACpB,MAAA,MAAM,CAAA,GAAI,SAAS,EAAE,CAAA;AACrB,MAAA,MAAM,CAAA,GAAI,SAAA,CAAU,GAAA,CAAI,EAAE,CAAA;AAC1B,MAAA,IAAI,IAAA;AACJ,MAAA,IAAI,aAAa,CAAA,EAAG;AAClB,QAAA,MAAM,GAAA,GAAM,IAAI,MAAA,CAAO,IAAA,CAAK,CAAC,CAAA,KAAM,CAAA,CAAE,OAAO,EAAE,CAAA;AAC9C,QAAA,IAAA,GAAO;AAAA,UACL,EAAA;AAAA,UACA,IAAA,EAAM,OAAA;AAAA,UACN,CAAA,EAAG,MAAA;AAAA,UACH,CAAA;AAAA,UACA,KAAA,EAAO,CAAA;AAAA,UACP,OAAO,GAAA,CAAI,KAAA;AAAA,UACX,aAAa,GAAA,CAAI;AAAA,SACnB;AAAA,MACF,CAAA,MAAA,IAAW,aAAa,WAAA,IAAe,CAAC,KAAK,EAAA,CAAG,UAAA,CAAW,OAAO,CAAA,EAAG;AACnE,QAAA,MAAM,MAAM,WAAA,CAAY,IAAA,CAAK,CAAC,CAAA,KAAM,CAAA,CAAE,WAAW,EAAE,CAAA;AACnD,QAAA,IAAA,GAAO;AAAA,UACL,EAAA;AAAA,UACA,IAAA,EAAM,QAAA;AAAA,UACN,CAAA,EAAG,MAAA;AAAA,UACH,CAAA;AAAA,UACA,KAAA,EAAO,WAAA;AAAA,UACP,OAAO,GAAA,CAAI,KAAA;AAAA,UACX,aAAa,GAAA,CAAI;AAAA,SACnB;AAAA,MACF,CAAA,MAAO;AACL,QAAA,IAAA,GAAO;AAAA,UACL,EAAA;AAAA,UACA,IAAA,EAAM,MAAA;AAAA,UACN,CAAA,EAAG,MAAA;AAAA,UACH,CAAA;AAAA,UACA,KAAA,EAAO,QAAA;AAAA,UACP,QAAA,EAAU,CAAA;AAAA,UACV,QAAA,EAAU,IAAI,KAAA,CAAM,IAAA,CAAK,CAAC,EAAA,KAAO,EAAA,CAAG,EAAA,KAAO,EAAE,CAAA,CAAG,QAAA;AAAA,UAChD,KAAA,EAAO;AAAA,SACT;AAAA,MACF;AACA,MAAA,KAAA,CAAM,KAAK,IAAI,CAAA;AACf,MAAA,QAAA,CAAS,GAAA,CAAI,IAAI,IAAI,CAAA;AACrB,MAAA,CAAA,IAAK,CAAA,GAAI,OAAA;AAAA,IACX;AAAA,EACF;AAGA,EAAA,MAAM,QAA2B,EAAC;AAClC,EAAA,MAAM,cAAA,GAAiB,CAAC,EAAA,KAAe;AACrC,IAAA,MAAM,CAAA,GAAI,QAAA,CAAS,GAAA,CAAI,EAAE,CAAA;AACzB,IAAA,IAAI,CAAC,GAAG,OAAO,IAAA;AACf,IAAA,IAAI,CAAA,CAAE,IAAA,KAAS,OAAA,EAAS,OAAO,EAAE,CAAA,EAAG,CAAA,CAAE,CAAA,GAAI,SAAA,EAAW,CAAA,EAAG,CAAA,CAAE,CAAA,GAAI,SAAS,CAAA,EAAE;AACzE,IAAA,IAAI,CAAA,CAAE,IAAA,KAAS,MAAA,IAAU,CAAA,CAAE,QAAA,EAAU;AACnC,MAAA,MAAM,GAAA,GAAM,CAAA,CAAE,QAAA,CAAS,UAAA,CAAW,CAAC,CAAA;AACnC,MAAA,OAAO,EAAE,CAAA,EAAG,CAAA,CAAE,CAAA,GAAI,GAAA,CAAI,GAAG,CAAA,EAAG,CAAA,CAAE,CAAA,GAAI,GAAA,CAAI,CAAA,EAAE;AAAA,IAC1C;AACA,IAAA,OAAO,IAAA;AAAA,EACT,CAAA;AAEA,EAAA,KAAA,MAAW,CAAA,IAAK,IAAI,KAAA,EAAO;AACzB,IAAA,MAAM,MAAA,GAAS,QAAA,CAAS,GAAA,CAAI,CAAA,CAAE,EAAE,CAAA;AAChC,IAAA,IAAI,CAAC,MAAA,IAAU,CAAC,MAAA,CAAO,QAAA,EAAU;AACjC,IAAA,CAAA,CAAE,MAAA,CAAO,OAAA,CAAQ,CAAC,MAAA,EAAQ,GAAA,KAAQ;AAChC,MAAA,MAAM,KAAA,GAAQ,MAAA,CAAO,UAAA,CAAW,GAAG,CAAA;AACnC,MAAA,MAAM,KAAA,GAAQ,KAAA,GAAQ,MAAA,CAAO,KAAA,CAAM,CAAC,CAAA,GAAI,MAAA;AACxC,MAAA,MAAM,GAAA,GAAM,eAAe,KAAK,CAAA;AAChC,MAAA,IAAI,CAAC,GAAA,EAAK;AACV,MAAA,MAAM,GAAA,GAAM,MAAA,CAAO,QAAA,CAAU,SAAA,CAAU,GAAG,CAAA;AAC1C,MAAA,IAAI,CAAC,GAAA,EAAK;AACV,MAAA,MAAM,GAAA,GAAM,MAAA,CAAO,CAAA,GAAI,GAAA,CAAI,CAAA;AAC3B,MAAA,MAAM,GAAA,GAAM,MAAA,CAAO,CAAA,GAAI,GAAA,CAAI,CAAA;AAC3B,MAAA,MAAM,IAAA,GAAA,CAAQ,GAAA,CAAI,CAAA,GAAI,GAAA,IAAO,CAAA;AAC7B,MAAA,MAAMC,QAAO,CAAA,EAAA,EAAK,GAAA,CAAI,CAAC,CAAA,CAAA,EAAI,GAAA,CAAI,CAAC,CAAA,GAAA,EAAM,IAAI,IAAI,GAAA,CAAI,CAAC,MAAM,IAAI,CAAA,CAAA,EAAI,GAAG,CAAA,GAAA,EAAM,GAAG,IAAI,GAAG,CAAA,CAAA;AACpF,MAAA,KAAA,CAAM,IAAA,CAAK;AAAA,QACT,QAAA,EAAU,KAAA;AAAA,QACV,OAAO,GAAA,CAAI,CAAA;AAAA,QACX,OAAO,GAAA,CAAI,CAAA;AAAA,QACX,QAAQ,CAAA,CAAE,EAAA;AAAA,QACV,GAAA;AAAA,QACA,GAAA;AAAA,QACA,WAAA,EAAa,KAAA;AAAA,QACb,IAAA,EAAAA;AAAA,OACD,CAAA;AAAA,IACH,CAAC,CAAA;AAAA,EACH;AAGA,EAAA,KAAA,MAAW,KAAK,WAAA,EAAa;AAC3B,IAAA,MAAM,GAAA,GAAM,cAAA,CAAe,CAAA,CAAE,MAAM,CAAA;AACnC,IAAA,MAAM,MAAA,GAAS,QAAA,CAAS,GAAA,CAAI,CAAA,CAAE,MAAM,CAAA;AACpC,IAAA,IAAI,CAAC,GAAA,IAAO,CAAC,MAAA,IAAU,MAAA,CAAO,SAAS,QAAA,EAAU;AACjD,IAAA,MAAM,MAAM,MAAA,CAAO,CAAA;AACnB,IAAA,MAAM,GAAA,GAAM,MAAA,CAAO,CAAA,GAAI,MAAA,GAAS,CAAA;AAChC,IAAA,IAAIA,KAAAA;AACJ,IAAA,IAAI,KAAK,GAAA,CAAI,GAAA,CAAI,CAAA,GAAI,GAAG,IAAI,GAAA,EAAK;AAC/B,MAAAA,KAAAA,GAAO,CAAA,EAAA,EAAK,GAAA,CAAI,CAAC,CAAA,CAAA,EAAI,IAAI,CAAC,CAAA,GAAA,EAAM,GAAG,CAAA,CAAA,EAAI,GAAG,CAAA,CAAA;AAAA,IAC5C,CAAA,MAAO;AACL,MAAA,MAAM,IAAA,GAAA,CAAQ,GAAA,CAAI,CAAA,GAAI,GAAA,IAAO,CAAA;AAC7B,MAAAA,QAAO,CAAA,EAAA,EAAK,GAAA,CAAI,CAAC,CAAA,CAAA,EAAI,GAAA,CAAI,CAAC,CAAA,GAAA,EAAM,IAAI,IAAI,GAAA,CAAI,CAAC,MAAM,IAAI,CAAA,CAAA,EAAI,GAAG,CAAA,GAAA,EAAM,GAAG,IAAI,GAAG,CAAA,CAAA;AAAA,IAChF;AACA,IAAA,KAAA,CAAM,IAAA,CAAK;AAAA,MACT,UAAU,CAAA,CAAE,MAAA;AAAA,MACZ,OAAO,GAAA,CAAI,CAAA;AAAA,MACX,OAAO,GAAA,CAAI,CAAA;AAAA,MACX,QAAQ,CAAA,CAAE,MAAA;AAAA,MACV,GAAA;AAAA,MACA,GAAA;AAAA,MACA,IAAA,EAAAA;AAAA,KACD,CAAA;AAAA,EACH;AAGA,EAAA,MAAM,UAA+B,EAAC;AACtC,EAAA,IAAI,GAAA,CAAI,OAAA,IAAW,GAAA,CAAI,OAAA,CAAQ,SAAS,CAAA,EAAG;AACzC,IAAA,MAAM,GAAA,GAAM,EAAA;AACZ,IAAA,KAAA,MAAW,GAAA,IAAO,IAAI,OAAA,EAAS;AAC7B,MAAA,MAAM,YAAY,IAAI,GAAA;AAAA,QACpB,GAAA,CAAI,KAAA,CAAM,MAAA,CAAO,CAAC,MAAM,CAAA,CAAE,QAAA,KAAa,GAAA,CAAI,EAAE,CAAA,CAAE,GAAA,CAAI,CAAC,CAAA,KAAM,EAAE,EAAE;AAAA,OAChE;AACA,MAAA,IAAI,SAAA,CAAU,SAAS,CAAA,EAAG;AAC1B,MAAA,IAAI,OAAO,QAAA,EAAU,IAAA,GAAO,QAAA,EAAU,IAAA,GAAO,WAAW,IAAA,GAAO,CAAA,QAAA;AAC/D,MAAA,KAAA,MAAW,KAAK,KAAA,EAAO;AACrB,QAAA,IAAI,CAAC,SAAA,CAAU,GAAA,CAAI,CAAA,CAAE,EAAE,CAAA,EAAG;AAC1B,QAAA,MAAM,CAAA,GAAI,CAAA,CAAE,QAAA,EAAU,KAAA,IAAS,EAAA;AAC/B,QAAA,MAAM,CAAA,GAAI,CAAA,CAAE,QAAA,EAAU,MAAA,IAAU,EAAA;AAChC,QAAA,IAAI,CAAA,CAAE,CAAA,GAAI,IAAA,EAAM,IAAA,GAAO,CAAA,CAAE,CAAA;AACzB,QAAA,IAAI,CAAA,CAAE,CAAA,GAAI,IAAA,EAAM,IAAA,GAAO,CAAA,CAAE,CAAA;AACzB,QAAA,IAAI,EAAE,CAAA,GAAI,CAAA,GAAI,IAAA,EAAM,IAAA,GAAO,EAAE,CAAA,GAAI,CAAA;AACjC,QAAA,IAAI,EAAE,CAAA,GAAI,CAAA,GAAI,IAAA,EAAM,IAAA,GAAO,EAAE,CAAA,GAAI,CAAA;AAAA,MACnC;AACA,MAAA,IAAI,CAAC,QAAA,CAAS,IAAI,CAAA,EAAG;AACrB,MAAA,OAAA,CAAQ,IAAA,CAAK;AAAA,QACX,IAAI,GAAA,CAAI,EAAA;AAAA,QACR,OAAO,GAAA,CAAI,KAAA;AAAA,QACX,GAAG,IAAA,GAAO,GAAA;AAAA,QACV,CAAA,EAAG,OAAO,GAAA,GAAM,CAAA;AAAA,QAChB,KAAA,EAAO,IAAA,GAAO,IAAA,GAAO,GAAA,GAAM,CAAA;AAAA,QAC3B,MAAA,EAAQ,IAAA,GAAO,IAAA,GAAO,GAAA,GAAM,CAAA,GAAI;AAAA,OACjC,CAAA;AAAA,IACH;AAAA,EACF;AAEA,EAAA,OAAO,EAAE,KAAA,EAAO,MAAA,EAAQ,QAAQ,MAAA,EAAQ,KAAA,EAAO,OAAO,OAAA,EAAQ;AAChE;;;ACvRA,IAAMC,UAAAA,GAAY,EAAA;AAClB,IAAMC,OAAAA,GAAS,EAAA;AAEf,SAAS,cAAA,CACP,GACA,KAAA,EACU;AACV,EAAA,MAAM,MAAgB,EAAC;AACvB,EAAA,IAAI,CAAC,CAAA,CAAE,QAAA,EAAU,OAAO,GAAA;AACxB,EAAA,MAAM,IAAI,CAAA,CAAE,QAAA;AAEZ,EAAA,IAAI,UAAU,KAAA,EAAO;AAEnB,IAAA,GAAA,CAAI,IAAA;AAAA,MACF,GAAG,MAAA,EAAQ;AAAA,QACT,CAAA,EAAG,CAAA;AAAA,QACH,CAAA,EAAG,CAAA;AAAA,QACH,OAAO,CAAA,CAAE,KAAA;AAAA,QACT,QAAQ,CAAA,CAAE,MAAA;AAAA,QACV,KAAA,EAAO;AAAA,OACR;AAAA,KACH;AACA,IAAA,IAAI,EAAE,QAAA,EAAU;AACd,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,IAAA;AAAA,UACE;AAAA,YACE,CAAA,EAAG,EAAE,KAAA,GAAQ,CAAA;AAAA,YACb,CAAA,EAAG,CAAA,CAAE,MAAA,GAAS,CAAA,GAAI,CAAA;AAAA,YAClB,KAAA,EAAO,gCAAA;AAAA,YACP,aAAA,EAAe;AAAA,WACjB;AAAA,UACA,CAAA,CAAE;AAAA;AACJ,OACF;AAAA,IACF;AAAA,EACF,CAAA,MAAO;AACL,IAAA,GAAA,CAAI,IAAA;AAAA,MACF,EAAA,CAAG,QAAQ,EAAE,CAAA,EAAG,EAAE,QAAA,EAAU,KAAA,EAAO,6BAA6B;AAAA,KAClE;AAAA,EACF;AAGA,EAAA,IAAI,EAAE,YAAA,EAAc;AAClB,IAAA,MAAM,EAAA,GAAK,CAAA,CAAE,UAAA,CAAW,CAAC,CAAA;AACzB,IAAA,GAAA,CAAI,IAAA;AAAA,MACF,MAAA,CAAO;AAAA,QACL,EAAA,EAAI,GAAG,CAAA,GAAI,CAAA;AAAA,QACX,IAAI,EAAA,CAAG,CAAA;AAAA,QACP,CAAA,EAAG,CAAA;AAAA,QACH,KAAA,EAAO;AAAA,OACR;AAAA,KACH;AAAA,EACF;AAGA,EAAA,IAAI,EAAE,QAAA,EAAU;AACd,IAAA,MAAM,EAAA,GAAK,EAAE,SAAA,CAAU,IAAA,CAAK,CAAC,CAAA,KAAM,CAAA,CAAE,EAAA,KAAO,CAAA,CAAE,QAAQ,CAAA;AACtD,IAAA,IAAI,EAAA,EAAI;AACN,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,OAAA,CAAQ;AAAA,UACN,MAAA,EAAQ,GAAG,EAAA,CAAG,CAAC,IAAI,EAAA,CAAG,CAAA,GAAI,CAAC,CAAA,CAAA,EAAI,EAAA,CAAG,IAAI,CAAC,CAAA,CAAA,EAAI,GAAG,CAAC,CAAA,CAAA,EAAI,GAAG,CAAC,CAAA,CAAA,EAAI,EAAA,CAAG,CAAA,GAAI,CAAC,CAAA,CAAA;AAAA,UACnE,KAAA,EAAO;AAAA,SACR;AAAA,OACH;AAAA,IACF;AAAA,EACF;AAGA,EAAA,KAAA,MAAW,EAAA,IAAM,EAAE,UAAA,EAAY;AAC7B,IAAA,IAAI,EAAA,CAAG,MAAA,IAAU,EAAA,CAAG,EAAA,KAAO,KAAA,EAAO;AAChC,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,MAAA,CAAO;AAAA,UACL,EAAA,EAAI,GAAG,CAAA,GAAI,CAAA;AAAA,UACX,IAAI,EAAA,CAAG,CAAA;AAAA,UACP,CAAA,EAAG,CAAA;AAAA,UACH,KAAA,EAAO;AAAA,SACR;AAAA,OACH;AAAA,IACF;AAAA,EACF;AAGA,EAAA,KAAA,MAAW,GAAA,IAAO,EAAE,SAAA,EAAW;AAC7B,IAAA,IAAI,GAAA,CAAI,KAAA,IAAS,GAAA,CAAI,EAAA,KAAO,EAAE,QAAA,EAAU;AACtC,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,IAAA;AAAA,UACE;AAAA,YACE,CAAA,EAAG,IAAI,CAAA,GAAI,CAAA;AAAA,YACX,CAAA,EAAG,IAAI,CAAA,GAAI,CAAA;AAAA,YACX,KAAA,EAAO;AAAA,WACT;AAAA,UACA,GAAA,CAAI;AAAA;AACN,OACF;AAAA,IACF;AAAA,EACF;AACA,EAAA,KAAA,MAAW,GAAA,IAAO,EAAE,UAAA,EAAY;AAC9B,IAAA,IAAI,IAAI,KAAA,EAAO;AACb,MAAA,GAAA,CAAI,IAAA;AAAA,QACF,IAAA;AAAA,UACE;AAAA,YACE,CAAA,EAAG,IAAI,CAAA,GAAI,CAAA;AAAA,YACX,CAAA,EAAG,IAAI,CAAA,GAAI,CAAA;AAAA,YACX,KAAA,EAAO,2BAAA;AAAA,YACP,aAAA,EAAe;AAAA,WACjB;AAAA,UACA,GAAA,CAAI;AAAA;AACN,OACF;AAAA,IACF;AAAA,EACF;AAGA,EAAA,IAAI,UAAU,MAAA,IAAU,CAAA,CAAE,QAAA,IAAY,CAAA,CAAE,UAAU,EAAA,EAAI;AACpD,IAAA,MAAM,MAAA,GAAS,EAAE,KAAA,GAAQ,CAAA;AACzB,IAAA,MAAM,MAAA,GAAS,EAAE,MAAA,GAAS,EAAA;AAC1B,IAAA,GAAA,CAAI,IAAA;AAAA,MACF,IAAA;AAAA,QACE;AAAA,UACE,CAAA,EAAG,MAAA;AAAA,UACH,CAAA,EAAG,MAAA;AAAA,UACH,KAAA,EAAO,2BAAA;AAAA,UACP,aAAA,EAAe;AAAA,SACjB;AAAA,QACA,EAAE,QAAA,IAAY;AAAA;AAChB,KACF;AAAA,EACF;AAEA,EAAA,OAAO,GAAA;AACT;AAEO,SAAS,WAAA,CAAY,KAAmB,MAAA,EAA+B;AAC5E,EAAA,MAAM,KAAA,GAAwB,IAAI,KAAA,IAAS,MAAA;AAC3C,EAAA,MAAM,MAAA,GAAS,YAAY,GAAG,CAAA;AAC9B,EAAA,MAAM,EAAE,KAAA,EAAO,MAAA,EAAO,GAAI,MAAA;AAC1B,EAAA,MAAM,CAAA,GAAI,sBAAA,CAAuB,MAAA,EAAQ,KAAA,IAAS,SAAS,CAAA;AAE3D,EAAA,MAAM,WAAqB,EAAC;AAC5B,EAAA,MAAM,WAAqB,EAAC;AAC5B,EAAA,MAAM,aAAuB,EAAC;AAE9B,EAAA,KAAA,MAAW,CAAA,IAAK,OAAO,OAAA,EAAS;AAC9B,IAAA,UAAA,CAAW,IAAA;AAAA,MACT,KAAA,CAAM,EAAE,gBAAA,EAAkB,CAAA,CAAE,IAAG,EAAG;AAAA,QAChC,GAAG,MAAA,EAAQ;AAAA,UACT,GAAG,CAAA,CAAE,CAAA;AAAA,UACL,GAAG,CAAA,CAAE,CAAA;AAAA,UACL,OAAO,CAAA,CAAE,KAAA;AAAA,UACT,QAAQ,CAAA,CAAE,MAAA;AAAA,UACV,EAAA,EAAI,CAAA;AAAA,UACJ,KAAA,EAAO;AAAA,SACR,CAAA;AAAA,QACD,IAAA;AAAA,UACE;AAAA,YACE,CAAA,EAAG,EAAE,CAAA,GAAI,EAAA;AAAA,YACT,CAAA,EAAG,EAAE,CAAA,GAAI,EAAA;AAAA,YACT,KAAA,EAAO;AAAA,WACT;AAAA,UACA,CAAA,CAAE;AAAA;AACJ,OACD;AAAA,KACH;AAAA,EACF;AAEA,EAAA,KAAA,MAAW,CAAA,IAAK,OAAO,KAAA,EAAO;AAC5B,IAAA,IAAI,CAAA,CAAE,SAAS,MAAA,EAAQ;AACrB,MAAA,QAAA,CAAS,IAAA;AAAA,QACP,KAAA;AAAA,UACE;AAAA,YACE,WAAW,CAAA,UAAA,EAAa,CAAA,CAAE,CAAC,CAAA,EAAA,EAAK,EAAE,CAAC,CAAA,CAAA,CAAA;AAAA,YACnC,gBAAgB,CAAA,CAAE,EAAA;AAAA,YAClB,gBAAA,EAAkB,EAAE,QAAA,IAAY;AAAA,WAClC;AAAA,UACA,cAAA,CAAe,GAAG,KAAK;AAAA;AACzB,OACF;AAAA,IACF,CAAA,MAAA,IAAW,CAAA,CAAE,IAAA,KAAS,OAAA,EAAS;AAE7B,MAAA,MAAM,KAAKA,OAAAA,GAAS,CAAA;AACpB,MAAA,QAAA,CAAS,IAAA;AAAA,QACP,KAAA,CAAM,EAAE,SAAA,EAAW,CAAA,UAAA,EAAa,CAAA,CAAE,CAAC,CAAA,EAAA,EAAK,CAAA,CAAE,CAAC,CAAA,CAAA,CAAA,EAAK,WAAA,EAAa,OAAA,EAAQ,EAAG;AAAA,UACtE,IAAA;AAAA,YACE;AAAA,cACE,CAAA,EAAG,CAAA;AAAA,cACH,GAAG,EAAA,GAAK,CAAA;AAAA,cACR,aAAA,EAAe,OAAA;AAAA,cACf,KAAA,EAAO;AAAA,aACT;AAAA,YACA,CAAA,CAAE;AAAA,WACJ;AAAA,UACA,GAAG,MAAA,EAAQ;AAAA,YACT,IAAID,UAAAA,GAAY,EAAA;AAAA,YAChB,EAAA,EAAI,EAAA;AAAA,YACJ,EAAA,EAAI,CAAA,CAAE,WAAA,GAAcA,UAAAA,GAAY,CAAA,GAAIA,UAAAA;AAAA,YACpC,EAAA,EAAI,EAAA;AAAA,YACJ,KAAA,EAAO;AAAA,WACR,CAAA;AAAA,UACD,CAAA,CAAE,cACE,MAAA,CAAO;AAAA,YACL,IAAIA,UAAAA,GAAY,CAAA;AAAA,YAChB,EAAA;AAAA,YACA,CAAA,EAAG,CAAA;AAAA,YACH,KAAA,EAAO;AAAA,WACR,CAAA,GACD;AAAA,SACL;AAAA,OACH;AAAA,IACF,CAAA,MAAA,IAAW,CAAA,CAAE,IAAA,KAAS,QAAA,EAAU;AAC9B,MAAA,MAAM,KAAKC,OAAAA,GAAS,CAAA;AACpB,MAAA,QAAA,CAAS,IAAA;AAAA,QACP,KAAA,CAAM,EAAE,SAAA,EAAW,CAAA,UAAA,EAAa,CAAA,CAAE,CAAC,CAAA,EAAA,EAAK,CAAA,CAAE,CAAC,CAAA,CAAA,CAAA,EAAK,WAAA,EAAa,QAAA,EAAS,EAAG;AAAA,UACvE,GAAG,MAAA,EAAQ;AAAA,YACT,EAAA,EAAI,CAAA;AAAA,YACJ,EAAA,EAAI,EAAA;AAAA,YACJ,EAAA,EAAI,EAAA;AAAA,YACJ,EAAA,EAAI,EAAA;AAAA,YACJ,KAAA,EAAO;AAAA,WACR,CAAA;AAAA,UACD,IAAA;AAAA,YACE;AAAA,cACE,CAAA,EAAG,EAAA;AAAA,cACH,GAAG,EAAA,GAAK,CAAA;AAAA,cACR,aAAA,EAAe,OAAA;AAAA,cACf,KAAA,EAAO;AAAA,aACT;AAAA,YACA,CAAA,CAAE;AAAA;AACJ,SACD;AAAA,OACH;AAAA,IACF;AAAA,EACF;AAEA,EAAA,MAAM,QAAA,GAAW,MAAA,CAAO,KAAA,CAAM,GAAA,CAAI,CAAC,CAAA,KAAM;AACvC,IAAA,MAAM,SAAmB,EAAC;AAC1B,IAAA,IAAI,EAAE,WAAA,EAAa;AACjB,MAAA,MAAA,CAAO,IAAA;AAAA,QACL,MAAA,CAAO;AAAA,UACL,EAAA,EAAI,EAAE,GAAA,GAAM,CAAA;AAAA,UACZ,IAAI,CAAA,CAAE,GAAA;AAAA,UACN,CAAA,EAAG,CAAA;AAAA,UACH,KAAA,EAAO;AAAA,SACR;AAAA,OACH;AAAA,IACF;AACA,IAAA,OAAO;AAAA,MACL,IAAA,CAAO;AAAA,QACL,GAAG,CAAA,CAAE,IAAA;AAAA,QACL,KAAA,EAAO,sBAAA;AAAA,QACP,aAAa,CAAA,CAAE,QAAA;AAAA,QACf,WAAW,CAAA,CAAE;AAAA,OACd,CAAA;AAAA,MACD,GAAG;AAAA,KACL,CAAE,KAAK,EAAE,CAAA;AAAA,EACX,CAAC,CAAA;AAED,EAAA,MAAM,GAAA,GAAM;AAAA,+BAAA,EACmB,EAAE,EAAE,CAAA;AAAA,iDAAA,EACc,EAAE,WAAW,CAAA;AAAA,gCAAA,EAC9B,CAAA,CAAE,EAAE,CAAA,UAAA,EAAa,CAAA,CAAE,WAAW,CAAA;AAAA,iDAAA,EACb,EAAE,WAAW,CAAA;AAAA,gCAAA,EAC9B,EAAE,WAAW,CAAA;AAAA,sEAAA,EACyB,EAAE,IAAI,CAAA;AAAA,yDAAA,EACnB,EAAE,MAAM,CAAA;AAAA,0DAAA,EACP,EAAE,SAAS,CAAA;AAAA,oEAAA,EACD,EAAE,IAAI,CAAA;AAAA,2DAAA,EACf,EAAE,IAAI,CAAA;AAAA,8CAAA,EACnB,EAAE,SAAS,CAAA;AAAA,6DAAA,EACI,EAAE,SAAS,CAAA;AAAA,CAAA,CACxE,IAAA,EAAK;AAEL,EAAA,MAAM,QAAA,GAAW,IAAI,KAAA,GACjB,IAAA;AAAA,IACE;AAAA,MACE,GAAG,KAAA,GAAQ,CAAA;AAAA,MACX,CAAA,EAAG,EAAA;AAAA,MACH,aAAA,EAAe,QAAA;AAAA,MACf,KAAA,EAAO;AAAA,KACT;AAAA,IACA,GAAA,CAAI;AAAA,GACN,GACA,EAAA;AAEJ,EAAA,OAAO,OAAA;AAAA,IACL;AAAA,MACE,KAAA,EAAO,iBAAA;AAAA,MACP,OAAA,EAAS,OAAO,KAAK,CAAA,CAAA,EAAI,UAAU,GAAA,CAAI,KAAA,GAAQ,KAAK,CAAA,CAAE,CAAA,CAAA;AAAA,MACtD,KAAA;AAAA,MACA,MAAA,EAAQ,MAAA,IAAU,GAAA,CAAI,KAAA,GAAQ,EAAA,GAAK,CAAA,CAAA;AAAA,MACnC,IAAA,EAAM,KAAA;AAAA,MACN,mBAAA,EAAqB;AAAA,KACvB;AAAA,IACA;AAAA,MACE,KAAA,CAAQ,GAAA,CAAI,KAAA,IAAS,oBAAoB,CAAA;AAAA,MACzC,IAAA;AAAA,QACE,CAAA,wBAAA,EAA2B,GAAA,CAAI,KAAA,CAAM,MAAM,CAAA,QAAA,EAAW,GAAA,CAAI,MAAA,CAAO,MAAM,CAAA,SAAA,EAAY,GAAA,CAAI,OAAA,CAAQ,MAAM,CAAA,QAAA;AAAA,OACvG;AAAA,MACA,IAAA,CAAK,CAAC,EAAA,CAAG,OAAA,EAAS,EAAC,EAAG,GAAG,CAAC,CAAC,CAAA;AAAA,MAC3B,KAAA;AAAA,QACE,EAAE,SAAA,EAAW,CAAA,aAAA,EAAgB,IAAI,KAAA,GAAQ,EAAA,GAAK,CAAC,CAAA,CAAA,CAAA,EAAI;AAAA,QACnD;AAAA,UACE,KAAA,CAAM,EAAE,KAAA,EAAO,yBAAA,IAA6B,UAAU,CAAA;AAAA,UACtD,KAAA,CAAM,EAAE,KAAA,EAAO,uBAAA,IAA2B,QAAQ,CAAA;AAAA,UAClD,KAAA,CAAM,EAAE,KAAA,EAAO,uBAAA,IAA2B,QAAQ,CAAA;AAAA,UAClD,KAAA,CAAM,EAAE,KAAA,EAAO,uBAAA,IAA2B,QAAQ;AAAA;AACpD,OACF;AAAA,MACA;AAAA;AACF,GACF;AACF;;;AClUO,IAAM,KAAA,GAAuB;AAAA,EAClC,IAAA,EAAM,OAAA;AAAA,EACN,OAAOJ,KAAAA,EAAuB;AAC5B,IAAA,MAAM,KAAA,GAAQA,KAAAA,CAAK,IAAA,EAAK,CAAE,KAAA,CAAM,IAAI,CAAA,CAAE,CAAC,CAAA,EAAG,IAAA,EAAK,CAAE,WAAA,EAAY,IAAK,EAAA;AAClE,IAAA,OAAO,KAAA,CAAM,WAAW,OAAO,CAAA;AAAA,EACjC,CAAA;AAAA,EACA,KAAA,EAAO,UAAA;AAAA,EAEP,MAAA,CAAOA,OAAc,MAAA,EAAgB;AACnC,IAAA,MAAM,GAAA,GAAM,WAAWA,KAAI,CAAA;AAC3B,IAAA,OAAO,WAAA,CAAY,KAAK,MAAM,CAAA;AAAA,EAChC;AACF","file":"chunk-IQRRZPVZ.js","sourcesContent":["import type {\n  LogicGateAST,\n  LogicGateInput,\n  LogicGateOutput,\n  LogicGateNode,\n  LogicGateType,\n  LogicGateStyle,\n  LogicGateModule,\n} from \"../../core/types\";\n\nexport class LogicParseError extends Error {\n  constructor(message: string) {\n    super(message);\n    this.name = \"LogicParseError\";\n  }\n}\n\nconst GATE_TYPES = new Set<string>([\n  \"AND\", \"OR\", \"NOT\", \"NAND\", \"NOR\", \"XOR\", \"XNOR\", \"BUF\",\n  \"TRISTATE_BUF\", \"TRISTATE_INV\", \"OPEN_DRAIN\", \"SCHMITT\",\n  \"DFF\", \"JKFF\", \"SRFF\", \"TFF\", \"LATCH_SR\", \"LATCH_D\",\n  \"MUX\", \"DEMUX\", \"DECODER\", \"ENCODER\", \"COUNTER\", \"SHIFT_REG\",\n]);\n\nfunction splitIds(s: string): string[] {\n  return s\n    .split(\",\")\n    .map((x) => x.trim())\n    .filter(Boolean);\n}\n\nfunction parseInputList(s: string): string[] {\n  // Supports named (D=A) or positional. Returns raw tokens (keep ~ prefix for active-low).\n  return s\n    .split(\",\")\n    .map((x) => x.trim())\n    .filter(Boolean)\n    .map((tok) => {\n      const eq = tok.indexOf(\"=\");\n      return eq >= 0 ? tok.slice(eq + 1).trim() : tok;\n    });\n}\n\nexport function parseLogic(text: string): LogicGateAST {\n  const lines = text.split(\"\\n\").map((l) => l.replace(/\\r$/, \"\").trim());\n  let title: string | undefined;\n  let style: LogicGateStyle | undefined;\n  const inputs: LogicGateInput[] = [];\n  const outputs: LogicGateOutput[] = [];\n  const gates: LogicGateNode[] = [];\n  const modules: LogicGateModule[] = [];\n  const moduleStack: string[] = [];\n  let moduleCounter = 0;\n  const explicitOutputFrom = new Map<string, string>();\n\n  for (const rawLine of lines) {\n    // Strip line comments\n    const line = rawLine.replace(/#.*$/, \"\").replace(/--.*$/, \"\").trim();\n    if (!line) continue;\n\n    // module \"Label\" {   or  module Label {\n    const modOpen = line.match(/^module\\s+(?:\"([^\"]+)\"|([a-zA-Z_][\\w]*))\\s*\\{$/);\n    if (modOpen) {\n      const label = modOpen[1] ?? modOpen[2];\n      const id = `mod_${moduleCounter++}`;\n      modules.push({ id, label });\n      moduleStack.push(id);\n      continue;\n    }\n\n    // close module\n    if (line === \"}\") {\n      if (moduleStack.length === 0) {\n        throw new LogicParseError(\"Unmatched `}` — no open module\");\n      }\n      moduleStack.pop();\n      continue;\n    }\n\n    // Header\n    if (/^logic\\b/i.test(line)) {\n      const t = line.match(/\"([^\"]*)\"/);\n      if (t) title = t[1];\n      const s = line.match(/style\\s*:\\s*(ansi|iec)/i);\n      if (s) style = s[1].toLowerCase() as LogicGateStyle;\n      continue;\n    }\n\n    // input A, B, C\n    const inputMatch = line.match(/^input\\s+(.+)$/i);\n    if (inputMatch) {\n      for (const id of splitIds(inputMatch[1])) {\n        const isLow = id.startsWith(\"~\");\n        const clean = isLow ? id.slice(1) : id;\n        inputs.push({ id: clean, label: clean, isActiveLow: isLow || undefined });\n      }\n      continue;\n    }\n\n    // output X, Y\n    const outputMatch = line.match(/^output\\s+(.+)$/i);\n    if (outputMatch) {\n      for (const id of splitIds(outputMatch[1])) {\n        outputs.push({ id, label: id, from: id });\n      }\n      continue;\n    }\n\n    // OUTPUT <- GATE  (map output to gate)\n    const assignMatch = line.match(/^([a-zA-Z_][\\w]*)\\s*<-\\s*([a-zA-Z_][\\w]*)$/);\n    if (assignMatch) {\n      explicitOutputFrom.set(assignMatch[1], assignMatch[2]);\n      continue;\n    }\n\n    // Gate: ID = GATE(a, b, ...)\n    const gateMatch = line.match(/^([a-zA-Z_][\\w]*)\\s*=\\s*([A-Za-z_][\\w]*)\\s*\\(([^)]*)\\)$/);\n    if (gateMatch) {\n      const id = gateMatch[1];\n      const rawType = gateMatch[2].toUpperCase();\n      if (!GATE_TYPES.has(rawType)) {\n        throw new LogicParseError(`Unknown gate type: ${rawType}`);\n      }\n      const gInputs = parseInputList(gateMatch[3]);\n      const moduleId = moduleStack[moduleStack.length - 1];\n      gates.push({ id, gateType: rawType as LogicGateType, inputs: gInputs, moduleId });\n      continue;\n    }\n  }\n\n  if (moduleStack.length > 0) {\n    throw new LogicParseError(`Unclosed module (${moduleStack.length} open)`);\n  }\n\n  // Wire outputs: if output not explicitly mapped, look for gate with same id\n  for (const out of outputs) {\n    const mapped = explicitOutputFrom.get(out.id);\n    if (mapped) out.from = mapped;\n    else if (gates.some((g) => g.id === out.id)) out.from = out.id;\n  }\n\n  // Validate: undefined input references\n  const known = new Set<string>([\n    ...inputs.map((i) => i.id),\n    ...gates.map((g) => g.id),\n  ]);\n  for (const g of gates) {\n    for (const inp of g.inputs) {\n      const clean = inp.startsWith(\"~\") ? inp.slice(1) : inp;\n      if (!known.has(clean)) {\n        throw new LogicParseError(`Unknown signal \"${clean}\" in gate ${g.id}`);\n      }\n    }\n  }\n\n  return {\n    type: \"logic\",\n    title,\n    style: style ?? \"ansi\",\n    inputs,\n    outputs,\n    gates,\n    modules: modules.length > 0 ? modules : undefined,\n  };\n}\n","import type { LogicGateType } from \"../../core/types\";\n\n// Normalized gate geometry: combinational gates fit in 100×60; sequential in 60×80.\nexport interface GateGeometry {\n  width: number;\n  height: number;\n  inputPins: Array<{ id: string; x: number; y: number; label?: string }>;\n  outputPins: Array<{ id: string; x: number; y: number; label?: string; bubble?: boolean }>;\n  /** Body SVG path (ANSI) */\n  ansiPath: string;\n  /** Output bubble? */\n  outputBubble?: boolean;\n  /** Clock triangle pin id (sequential) */\n  clockPin?: string;\n  /** IEC label inside rectangle */\n  iecLabel?: string;\n}\n\nfunction combPins(nInputs: number, _width: number, leftX: number): Array<{ id: string; x: number; y: number }> {\n  const pins: Array<{ id: string; x: number; y: number }> = [];\n  if (nInputs === 1) {\n    pins.push({ id: \"in1\", x: leftX, y: 30 });\n  } else if (nInputs === 2) {\n    pins.push({ id: \"in1\", x: leftX, y: 15 });\n    pins.push({ id: \"in2\", x: leftX, y: 45 });\n  } else {\n    const step = 50 / (nInputs - 1);\n    for (let i = 0; i < nInputs; i++) {\n      pins.push({ id: `in${i + 1}`, x: leftX, y: 5 + step * i });\n    }\n  }\n  return pins;\n}\n\nexport function getGateGeometry(\n  gateType: LogicGateType,\n  inputCount: number\n): GateGeometry {\n  switch (gateType) {\n    case \"AND\":\n    case \"NAND\": {\n      const bubble = gateType === \"NAND\";\n      return {\n        width: bubble ? 90 : 80,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 20).map((p) => ({ ...p, x: 20 })),\n        outputPins: [{ id: \"out\", x: bubble ? 90 : 80, y: 30, bubble }],\n        ansiPath: \"M 20,60 L 20,0 Q 80,0 80,30 Q 80,60 20,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"&\",\n      };\n    }\n    case \"OR\":\n    case \"NOR\": {\n      const bubble = gateType === \"NOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 18).map((p) => ({ ...p, x: 18 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath: \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z\",\n        outputBubble: bubble,\n        iecLabel: \"≥1\",\n      };\n    }\n    case \"XOR\":\n    case \"XNOR\": {\n      const bubble = gateType === \"XNOR\";\n      return {\n        width: bubble ? 80 : 70,\n        height: 60,\n        inputPins: combPins(inputCount, 80, 12).map((p) => ({ ...p, x: 12 })),\n        outputPins: [{ id: \"out\", x: bubble ? 80 : 70, y: 30, bubble }],\n        ansiPath:\n          \"M 15,60 Q 10,30 15,0 Q 30,15 70,30 Q 30,45 15,60 Z M 8,60 Q 3,30 8,0\",\n        outputBubble: bubble,\n        iecLabel: \"=1\",\n      };\n    }\n    case \"NOT\": {\n      return {\n        width: 70,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 70, y: 30, bubble: true }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: true,\n        iecLabel: \"1\",\n      };\n    }\n    case \"BUF\":\n    case \"SCHMITT\": {\n      return {\n        width: 60,\n        height: 60,\n        inputPins: [{ id: \"in1\", x: 10, y: 30 }],\n        outputPins: [{ id: \"out\", x: 60, y: 30 }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        iecLabel: \"1\",\n      };\n    }\n    case \"TRISTATE_BUF\":\n    case \"TRISTATE_INV\":\n    case \"OPEN_DRAIN\": {\n      const bubble = gateType === \"TRISTATE_INV\";\n      return {\n        width: bubble ? 70 : 60,\n        height: 70,\n        inputPins: [\n          { id: \"in1\", x: 10, y: 30 },\n          { id: \"en\", x: 35, y: 65, label: \"EN\" },\n        ],\n        outputPins: [{ id: \"out\", x: bubble ? 70 : 60, y: 30, bubble }],\n        ansiPath: \"M 10,55 L 60,30 L 10,5 Z\",\n        outputBubble: bubble,\n        iecLabel: \"1\",\n      };\n    }\n    case \"DFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"CLK\", x: 0, y: 50, label: \"\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"DFF\",\n      };\n    }\n    case \"JKFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"J\", x: 0, y: 15, label: \"J\" },\n          { id: \"CLK\", x: 0, y: 40 },\n          { id: \"K\", x: 0, y: 65, label: \"K\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"JK\",\n      };\n    }\n    case \"SRFF\":\n    case \"LATCH_SR\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"S\", x: 0, y: 20, label: \"S\" },\n          { id: \"R\", x: 0, y: 60, label: \"R\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"SR\",\n      };\n    }\n    case \"TFF\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"T\", x: 0, y: 20, label: \"T\" },\n          { id: \"CLK\", x: 0, y: 50 },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        clockPin: \"CLK\",\n        iecLabel: \"T\",\n      };\n    }\n    case \"LATCH_D\": {\n      return {\n        width: 60,\n        height: 80,\n        inputPins: [\n          { id: \"D\", x: 0, y: 20, label: \"D\" },\n          { id: \"E\", x: 0, y: 60, label: \"E\" },\n        ],\n        outputPins: [\n          { id: \"Q\", x: 60, y: 20, label: \"Q\" },\n          { id: \"Qn\", x: 60, y: 60, label: \"Q̄\", bubble: true },\n        ],\n        ansiPath: \"M 0,0 H 60 V 80 H 0 Z\",\n        iecLabel: \"D\",\n      };\n    }\n    default: {\n      // Generic box for MUX/DEMUX/DECODER/ENCODER/COUNTER/SHIFT_REG\n      const ins = Math.max(inputCount, 2);\n      const inputPins = combPins(ins, 100, 0).map((p, i) => ({\n        ...p,\n        x: 0,\n        label: `I${i}`,\n      }));\n      return {\n        width: 100,\n        height: 80,\n        inputPins,\n        outputPins: [{ id: \"out\", x: 100, y: 40 }],\n        ansiPath: \"M 0,0 H 100 V 80 H 0 Z\",\n        iecLabel: gateType,\n      };\n    }\n  }\n}\n","import type { LogicGateAST } from \"../../core/types\";\nimport { getGateGeometry, type GateGeometry } from \"./symbols\";\n\nexport interface LogicLayoutNode {\n  id: string;\n  kind: \"input\" | \"gate\" | \"output\";\n  x: number;\n  y: number;\n  layer: number;\n  geometry?: GateGeometry;\n  gateType?: string;\n  label: string;\n  isActiveLow?: boolean;\n}\n\nexport interface LogicLayoutWire {\n  fromNode: string;\n  fromX: number;\n  fromY: number;\n  toNode: string;\n  toX: number;\n  toY: number;\n  isActiveLow?: boolean;\n  path: string;\n}\n\nexport interface LogicLayoutModule {\n  id: string;\n  label: string;\n  x: number;\n  y: number;\n  width: number;\n  height: number;\n}\n\nexport interface LogicLayoutResult {\n  width: number;\n  height: number;\n  nodes: LogicLayoutNode[];\n  wires: LogicLayoutWire[];\n  modules: LogicLayoutModule[];\n}\n\nconst LAYER_GAP = 80; // extra horizontal gap between layers\nconst ROW_GAP = 40;   // vertical gap between rows in same layer\nconst PORT_SIZE = 40; // input/output port pseudo-box width\nconst PORT_H = 30;\n\nexport function layoutLogic(ast: LogicGateAST): LogicLayoutResult {\n  // Determine layer per signal id using longest-path layering\n  const layerOf = new Map<string, number>();\n  for (const inp of ast.inputs) layerOf.set(inp.id, 0);\n\n  // Build dependency map for gates\n  const pending = new Set(ast.gates.map((g) => g.id));\n  let safety = 0;\n  while (pending.size > 0 && safety++ < 1000) {\n    for (const g of ast.gates) {\n      if (!pending.has(g.id)) continue;\n      let maxDep = -1;\n      let ready = true;\n      for (const inp of g.inputs) {\n        const clean = inp.startsWith(\"~\") ? inp.slice(1) : inp;\n        const l = layerOf.get(clean);\n        if (l === undefined) {\n          ready = false;\n          break;\n        }\n        if (l > maxDep) maxDep = l;\n      }\n      if (ready) {\n        layerOf.set(g.id, maxDep + 1);\n        pending.delete(g.id);\n      }\n    }\n  }\n  if (pending.size > 0) {\n    // cycle or unresolved: force layer 1\n    for (const id of pending) layerOf.set(id, 1);\n  }\n\n  const outputLayer =\n    Math.max(0, ...Array.from(layerOf.values())) + 1;\n  // All outputs get a terminal label node. Use synthetic id to avoid colliding\n  // with a gate that shares the output's name (e.g. `output Y; Y = AND(A,B)`).\n  const outTermId = (o: { id: string }) => `$out$${o.id}`;\n  const portOutputs = ast.outputs.map((o) => ({\n    ...o,\n    termId: outTermId(o),\n    source: o.from,\n  }));\n  for (const o of portOutputs) layerOf.set(o.termId, outputLayer);\n\n  // Group ids by layer\n  const layers = new Map<number, string[]>();\n  const addToLayer = (id: string, layer: number) => {\n    if (!layers.has(layer)) layers.set(layer, []);\n    layers.get(layer)!.push(id);\n  };\n  for (const i of ast.inputs) addToLayer(i.id, 0);\n  for (const g of ast.gates) addToLayer(g.id, layerOf.get(g.id)!);\n  for (const o of portOutputs) addToLayer(o.termId, outputLayer);\n\n  // Compute sizes per node (precompute geometries for gates)\n  const gateGeoms = new Map<string, GateGeometry>();\n  for (const g of ast.gates) {\n    gateGeoms.set(g.id, getGateGeometry(g.gateType, g.inputs.length));\n  }\n\n  // Assign coordinates\n  const nodes: LogicLayoutNode[] = [];\n  const sortedLayers = Array.from(layers.keys()).sort((a, b) => a - b);\n\n  // compute each layer's widest node\n  const layerWidth = new Map<number, number>();\n  for (const [layerIdx, ids] of layers) {\n    let maxW = 60;\n    for (const id of ids) {\n      const g = gateGeoms.get(id);\n      if (g && g.width > maxW) maxW = g.width;\n      if (!g && layerIdx === 0) maxW = Math.max(maxW, PORT_SIZE);\n      if (!g && layerIdx === outputLayer) maxW = Math.max(maxW, PORT_SIZE);\n    }\n    layerWidth.set(layerIdx, maxW);\n  }\n\n  let cursorX = 20;\n  const layerStartMap = new Map<number, number>();\n  for (const layerIdx of sortedLayers) {\n    layerStartMap.set(layerIdx, cursorX);\n    cursorX += (layerWidth.get(layerIdx) ?? 60) + LAYER_GAP;\n  }\n  const totalW = cursorX;\n\n  // Compute vertical placement per layer\n  const heightOf = (id: string): number => {\n    const g = gateGeoms.get(id);\n    if (g) return g.height;\n    return PORT_H;\n  };\n\n  // find max column height\n  let maxColH = 0;\n  for (const ids of layers.values()) {\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    if (total > maxColH) maxColH = total;\n  }\n  const totalH = maxColH + 80;\n\n  const nodeInfo = new Map<string, LogicLayoutNode>();\n  for (const [layerIdx, ids] of layers) {\n    const xStart = layerStartMap.get(layerIdx)!;\n    const total = ids.reduce((s, id) => s + heightOf(id), 0) + (ids.length - 1) * ROW_GAP;\n    let y = 40 + (maxColH - total) / 2;\n    for (const id of ids) {\n      const h = heightOf(id);\n      const g = gateGeoms.get(id);\n      let node: LogicLayoutNode;\n      if (layerIdx === 0) {\n        const inp = ast.inputs.find((i) => i.id === id)!;\n        node = {\n          id,\n          kind: \"input\",\n          x: xStart,\n          y,\n          layer: 0,\n          label: inp.label,\n          isActiveLow: inp.isActiveLow,\n        };\n      } else if (layerIdx === outputLayer && !g && id.startsWith(\"$out$\")) {\n        const out = portOutputs.find((o) => o.termId === id)!;\n        node = {\n          id,\n          kind: \"output\",\n          x: xStart,\n          y,\n          layer: outputLayer,\n          label: out.label,\n          isActiveLow: out.isActiveLow,\n        };\n      } else {\n        node = {\n          id,\n          kind: \"gate\",\n          x: xStart,\n          y,\n          layer: layerIdx,\n          geometry: g,\n          gateType: ast.gates.find((gg) => gg.id === id)!.gateType,\n          label: id,\n        };\n      }\n      nodes.push(node);\n      nodeInfo.set(id, node);\n      y += h + ROW_GAP;\n    }\n  }\n\n  // Wires\n  const wires: LogicLayoutWire[] = [];\n  const getSourcePoint = (id: string) => {\n    const n = nodeInfo.get(id);\n    if (!n) return null;\n    if (n.kind === \"input\") return { x: n.x + PORT_SIZE, y: n.y + PORT_H / 2 };\n    if (n.kind === \"gate\" && n.geometry) {\n      const out = n.geometry.outputPins[0];\n      return { x: n.x + out.x, y: n.y + out.y };\n    }\n    return null;\n  };\n\n  for (const g of ast.gates) {\n    const target = nodeInfo.get(g.id);\n    if (!target || !target.geometry) continue;\n    g.inputs.forEach((rawInp, idx) => {\n      const isLow = rawInp.startsWith(\"~\");\n      const srcId = isLow ? rawInp.slice(1) : rawInp;\n      const src = getSourcePoint(srcId);\n      if (!src) return;\n      const pin = target.geometry!.inputPins[idx];\n      if (!pin) return;\n      const toX = target.x + pin.x;\n      const toY = target.y + pin.y;\n      const midX = (src.x + toX) / 2;\n      const path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n      wires.push({\n        fromNode: srcId,\n        fromX: src.x,\n        fromY: src.y,\n        toNode: g.id,\n        toX,\n        toY,\n        isActiveLow: isLow,\n        path,\n      });\n    });\n  }\n\n  // Output port wires\n  for (const o of portOutputs) {\n    const src = getSourcePoint(o.source);\n    const target = nodeInfo.get(o.termId);\n    if (!src || !target || target.kind !== \"output\") continue;\n    const toX = target.x;\n    const toY = target.y + PORT_H / 2;\n    let path: string;\n    if (Math.abs(src.y - toY) < 0.5) {\n      path = `M ${src.x},${src.y} L ${toX},${toY}`;\n    } else {\n      const midX = (src.x + toX) / 2;\n      path = `M ${src.x},${src.y} L ${midX},${src.y} L ${midX},${toY} L ${toX},${toY}`;\n    }\n    wires.push({\n      fromNode: o.source,\n      fromX: src.x,\n      fromY: src.y,\n      toNode: o.termId,\n      toX,\n      toY,\n      path,\n    });\n  }\n\n  // Module bounding boxes (dashed enclosure for sub-circuits)\n  const modules: LogicLayoutModule[] = [];\n  if (ast.modules && ast.modules.length > 0) {\n    const PAD = 14;\n    for (const mod of ast.modules) {\n      const memberIds = new Set(\n        ast.gates.filter((g) => g.moduleId === mod.id).map((g) => g.id)\n      );\n      if (memberIds.size === 0) continue;\n      let minX = Infinity, minY = Infinity, maxX = -Infinity, maxY = -Infinity;\n      for (const n of nodes) {\n        if (!memberIds.has(n.id)) continue;\n        const w = n.geometry?.width ?? 60;\n        const h = n.geometry?.height ?? 60;\n        if (n.x < minX) minX = n.x;\n        if (n.y < minY) minY = n.y;\n        if (n.x + w > maxX) maxX = n.x + w;\n        if (n.y + h > maxY) maxY = n.y + h;\n      }\n      if (!isFinite(minX)) continue;\n      modules.push({\n        id: mod.id,\n        label: mod.label,\n        x: minX - PAD,\n        y: minY - PAD - 4,\n        width: maxX - minX + PAD * 2,\n        height: maxY - minY + PAD * 2 + 4,\n      });\n    }\n  }\n\n  return { width: totalW, height: totalH, nodes, wires, modules };\n}\n","import type { LogicGateAST, LogicGateStyle, RenderConfig } from \"../../core/types\";\nimport { layoutLogic } from \"./layout\";\nimport {\n  svgRoot,\n  defs,\n  group,\n  el,\n  circle,\n  path as pathEl,\n  text,\n  title as titleEl,\n  desc,\n  polygon,\n} from \"../../core/svg\";\nimport { resolveIndustrialTheme } from \"../../core/theme\";\n\nconst PORT_SIZE = 40;\nconst PORT_H = 30;\n\nfunction renderGateBody(\n  n: ReturnType<typeof layoutLogic>[\"nodes\"][number],\n  style: LogicGateStyle\n): string[] {\n  const out: string[] = [];\n  if (!n.geometry) return out;\n  const g = n.geometry;\n\n  if (style === \"iec\") {\n    // Rectangle\n    out.push(\n      el(\"rect\", {\n        x: 0,\n        y: 0,\n        width: g.width,\n        height: g.height,\n        class: \"schematex-logic-gate-body\",\n      })\n    );\n    if (g.iecLabel) {\n      out.push(\n        text(\n          {\n            x: g.width / 2,\n            y: g.height / 2 + 4,\n            class: \"schematex-logic-gate-iec-label\",\n            \"text-anchor\": \"middle\",\n          },\n          g.iecLabel\n        )\n      );\n    }\n  } else {\n    out.push(\n      el(\"path\", { d: g.ansiPath, class: \"schematex-logic-gate-body\" })\n    );\n  }\n\n  // Output bubble\n  if (g.outputBubble) {\n    const op = g.outputPins[0];\n    out.push(\n      circle({\n        cx: op.x - 4,\n        cy: op.y,\n        r: 4,\n        class: \"schematex-logic-bubble\",\n      })\n    );\n  }\n\n  // Clock triangle\n  if (g.clockPin) {\n    const cp = g.inputPins.find((p) => p.id === g.clockPin);\n    if (cp) {\n      out.push(\n        polygon({\n          points: `${cp.x},${cp.y - 5} ${cp.x + 8},${cp.y} ${cp.x},${cp.y + 5}`,\n          class: \"schematex-logic-clock-tri\",\n        })\n      );\n    }\n  }\n\n  // Qn bubble (sequential)\n  for (const op of g.outputPins) {\n    if (op.bubble && op.id !== \"out\") {\n      out.push(\n        circle({\n          cx: op.x + 4,\n          cy: op.y,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n  }\n\n  // Pin labels\n  for (const pin of g.inputPins) {\n    if (pin.label && pin.id !== g.clockPin) {\n      out.push(\n        text(\n          {\n            x: pin.x + 5,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n  for (const pin of g.outputPins) {\n    if (pin.label) {\n      out.push(\n        text(\n          {\n            x: pin.x - 6,\n            y: pin.y + 3,\n            class: \"schematex-logic-pin-label\",\n            \"text-anchor\": \"end\",\n          },\n          pin.label\n        )\n      );\n    }\n  }\n\n  // Gate type label (center top, small)\n  if (style === \"ansi\" && g.iecLabel && g.height >= 60) {\n    const labelX = g.width / 2;\n    const labelY = g.height + 14;\n    out.push(\n      text(\n        {\n          x: labelX,\n          y: labelY,\n          class: \"schematex-logic-gate-type\",\n          \"text-anchor\": \"middle\",\n        },\n        n.gateType ?? \"\"\n      )\n    );\n  }\n\n  return out;\n}\n\nexport function renderLogic(ast: LogicGateAST, config?: RenderConfig): string {\n  const style: LogicGateStyle = ast.style ?? \"ansi\";\n  const layout = layoutLogic(ast);\n  const { width, height } = layout;\n  const t = resolveIndustrialTheme(config?.theme ?? \"default\");\n\n  const gateSvgs: string[] = [];\n  const portSvgs: string[] = [];\n  const moduleSvgs: string[] = [];\n\n  for (const m of layout.modules) {\n    moduleSvgs.push(\n      group({ \"data-module-id\": m.id }, [\n        el(\"rect\", {\n          x: m.x,\n          y: m.y,\n          width: m.width,\n          height: m.height,\n          rx: 6,\n          class: \"schematex-logic-module\",\n        }),\n        text(\n          {\n            x: m.x + 10,\n            y: m.y + 14,\n            class: \"schematex-logic-module-label\",\n          },\n          m.label\n        ),\n      ])\n    );\n  }\n\n  for (const n of layout.nodes) {\n    if (n.kind === \"gate\") {\n      gateSvgs.push(\n        group(\n          {\n            transform: `translate(${n.x}, ${n.y})`,\n            \"data-gate-id\": n.id,\n            \"data-gate-type\": n.gateType ?? \"\",\n          },\n          renderGateBody(n, style)\n        )\n      );\n    } else if (n.kind === \"input\") {\n      // Label + short stub line; no rectangle.\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"input\" }, [\n          text(\n            {\n              x: 0,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n          el(\"line\", {\n            x1: PORT_SIZE - 12,\n            y1: cy,\n            x2: n.isActiveLow ? PORT_SIZE - 8 : PORT_SIZE,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          n.isActiveLow\n            ? circle({\n                cx: PORT_SIZE - 4,\n                cy,\n                r: 4,\n                class: \"schematex-logic-bubble\",\n              })\n            : \"\",\n        ])\n      );\n    } else if (n.kind === \"output\") {\n      const cy = PORT_H / 2;\n      portSvgs.push(\n        group({ transform: `translate(${n.x}, ${n.y})`, \"data-port\": \"output\" }, [\n          el(\"line\", {\n            x1: 0,\n            y1: cy,\n            x2: 12,\n            y2: cy,\n            class: \"schematex-logic-wire\",\n          }),\n          text(\n            {\n              x: 16,\n              y: cy + 4,\n              \"text-anchor\": \"start\",\n              class: \"schematex-logic-port-label\",\n            },\n            n.label\n          ),\n        ])\n      );\n    }\n  }\n\n  const wireSvgs = layout.wires.map((w) => {\n    const extras: string[] = [];\n    if (w.isActiveLow) {\n      extras.push(\n        circle({\n          cx: w.toX - 4,\n          cy: w.toY,\n          r: 4,\n          class: \"schematex-logic-bubble\",\n        })\n      );\n    }\n    return [\n      pathEl({\n        d: w.path,\n        class: \"schematex-logic-wire\",\n        \"data-from\": w.fromNode,\n        \"data-to\": w.toNode,\n      }),\n      ...extras,\n    ].join(\"\");\n  });\n\n  const css = `\n.schematex-logic { background: ${t.bg}; font-family: system-ui, -apple-system, sans-serif; }\n.schematex-logic-gate-body { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.75; stroke-linejoin: round; }\n.schematex-logic-bubble { fill: ${t.bg}; stroke: ${t.strokeHeavy}; stroke-width: 1.5; }\n.schematex-logic-clock-tri { fill: none; stroke: ${t.strokeHeavy}; stroke-width: 1.5; stroke-linejoin: round; }\n.schematex-logic-wire { stroke: ${t.strokeHeavy}; stroke-width: 1.5; fill: none; stroke-linecap: square; }\n.schematex-logic-port-label { font: 13px system-ui, sans-serif; fill: ${t.text}; }\n.schematex-logic-pin-label { font: 9px sans-serif; fill: ${t.stroke}; }\n.schematex-logic-gate-type { font: 10px sans-serif; fill: ${t.textMuted}; }\n.schematex-logic-gate-iec-label { font: bold 13px sans-serif; fill: ${t.text}; }\n.schematex-logic-title { font: bold 14px sans-serif; fill: ${t.text}; }\n.schematex-logic-module { fill: none; stroke: ${t.textMuted}; stroke-width: 1.25; stroke-dasharray: 6 4; }\n.schematex-logic-module-label { font: 11px sans-serif; fill: ${t.textMuted}; font-style: italic; }\n`.trim();\n\n  const titleSvg = ast.title\n    ? text(\n        {\n          x: width / 2,\n          y: 18,\n          \"text-anchor\": \"middle\",\n          class: \"schematex-logic-title\",\n        },\n        ast.title\n      )\n    : \"\";\n\n  return svgRoot(\n    {\n      class: \"schematex-logic\",\n      viewBox: `0 0 ${width} ${height + (ast.title ? 20 : 0)}`,\n      width,\n      height: height + (ast.title ? 20 : 0),\n      role: \"img\",\n      \"data-diagram-type\": \"logic\",\n    },\n    [\n      titleEl(ast.title ?? \"Logic Gate Diagram\"),\n      desc(\n        `Logic gate diagram with ${ast.gates.length} gates, ${ast.inputs.length} inputs, ${ast.outputs.length} outputs`\n      ),\n      defs([el(\"style\", {}, css)]),\n      group(\n        { transform: `translate(0, ${ast.title ? 20 : 0})` },\n        [\n          group({ class: \"schematex-logic-modules\" }, moduleSvgs),\n          group({ class: \"schematex-logic-wires\" }, wireSvgs),\n          group({ class: \"schematex-logic-gates\" }, gateSvgs),\n          group({ class: \"schematex-logic-ports\" }, portSvgs),\n        ]\n      ),\n      titleSvg,\n    ]\n  );\n}\n","import type { DiagramPlugin } from \"../../core/types\";\nimport { parseLogic } from \"./parser\";\nimport { renderLogic } from \"./renderer\";\n\nexport const logic: DiagramPlugin = {\n  type: \"logic\",\n  detect(text: string): boolean {\n    const first = text.trim().split(\"\\n\")[0]?.trim().toLowerCase() ?? \"\";\n    return first.startsWith(\"logic\");\n  },\n  parse: parseLogic,\n\n  render(text: string, config): string {\n    const ast = parseLogic(text);\n    return renderLogic(ast, config);\n  },\n};\n\nexport { parseLogic } from \"./parser\";\nexport { renderLogic } from \"./renderer\";\nexport { layoutLogic } from \"./layout\";\n"]}

package/dist/{chunk-H4CJTKEH.js → chunk-MNOO7STY.js}

@@ -1,4 +1,4 @@
-import { parse, render } from './chunk-RNGYXGHS.js';
+import { parse, render } from './chunk-6YUP3QMA.js';
 
 // src/ai/registry.ts
 var DIAGRAM_REGISTRY = [
@@ -985,7 +985,7 @@ var SYNTAX = {
   },
   "circuit": {
     "title": "Circuit schematic",
-    "content": '## 1. A minimal circuit\n\nThe smallest useful positional circuit: a voltage source, a resistor, and a ground.\n\n```\ncircuit "Voltage divider"\nV1: voltage_source down value="5V"\nwire right\nR1: resistor right value="10k"\nwire right\nground\n```\n\nFour rules cover 80% of positional-mode usage:\n\n1. Start with the keyword `circuit`, optionally followed by a quoted title.\n2. Each component is `id: type direction` \u2014 or just `type direction` for anonymous components.\n3. Each component\'s output end becomes the starting point for the next component (the "cursor").\n4. `at: id.end` (or `at: id.start`) jumps the cursor to any named anchor \u2014 use this to branch.\n\n> Comments must start with `#` on their own line.\n\n---\n\n## 2. Components\n\n### 2.1 Positional mode syntax\n\nA named component line has the form:\n\n```\nid: type direction [value="\u2026"] [label="\u2026"]\n```\n\nAn anonymous component omits the `id:` prefix \u2014 the parser assigns an auto ID.\n\n```\nR1: resistor right value="4.7k" label="R1"\ncapacitor down value="100n"\n```\n\n**Direction** is one of `right` (default), `left`, `up`, `down`. It controls which way the component extends from the current cursor position.\n\n### 2.2 Passive components\n\n| DSL type | Description |\n|---|---|\n| `resistor` | Zigzag (ANSI) or rectangle (IEC) |\n| `potentiometer` | Resistor + wiper arrow, 3-pin |\n| `rheostat` | 2-pin variable resistor |\n| `thermistor_ntc` | NTC thermistor (also: `therm`, `ntc`) |\n| `thermistor_ptc` | PTC thermistor (also: `ptc`) |\n| `ldr` | Light-dependent resistor |\n| `varistor` | Voltage-dependent resistor |\n| `fuse` | Standard fuse |\n| `fuse_slow` | Slow-blow fuse (`T` designation) |\n| `capacitor` | Non-polar capacitor |\n| `electrolytic_cap` | Polar/electrolytic capacitor (also: `ecap`) |\n| `variable_cap` | Variable capacitor |\n| `inductor` | Air-core inductor |\n| `inductor_iron` | Iron-core inductor |\n| `inductor_ferrite` | Ferrite-core inductor |\n| `variable_inductor` | Variable inductor |\n| `ferrite_bead` | EMI ferrite bead |\n| `crystal` | Quartz crystal oscillator (also: `xtal`) |\n| `transformer` | Coupled coils (also: `xfmr`) |\n\n```\ncircuit "Passive components gallery"\n# Row 1: resistor \u2192 capacitor \u2192 inductor\nR1: resistor right value="1k"\nwire right\nC1: capacitor right value="100n"\nwire right\nL1: inductor right value="10u"\n# Row 2: crystal and transformer, offset below\nat: R1.start\nwire down\nwire down\nX1: crystal right\nwire right\nwire right\nT1: transformer right\n```\n\n### 2.3 Sources and power\n\n| DSL type | Description |\n|---|---|\n| `voltage_source` | Circle + polarity (also: `vsource`) |\n| `current_source` | Circle + arrow (also: `isource`) |\n| `ac_source` | Circle + sine symbol (also: `acsource`) |\n| `battery` | Alternating long/short terminal lines |\n| `vcc` | Power rail arrow (pointing up) |\n| `ground` | Earth ground \u2014 3 decreasing lines (also: `gnd`) |\n| `gnd_signal` | Signal ground \u2014 solid triangle |\n| `gnd_chassis` | Chassis ground |\n| `gnd_digital` | Digital ground |\n\n```\ncircuit "Sources and power gallery"\n# voltage source with ground\nV1: voltage_source down value="5V"\nwire down\nground\nat: V1.start\nwire right\nwire right\n# battery\nB1: battery down value="9V"\nwire down\nground\nat: B1.start\nwire right\nwire right\n# ac source\nA1: ac_source down value="120V"\nwire down\nground\nat: A1.start\nwire right\nwire right\n# vcc rail\nvcc up\nwire down\ngnd_signal down\n```\n\n### 2.4 Semiconductors \u2014 diodes\n\n| DSL type | Description |\n|---|---|\n| `diode` | Triangle + cathode bar |\n| `zener` | Diode + bent cathode bar |\n| `schottky` | Diode + S-bar |\n| `led` | Diode + outward emission arrows |\n| `photodiode` | Diode + inward light arrows |\n| `varactor` | Diode + variable capacitor |\n| `tvs_diode` | Bidirectional TVS (two bent bars) |\n| `bridge_rectifier` | 4-diode bridge, 4-pin |\n\n```\ncircuit "Diode types gallery"\nD1: diode right\nwire right\nD2: zener right\nwire right\nD3: led right\nwire right\nD4: schottky right\nwire right\nD5: photodiode right\nwire right\nground\nat: D1.start\nwire left\nground\n```\n\n### 2.5 Semiconductors \u2014 transistors\n\n| DSL type | Description |\n|---|---|\n| `npn` | NPN BJT (also: `transistor`, `bjt_npn`) |\n| `pnp` | PNP BJT (also: `bjt_pnp`) |\n| `darlington_npn` | NPN Darlington pair |\n| `darlington_pnp` | PNP Darlington pair |\n| `nmos` | N-channel MOSFET enhancement (also: `mosfet_n`) |\n| `pmos` | P-channel MOSFET enhancement (also: `mosfet_p`) |\n| `nmos_depletion` | N-channel MOSFET depletion |\n| `jfet_n` | N-channel JFET |\n| `jfet_p` | P-channel JFET |\n| `igbt` | IGBT |\n| `scr` | SCR / thyristor |\n| `triac` | TRIAC |\n| `diac` | DIAC |\n| `phototransistor` | NPN with light arrows |\n| `optocoupler` | LED + phototransistor in isolation box |\n\n```\ncircuit "Transistor types gallery"\n# NPN BJT\nQ1: npn right\nwire right\nwire right\n# PNP BJT\nQ2: pnp right\nwire right\nwire right\n# N-channel MOSFET\nQ3: nmos right\nwire right\nwire right\n# P-channel MOSFET\nQ4: pmos right\n```\n\n### 2.6 Analog ICs and op-amps\n\n| DSL type | Description |\n|---|---|\n| `opamp` | Triangle: +/\u2212 inputs, output |\n| `comparator` | Same shape, open-collector output |\n| `schmitt_buffer` | Buffer + hysteresis symbol |\n| `tri_state_buffer` | Buffer + enable pin |\n| `instrumentation_amp` | Three-op-amp INA block |\n| `generic_ic` | Configurable rect with labeled pins (also: `ic`) |\n| `voltage_regulator` | 3-terminal block: IN/GND/OUT (also: `reg`) |\n| `dc_dc_converter` | 2-port block with DC/DC label |\n| `555_timer` | 8-pin 555 pinout block (also: `timer555`) |\n\n```\ncircuit "Analog IC gallery"\n# op-amp with input/output wires\nwire right\nU1: opamp right\nwire right\nwire right\nwire right\n# comparator\nU2: comparator right\nwire right\nwire right\nwire right\n# generic IC block\nU3: generic_ic right\n```\n\n### 2.7 Switches and relays\n\n| DSL type | Description |\n|---|---|\n| `switch_spst` | Single-pole single-throw |\n| `switch_spdt` | Single-pole double-throw |\n| `switch_dpdt` | Double-pole double-throw |\n| `push_no` | Push button normally-open |\n| `push_nc` | Push button normally-closed |\n| `relay_coil` | Relay coil (2-pin rect) |\n| `relay_no` | Relay contact normally-open |\n| `relay_nc` | Relay contact normally-closed |\n\n```\ncircuit "Switch and relay gallery"\n# SPST switch\nS1: switch_spst right\nwire right\nwire right\n# SPDT switch\nS2: switch_spdt right\nwire right\nwire right\n# normally-open push button\nS3: push_no right\nwire right\nwire right\n# relay coil + contact pair\nK1: relay_coil right\nwire right\nK2: relay_no right\n```\n\n### 2.8 Electromechanical and measurement\n\n| DSL type | Description |\n|---|---|\n| `motor` | Circle + M |\n| `speaker` | Cone + box |\n| `microphone` | Capsule symbol |\n| `buzzer` | Piezo buzzer |\n| `ammeter` | Circle + A |\n| `voltmeter` | Circle + V |\n| `wattmeter` | Circle + W |\n| `oscilloscope` | Circle + waveform |\n\n### 2.9 Connectors and annotations\n\n| DSL type | Description |\n|---|---|\n| `wire` | Plain wire segment |\n| `dot` | Junction dot (T-junction marker) |\n| `label` | Net label / flag |\n| `port` | Named port (hollow circle) |\n| `test_point` | TP marker |\n| `no_connect` | X \u2014 intentionally unconnected pin |\n| `antenna` | Antenna stub |\n\n```\ncircuit "Passive components"\nR1: resistor right value="1k" label="R1"\nwire right\nC1: capacitor down value="100n" label="C1"\nwire down\nground\nat: R1.start\nwire up\nbattery up label="9V"\n```\n\n---\n\n## 3. Wiring and branching\n\n### 3.1 Wire segments\n\n`wire direction [N]` draws a bare wire from the current cursor in the given direction. An optional number sets the length in pixels.\n\n```\nwire right\nwire down 40\nwire left 20\n```\n\n### 3.2 Jumping the cursor with `at:`\n\n`at: id.end` moves the cursor to a named anchor without drawing anything. Use it to branch from a previously placed component.\n\n```\nR1: resistor right value="10k"\nat: R1.end\nC1: capacitor down value="100n"\n```\n\nNamed anchor suffixes: `end`, `start`. Components retain their ID across the whole diagram, so you can jump back to any previously placed component.\n\n### 3.3 Junction dots\n\nPlace a `dot` (or use `net NAME: dot`) to mark a T-junction \u2014 a point where three or more wires meet. Without a dot, crossed wires are drawn as a crossover (no connection).\n\n```\nR1: resistor right\ndot\nwire right           # continues from R1.end\nat: R1.end\nC1: capacitor down   # branches down from the same point\n```\n\n### 3.4 Named nets\n\n`net NAME` declares a named net. `net NAME: dot` declares the net and places a junction dot at the current cursor, remembering that location. Later, `at: NAME` jumps back to that net\'s anchor.\n\n```\nnet VOUT: dot\nR2: resistor right value="10k"\nat: VOUT\nC1: capacitor down value="470n"\n```\n\n### 3.5 Net labels\n\n`label "text" direction?` places a text label at the current cursor position. Labels do not advance the cursor. They are useful for naming power rails or inter-sheet connections.\n\n```\nlabel "VCC" up\nlabel "GND" down\n```\n\n```\ncircuit "RC filter"\nV1: voltage_source down value="5V"\nwire right\nR1: resistor right value="1k" label="R1"\nnet OUT: dot\nwire right\nlabel "Vout" right\nat: OUT\nC1: capacitor down value="100n" label="C1"\nwire down\nground\n```\n\n---\n\n## 4. Netlist mode\n\nAdd `netlist` after the title on the header line to switch to SPICE-style netlist parsing. The auto-layout engine computes component positions from the net connectivity.\n\n```\ncircuit "Low-pass filter" netlist\n```\n\n### 4.1 Netlist line format\n\nEach line is: `ID net1 net2 [net3\u2026] [value] [key=value\u2026]`\n\n- **ID** \u2014 component identifier. The first letter determines the default type (SPICE prefix convention).\n- **net1, net2, \u2026** \u2014 net names the pins connect to. Use `0`, `gnd`, or `GND` for the ground net.\n- **value** (optional bare token) \u2014 component value or model name.\n- **key=value** (optional) \u2014 `label=`, `value=`, `type=` overrides.\n\n### 4.2 SPICE prefix \u2192 component type\n\n| Prefix | Default type | Pin order |\n|---|---|---|\n| `R` | `resistor` | p1, p2 |\n| `C` | `capacitor` | p1, p2 |\n| `L` | `inductor` | p1, p2 |\n| `D` | `diode` | anode (start), cathode (end) |\n| `V` | `voltage_source` | plus, minus |\n| `I` | `current_source` | plus, minus |\n| `Q` | `npn` | c, b, e |\n| `M` | `nmos` | d, g, s |\n| `J` | `jfet_n` | d, g, s |\n| `S` | `switch_spst` | p1, p2 |\n| `F` | `fuse` | p1, p2 |\n| `B` | `battery` | plus, minus |\n| `K` | `relay_coil` | p1, p2 |\n| `U`, `X` | `generic_ic` | custom via `pins=` |\n\n### 4.3 Transistor model override\n\nFor `Q` lines, a trailing model name overrides the type:\n\n```\nQ1 c b e npn      # NPN BJT\nQ2 c b e pnp      # PNP BJT\nM1 d g s nmos     # N-channel MOSFET\nM2 d g s pmos     # P-channel MOSFET\n```\n\nFor `D` lines, similarly:\n\n```\nD1 anode cathode zener\nD2 anode cathode led\nD3 anode cathode schottky\nD4 anode cathode photodiode\n```\n\n### 4.4 Netlist example\n\n```\ncircuit "CE Amp (netlist)" netlist\nV1 vcc 0 9V\nRc vcc c 2.2k\nRb vcc b 100k\nQ1 c b e npn\nRe e 0 1k\n```\n\n---\n\n## 5. Attributes\n\nBoth positional and netlist modes accept these key=value attributes:\n\n| Attribute | Accepted by | Effect |\n|---|---|---|\n| `label="\u2026"` | all components | Display label (reference designator) |\n| `value="\u2026"` | all components | Value annotation (1k\u03A9, 100nF, 5V) |\n| `at=id.end` | positional components | Start this component at a named anchor |\n| `length=N` | `wire`, some passives | Length in pixels |\n\nIn positional mode, `at=` inside the component line is equivalent to a preceding `at:` line:\n\n```\nC1: capacitor down at=R1.end value="100n"\n```\n\n---\n\n## 6. Labels & comments\n\n- **Diagram title:** `circuit "RC Filter"` \u2014 first line only.\n- **Component label:** `label="R1"` attribute \u2014 reference designator shown beside the symbol.\n- **Value annotation:** `value="4.7k"` \u2014 shown beside or below the component.\n- **Net label:** `label "VOUT" right` \u2014 standalone net flag at the current cursor.\n- **Comments:** `#` at the start of a line (after leading whitespace).\n\n---\n\n## 7. Reserved words & escaping\n\n**Reserved at line start (positional):** `circuit` (header), `at:`, `net`, `wire`, `label`.\n\n**Reserved in netlist mode:** same header rules apply; all other lines are SPICE component lines.\n\n**Ground net aliases (netlist only):** `0`, `gnd`, `GND`, `Gnd`, `ground`, `Ground` \u2014 all treated as the same node.\n\n**Component IDs** must match `[a-zA-Z_][a-zA-Z0-9_]*`. Spaces in values must be quoted: `value="10 k\u03A9"`.\n\n---\n\n## 8. Common mistakes\n\n| You wrote | Parser says | Fix |\n|---|---|---|\n| `resistor right 1k` (bare value without `value=`) | `1k` is parsed as an unknown attribute flag and ignored | Use `value="1k"`: `resistor right value="1k"` |\n| `at: R1.center` | `center` is not a recognized anchor suffix \u2014 cursor stays at current position | Use `at: R1.end` or `at: R1.start` |\n| `wire 40` (no direction) | Direction defaults to `right`; length `40` is accepted | Explicit direction recommended: `wire right 40` |\n| `R1 vcc out 10k` in positional mode | Line matches the bare-type pattern; `R1` is read as a type name, fails lookup | In positional mode, use `R1: resistor right value="10k"` |\n| `Q1 c b e` (netlist, no model) | Type defaults to `npn` from `Q` prefix \u2014 correct | OK; add `npn` explicitly for clarity |\n| `net OUT` then `at: OUT` without `net OUT: dot` | `OUT` net exists but has no anchor; jump has no destination | Use `net OUT: dot` to register the cursor position |\n| `label VCC up` (unquoted label) | `VCC` is parsed as a direction token, then `up` \u2014 the label text is lost | Quote the text: `label "VCC" up` |\n\n---\n\n## 9. Grammar (EBNF)\n\n```text\ndocument        = header statement*\n\n-- Positional mode --\nheader          = "circuit" ( WS quoted-string )? NEWLINE\nstatement       = blank | comment | component | wire | at | net-decl | label-stmt\n\ncomponent       = ( id ":" WS )? type WS direction? attrs* NEWLINE\nwire            = "wire" ( WS direction )? ( WS integer )? NEWLINE\nat              = "at:" WS anchor NEWLINE\nanchor          = id "." ( "start" | "end" )\n                | id                          // net name anchor\n\nnet-decl        = "net" WS id NEWLINE         // declare net only\n                | "net" WS id ":" WS "dot" NEWLINE  // declare + place dot\n\nlabel-stmt      = "label" WS quoted-string ( WS direction )? NEWLINE\n\ncomponent-attr  = "value=" quoted-string\n                | "label=" quoted-string\n                | "at=" anchor\n                | "length=" integer\n\ndirection       = "right" | "left" | "up" | "down"\ntype            = // any value from \xA72 component tables\n\n-- Netlist mode --\nnetlist-header  = "circuit" ( WS quoted-string )? WS "netlist" NEWLINE\nnetlist-stmt    = id WS net-ref+ ( WS kv-pair )* NEWLINE\n                | comment\nnet-ref         = id | "0"                    // net name or ground alias\nkv-pair         = id "=" ( quoted-string | bare-value )\n\nid              = [a-zA-Z_] [a-zA-Z0-9_]*\ninteger         = [0-9]+\nquoted-string   = \'"\' any-char-but-quote* \'"\'\ncomment         = "#" any NEWLINE\n```\n\nAuthoritative source: `src/diagrams/circuit/parser.ts` and `src/diagrams/circuit/netlist.ts`. If this diverges from the parser, the parser wins \u2014 please open an issue.\n\n---'
+    "content": '## 1. A minimal circuit\n\nThe smallest useful positional circuit: a voltage source, a resistor, and a ground.\n\n```\ncircuit "Voltage divider"\nV1: voltage_source down value="5V"\nwire right\nR1: resistor right value="10k"\nwire right\nground\n```\n\nFour rules cover 80% of positional-mode usage:\n\n1. Start with the keyword `circuit`, optionally followed by a quoted title.\n2. Each component is `id: type direction` \u2014 or just `type direction` for anonymous components.\n3. Each component\'s output end becomes the starting point for the next component (the "cursor").\n4. `at: id.end` (or `at: id.start`) jumps the cursor to any named anchor \u2014 use this to branch.\n\n> Comments must start with `#` on their own line.\n\n---\n\n## 2. Components\n\n### 2.1 Positional mode syntax\n\nA named component line has the form:\n\n```\nid: type direction [value="\u2026"] [label="\u2026"]\n```\n\nAn anonymous component omits the `id:` prefix \u2014 the parser assigns an auto ID.\n\n```\nR1: resistor right value="4.7k" label="R1"\ncapacitor down value="100n"\n```\n\n**Direction** is one of `right` (default), `left`, `up`, `down`. It controls which way the component extends from the current cursor position.\n\n### 2.2 Passive components\n\n| DSL type | Description |\n|---|---|\n| `resistor` | Zigzag (ANSI) or rectangle (IEC) |\n| `potentiometer` | Resistor + wiper arrow, 3-pin |\n| `rheostat` | 2-pin variable resistor |\n| `thermistor_ntc` | NTC thermistor (also: `therm`, `ntc`) |\n| `thermistor_ptc` | PTC thermistor (also: `ptc`) |\n| `ldr` | Light-dependent resistor |\n| `varistor` | Voltage-dependent resistor |\n| `fuse` | Standard fuse |\n| `fuse_slow` | Slow-blow fuse (`T` designation) |\n| `capacitor` | Non-polar capacitor |\n| `electrolytic_cap` | Polar/electrolytic capacitor (also: `ecap`) |\n| `variable_cap` | Variable capacitor |\n| `inductor` | Air-core inductor |\n| `inductor_iron` | Iron-core inductor |\n| `inductor_ferrite` | Ferrite-core inductor |\n| `variable_inductor` | Variable inductor |\n| `ferrite_bead` | EMI ferrite bead |\n| `crystal` | Quartz crystal oscillator (also: `xtal`) |\n| `transformer` | Coupled coils (also: `xfmr`) |\n\n```\ncircuit "Passive components gallery"\n# Row 1: resistor \u2192 capacitor \u2192 inductor\nR1: resistor right value="1k"\nwire right\nC1: capacitor right value="100n"\nwire right\nL1: inductor right value="10u"\n# Row 2: crystal and transformer, offset below\nat: R1.start\nwire down\nwire down\nX1: crystal right\nwire right\nwire right\nT1: transformer right\n```\n\n### 2.3 Sources and power\n\n| DSL type | Description |\n|---|---|\n| `voltage_source` | Circle + polarity (also: `vsource`) |\n| `current_source` | Circle + arrow (also: `isource`) |\n| `ac_source` | Circle + sine symbol (also: `acsource`) |\n| `battery` | Alternating long/short terminal lines |\n| `vcc` | Power rail arrow (pointing up) |\n| `ground` | Earth ground \u2014 3 decreasing lines (also: `gnd`) |\n| `gnd_signal` | Signal ground \u2014 solid triangle |\n| `gnd_chassis` | Chassis ground |\n| `gnd_digital` | Digital ground |\n\n```\ncircuit "Sources and power gallery"\n# voltage source with ground\nV1: voltage_source down value="5V"\nwire down\nground\nat: V1.start\nwire right\nwire right\n# battery\nB1: battery down value="9V"\nwire down\nground\nat: B1.start\nwire right\nwire right\n# ac source\nA1: ac_source down value="120V"\nwire down\nground\nat: A1.start\nwire right\nwire right\n# vcc rail\nvcc up\nwire down\ngnd_signal down\n```\n\n### 2.4 Semiconductors \u2014 diodes\n\n| DSL type | Description |\n|---|---|\n| `diode` | Triangle + cathode bar |\n| `zener` | Diode + bent cathode bar |\n| `schottky` | Diode + S-bar |\n| `led` | Diode + outward emission arrows |\n| `photodiode` | Diode + inward light arrows |\n| `varactor` | Diode + variable capacitor |\n| `tvs_diode` | Bidirectional TVS (two bent bars) |\n| `bridge_rectifier` | 4-diode bridge, 4-pin |\n\n```\ncircuit "Diode types gallery"\nD1: diode right\nwire right\nD2: zener right\nwire right\nD3: led right\nwire right\nD4: schottky right\nwire right\nD5: photodiode right\nwire right\nground\nat: D1.start\nwire left\nground\n```\n\n### 2.5 Semiconductors \u2014 transistors\n\n| DSL type | Description |\n|---|---|\n| `npn` | NPN BJT (also: `transistor`, `bjt_npn`) |\n| `pnp` | PNP BJT (also: `bjt_pnp`) |\n| `darlington_npn` | NPN Darlington pair |\n| `darlington_pnp` | PNP Darlington pair |\n| `nmos` | N-channel MOSFET enhancement (also: `mosfet_n`) |\n| `pmos` | P-channel MOSFET enhancement (also: `mosfet_p`) |\n| `nmos_depletion` | N-channel MOSFET depletion |\n| `jfet_n` | N-channel JFET |\n| `jfet_p` | P-channel JFET |\n| `igbt` | IGBT |\n| `scr` | SCR / thyristor |\n| `triac` | TRIAC |\n| `diac` | DIAC |\n| `phototransistor` | NPN with light arrows |\n| `optocoupler` | LED + phototransistor in isolation box |\n\n```\ncircuit "Transistor types gallery"\n# NPN BJT\nQ1: npn right\nwire right\nwire right\n# PNP BJT\nQ2: pnp right\nwire right\nwire right\n# N-channel MOSFET\nQ3: nmos right\nwire right\nwire right\n# P-channel MOSFET\nQ4: pmos right\n```\n\n### 2.6 Analog ICs and op-amps\n\n| DSL type | Description |\n|---|---|\n| `opamp` | Triangle: +/\u2212 inputs, output |\n| `comparator` | Same shape, open-collector output |\n| `schmitt_buffer` | Buffer + hysteresis symbol |\n| `tri_state_buffer` | Buffer + enable pin |\n| `instrumentation_amp` | Three-op-amp INA block |\n| `generic_ic` | Configurable rect with labeled pins (also: `ic`) |\n| `voltage_regulator` | 3-terminal block: IN/GND/OUT (also: `reg`) |\n| `dc_dc_converter` | 2-port block with DC/DC label |\n| `555_timer` | 8-pin 555 pinout block (also: `timer555`) |\n\n```\ncircuit "Analog IC gallery"\n# op-amp with input/output wires\nwire right\nU1: opamp right\nwire right\nwire right\nwire right\n# comparator\nU2: comparator right\nwire right\nwire right\nwire right\n# generic IC block\nU3: generic_ic right\n```\n\n### 2.7 Switches and relays\n\n| DSL type | Description |\n|---|---|\n| `switch_spst` | Single-pole single-throw |\n| `switch_spdt` | Single-pole double-throw |\n| `switch_dpdt` | Double-pole double-throw |\n| `push_no` | Push button normally-open |\n| `push_nc` | Push button normally-closed |\n| `relay_coil` | Relay coil (2-pin rect) |\n| `relay_no` | Relay contact normally-open |\n| `relay_nc` | Relay contact normally-closed |\n\n```\ncircuit "Switch and relay gallery"\n# SPST switch\nS1: switch_spst right\nwire right\nwire right\n# SPDT switch\nS2: switch_spdt right\nwire right\nwire right\n# normally-open push button\nS3: push_no right\nwire right\nwire right\n# relay coil + contact pair\nK1: relay_coil right\nwire right\nK2: relay_no right\n```\n\n### 2.8 Electromechanical and measurement\n\n| DSL type | Description |\n|---|---|\n| `motor` | Circle + M |\n| `speaker` | Cone + box |\n| `microphone` | Capsule symbol |\n| `buzzer` | Piezo buzzer |\n| `ammeter` | Circle + A |\n| `voltmeter` | Circle + V |\n| `wattmeter` | Circle + W |\n| `oscilloscope` | Circle + waveform |\n\n### 2.9 Connectors and annotations\n\n| DSL type | Description |\n|---|---|\n| `wire` | Plain wire segment |\n| `dot` | Junction dot (T-junction marker) |\n| `label` | Net label / flag |\n| `port` | Named port (hollow circle) |\n| `test_point` | TP marker |\n| `no_connect` | X \u2014 intentionally unconnected pin |\n| `antenna` | Antenna stub |\n\n```\ncircuit "Passive components"\nR1: resistor right value="1k" label="R1"\nwire right\nC1: capacitor down value="100n" label="C1"\nwire down\nground\nat: R1.start\nwire up\nbattery up label="9V"\n```\n\n---\n\n## 3. Wiring and branching\n\n### 3.1 Wire segments\n\n`wire direction [N]` draws a bare wire from the current cursor in the given direction. An optional number sets the length in pixels.\n\n```\nwire right\nwire down 40\nwire left 20\n```\n\n### 3.2 Jumping the cursor with `at:`\n\n`at: id.end` moves the cursor to a named anchor without drawing anything. Use it to branch from a previously placed component.\n\n```\nR1: resistor right value="10k"\nat: R1.end\nC1: capacitor down value="100n"\n```\n\nNamed anchor suffixes: `end`, `start`. Components retain their ID across the whole diagram, so you can jump back to any previously placed component.\n\n### 3.3 Junction dots\n\nPlace a `dot` (or use `net NAME: dot`) to mark a T-junction \u2014 a point where three or more wires meet. Without a dot, crossed wires are drawn as a crossover (no connection).\n\n```\nR1: resistor right\ndot\nwire right           # continues from R1.end\nat: R1.end\nC1: capacitor down   # branches down from the same point\n```\n\n### 3.4 Named nets\n\n`net NAME` declares a named net. `net NAME: dot` declares the net and places a junction dot at the current cursor, remembering that location. Later, `at: NAME` jumps back to that net\'s anchor.\n\n```\nnet VOUT: dot\nR2: resistor right value="10k"\nat: VOUT\nC1: capacitor down value="470n"\n```\n\n### 3.5 Net labels\n\n`label "text" direction?` places a text label at the current cursor position. Labels do not advance the cursor. They are useful for naming power rails or inter-sheet connections.\n\n```\nlabel "VCC" up\nlabel "GND" down\n```\n\n```\ncircuit "RC filter"\nV1: voltage_source down value="5V"\nwire right\nR1: resistor right value="1k" label="R1"\nnet OUT: dot\nwire right\nlabel "Vout" right\nat: OUT\nC1: capacitor down value="100n" label="C1"\nwire down\nground\n```\n\n---\n\n## 4. Netlist mode\n\nAdd `netlist` after the title on the header line to switch to SPICE-style netlist parsing. The auto-layout engine computes component positions from the net connectivity.\n\n```\ncircuit "Low-pass filter" netlist\n```\n\n### 4.1 Netlist line format\n\nEach line is: `ID net1 net2 [net3\u2026] [value] [key=value\u2026]`\n\n- **ID** \u2014 component identifier. The first letter determines the default type (SPICE prefix convention).\n- **net1, net2, \u2026** \u2014 net names the pins connect to. Net names matching `0`, `gnd`, `ground`, `earth`, `pe`, `agnd`, `dgnd`, `gnda`, `gndd`, `vss`, or `com` (case-insensitive, with optional `_<word>` or numeric suffix \u2014 e.g. `gnd_ref`, `AGND_DIG`, `EARTH1`) all canonicalize to the ground net.\n- **value** (optional bare token) \u2014 component value or model name.\n- **key=value** (optional) \u2014 `label=`, `value=`, `type=` overrides.\n\n### 4.2 SPICE prefix \u2192 component type\n\n| Prefix | Default type | Pin order |\n|---|---|---|\n| `R` | `resistor` | p1, p2 |\n| `C` | `capacitor` | p1, p2 |\n| `L` | `inductor` | p1, p2 |\n| `D` | `diode` | anode (start), cathode (end) |\n| `V` | `voltage_source` | plus, minus |\n| `I` | `current_source` | plus, minus |\n| `Q` | `npn` | c, b, e |\n| `M` | `nmos` | d, g, s |\n| `J` | `jfet_n` | d, g, s |\n| `S` | `switch_spst` | p1, p2 |\n| `F` | `fuse` | p1, p2 |\n| `B` | `battery` | plus, minus |\n| `K` | `relay_coil` | p1, p2 |\n| `U`, `X` | `generic_ic` | custom via `pins=` |\n| `W` | `wire` | start, end |\n| `T` | `terminal_block` | custom via `pins=` (also `type=junction_box`) |\n\n> **Scope:** schematex circuit covers **electrical schematics only** (IEEE 315 / IEC 60617). Hydraulic and pneumatic schematics (ISO 1219) use a fundamentally different visual grammar \u2014 directional valve envelopes, cylinder symbols, line styles for pressure/return/drain \u2014 and are not supported by this engine. Hydraulic prefixes such as `EV*` (electrovalve), `BOMBA*` (pump), `TANK*`, `DIPOSIT*` will be rejected with a "cannot infer type" error.\n\n### 4.3 Transistor model override\n\nFor `Q` lines, a trailing model name overrides the type:\n\n```\nQ1 c b e npn      # NPN BJT\nQ2 c b e pnp      # PNP BJT\nM1 d g s nmos     # N-channel MOSFET\nM2 d g s pmos     # P-channel MOSFET\n```\n\nFor `D` lines, similarly:\n\n```\nD1 anode cathode zener\nD2 anode cathode led\nD3 anode cathode schottky\nD4 anode cathode photodiode\n```\n\n### 4.4 Netlist example\n\n```\ncircuit "CE Amp (netlist)" netlist\nV1 vcc 0 9V\nRc vcc c 2.2k\nRb vcc b 100k\nQ1 c b e npn\nRe e 0 1k\n```\n\n---\n\n## 5. Attributes\n\nBoth positional and netlist modes accept these key=value attributes:\n\n| Attribute | Accepted by | Effect |\n|---|---|---|\n| `label="\u2026"` | all components | Display label (reference designator) |\n| `value="\u2026"` | all components | Value annotation (1k\u03A9, 100nF, 5V) |\n| `at=id.end` | positional components | Start this component at a named anchor |\n| `length=N` | `wire`, some passives | Length in pixels |\n\nIn positional mode, `at=` inside the component line is equivalent to a preceding `at:` line:\n\n```\nC1: capacitor down at=R1.end value="100n"\n```\n\n---\n\n## 6. Labels & comments\n\n- **Diagram title:** `circuit "RC Filter"` \u2014 first line only.\n- **Component label:** `label="R1"` attribute \u2014 reference designator shown beside the symbol.\n- **Value annotation:** `value="4.7k"` \u2014 shown beside or below the component.\n- **Net label:** `label "VOUT" right` \u2014 standalone net flag at the current cursor.\n- **Comments:** `#` at the start of a line (after leading whitespace).\n\n---\n\n## 7. Reserved words & escaping\n\n**Reserved at line start (positional):** `circuit` (header), `at:`, `net`, `wire`, `label`.\n\n**Reserved in netlist mode:** same header rules apply; all other lines are SPICE component lines.\n\n**Ground net aliases (netlist only):** `0`, `gnd`, `GND`, `Gnd`, `ground`, `Ground` \u2014 all treated as the same node.\n\n**Component IDs** must match `[a-zA-Z_][a-zA-Z0-9_]*`. Spaces in values must be quoted: `value="10 k\u03A9"`.\n\n---\n\n## 8. Common mistakes\n\n| You wrote | Parser says | Fix |\n|---|---|---|\n| `resistor right 1k` (bare value without `value=`) | `1k` is parsed as an unknown attribute flag and ignored | Use `value="1k"`: `resistor right value="1k"` |\n| `at: R1.center` | `center` is not a recognized anchor suffix \u2014 cursor stays at current position | Use `at: R1.end` or `at: R1.start` |\n| `wire 40` (no direction) | Direction defaults to `right`; length `40` is accepted | Explicit direction recommended: `wire right 40` |\n| `R1 vcc out 10k` in positional mode | Line matches the bare-type pattern; `R1` is read as a type name, fails lookup | In positional mode, use `R1: resistor right value="10k"` |\n| `Q1 c b e` (netlist, no model) | Type defaults to `npn` from `Q` prefix \u2014 correct | OK; add `npn` explicitly for clarity |\n| `net OUT` then `at: OUT` without `net OUT: dot` | `OUT` net exists but has no anchor; jump has no destination | Use `net OUT: dot` to register the cursor position |\n| `label VCC up` (unquoted label) | `VCC` is parsed as a direction token, then `up` \u2014 the label text is lost | Quote the text: `label "VCC" up` |\n\n---\n\n## 9. Grammar (EBNF)\n\n```text\ndocument        = header statement*\n\n-- Positional mode --\nheader          = "circuit" ( WS quoted-string )? NEWLINE\nstatement       = blank | comment | component | wire | at | net-decl | label-stmt\n\ncomponent       = ( id ":" WS )? type WS direction? attrs* NEWLINE\nwire            = "wire" ( WS direction )? ( WS integer )? NEWLINE\nat              = "at:" WS anchor NEWLINE\nanchor          = id "." ( "start" | "end" )\n                | id                          // net name anchor\n\nnet-decl        = "net" WS id NEWLINE         // declare net only\n                | "net" WS id ":" WS "dot" NEWLINE  // declare + place dot\n\nlabel-stmt      = "label" WS quoted-string ( WS direction )? NEWLINE\n\ncomponent-attr  = "value=" quoted-string\n                | "label=" quoted-string\n                | "at=" anchor\n                | "length=" integer\n\ndirection       = "right" | "left" | "up" | "down"\ntype            = // any value from \xA72 component tables\n\n-- Netlist mode --\nnetlist-header  = "circuit" ( WS quoted-string )? WS "netlist" NEWLINE\nnetlist-stmt    = id WS net-ref+ ( WS kv-pair )* NEWLINE\n                | comment\nnet-ref         = id | "0"                    // net name or ground alias\nkv-pair         = id "=" ( quoted-string | bare-value )\n\nid              = [a-zA-Z_] [a-zA-Z0-9_]*\ninteger         = [0-9]+\nquoted-string   = \'"\' any-char-but-quote* \'"\'\ncomment         = "#" any NEWLINE\n```\n\nAuthoritative source: `src/diagrams/circuit/parser.ts` and `src/diagrams/circuit/netlist.ts`. If this diverges from the parser, the parser wins \u2014 please open an issue.\n\n---'
   },
   "block": {
     "title": "Block diagram",
@@ -1017,7 +1017,7 @@ var SYNTAX = {
   },
   "flowchart": {
     "title": "Flowchart",
-    "content": '## 1. Your first flowchart\n\nThe smallest useful flowchart: a decision with two outcomes.\n\n```\nflowchart TD\n  A([Start]) --> B{File exists?}\n  B -->|Yes| C[Read file]\n  B -->|No| D[Return error]\n  C --> E([Done])\n```\n\nFour rules cover 80% of usage:\n\n1. Start with `flowchart` followed by a direction: `TD`, `LR`, `BT`, or `RL`.\n2. Each node is `ID[Label]` \u2014 the shape brackets determine the node type (see \xA72).\n3. Connect nodes with `-->`. Add a label between pipe characters: `-->|Yes|`.\n4. Nodes are created automatically when first referenced in an edge \u2014 but explicit declarations let you set shapes and labels independently.\n\n> Comments start with `%%` on their own line.\n\n---\n\n## 2. Node shapes\n\nEach node shape is written as `ID<brackets>Label<brackets>`. The ID must start with a letter and may contain letters, digits, `_`, and `-`.\n\n| Syntax | Shape | Typical use |\n|---|---|---|\n| `A[Label]` | Rectangle | Process step, operation |\n| `A(Label)` | Rounded rectangle | Subprocess, soft step |\n| `A([Label])` | Stadium (pill) | Start / end terminal |\n| `A{Label}` | Diamond | Decision / condition |\n| `A{{Label}}` | Hexagon | Preparation, configuration |\n| `A[[Label]]` | Subroutine | Predefined process |\n| `A[(Label)]` | Cylinder | Database, storage |\n| `A((Label))` | Circle | Connector, junction |\n| `A(((Label)))` | Double circle | End state |\n| `A[/Label/]` | Parallelogram | Input / output |\n| `A[\\Label\\]` | Parallelogram (alt) | Manual operation |\n| `A[/Label\\]` | Trapezoid | Manual input |\n| `A[\\Label/]` | Trapezoid (alt) | Off-page connector |\n| `A>Label]` | Asymmetric | Tag, annotation |\n\n```\nflowchart TD\n  t([Terminal / stadium])\n  r[Rectangle process]\n  d{Diamond decision}\n  p[/Parallelogram input/]\n  db[(Cylinder database)]\n  sub[[Subroutine]]\n  t --> r --> d\n  d -->|branch A| p\n  d -->|branch B| db\n  p --> sub\n  db --> sub\n```\n\n---\n\n## 3. Edges\n\nAn edge connects two nodes. The connector symbol determines the visual style and whether a label or arrowhead is present.\n\n### 3.1 Edge types\n\n```\nflowchart TD\n  A --> B\n  C --- D\n  E -.-> F\n  G ==> H\n  I <--> J\n  K --x L\n  M --o N\n```\n\n| Syntax | Style | Arrow | Typical use |\n|---|---|---|---|\n| `A --> B` | Solid | Arrow | Normal flow |\n| `A --- B` | Solid | None | Association, undirected link |\n| `A -.-> B` | Dotted | Arrow | Optional / async path |\n| `A ==> B` | Thick | Arrow | Critical / primary path |\n| `A <--> B` | Solid | Both ends | Bidirectional flow |\n| `A --x B` | Solid | Cross | Blocked / rejected path |\n| `A --o B` | Solid | Circle | Aggregation / composition |\n\n### 3.2 Edge labels\n\nTwo syntaxes attach a label to an edge:\n\n**Pipe label** \u2014 placed between `|` characters directly after the arrow:\n```\nA -->|Yes| B\nA -.->|optional| B\nA ==>|critical| B\n```\n\n**Inline label** \u2014 text placed between the dashes, before the arrow character:\n```\nA -- success --> B\nA -- error --x C\n```\n\nBoth produce identical results. Pipe label is more common when sharing a diagram with Mermaid tools.\n\n```\nflowchart TD\n  req[Request received]\n  req -->|valid| proc[Process]\n  req -->|invalid| err[Return 400]\n  proc -- success --> ok([Done])\n  proc -.->|timeout| retry[Retry queue]\n  retry ==>|max retries| dead[(Dead letter)]\n```\n\n### 3.3 Chains\n\nConnect three or more nodes in a single line:\n\n```\nA --> B --> C --> D\n```\n\nThis is equivalent to three separate edge statements.\n\n### 3.4 Fan-out with `&`\n\nUse `&` to include multiple nodes on either side of an arrow. The parser generates the full cross-product of edges:\n\n```\nA & B --> C        %% A\u2192C and B\u2192C\nA --> B & C        %% A\u2192B and A\u2192C\nA & B --> C & D    %% four edges: A\u2192C, A\u2192D, B\u2192C, B\u2192D\n```\n\n```\nflowchart LR\n  deploy[Deploy service]\n  smoke[Smoke test]\n  health[Health check]\n  notify_slack[Slack alert]\n  notify_email[Email alert]\n  deploy --> smoke & health\n  smoke & health -->|fail| notify_slack & notify_email\n```\n\n---\n\n## 4. Subgraphs\n\nA `subgraph` groups related nodes into a labeled cluster with a visible border.\n\n```\nsubgraph "Title"\n  A --> B\nend\n```\n\nThree subgraph header forms are accepted:\n\n| Form | ID | Label |\n|---|---|---|\n| `subgraph "My Group"` | auto-generated | `My Group` |\n| `subgraph sg1 "My Group"` | `sg1` | `My Group` |\n| `subgraph sg1 [My Group]` | `sg1` | `My Group` |\n\nSubgraphs can have their own `direction` override:\n\n```\nsubgraph sg1 "Frontend"\n  direction LR\n  ui[React App] --> api[API Client]\nend\n```\n\n```\nflowchart TB\n  subgraph ingestion [Ingestion]\n    raw[/Raw events/] --> parse[Parse & validate]\n    parse --> enrich[Enrich]\n  end\n  subgraph storage [Storage]\n    dw[(Data warehouse)]\n    cache[(Redis cache)]\n  end\n  enrich --> dw\n  enrich --> cache\n  dw --> report[Generate report]\n```\n\n---\n\n## 5. Styling\n\n### 5.1 Semantic classes\n\nAssign CSS class names to nodes for theme-level visual grouping. Classes are defined with `classDef` and applied with `class`.\n\n```\nclassDef danger fill:#f9c,stroke:#c00\nclassDef safe fill:#cfc,stroke:#090\nclass errorNode danger\nclass successNode safe\n```\n\n### 5.2 Per-node style overrides\n\n```\nstyle nodeId fill:#f9f,stroke:#333,stroke-width:4px\n```\n\nAccepts standard CSS property names. Multiple properties are comma-separated.\n\n---\n\n## 6. Labels & comments\n\n- **Direction:** `flowchart TD` \u2014 first token after `flowchart` or `graph`. `TD` and `TB` are equivalent.\n- **Title:** `flowchart LR "My diagram"` \u2014 optional quoted string after the direction.\n- **Edge labels:** pipe syntax `-->|label|` or inline `-- label -->`.\n- **Comments:** `%%` at the start of a line (after leading whitespace).\n\n```\nflowchart LR\n%% This is a comment \u2014 ignored by the parser\nA[Step 1] --> B[Step 2]  %% inline %% is NOT supported \u2014 only line-start %%\n```\n\n---\n\n## 7. Reserved words & escaping\n\n**Reserved at line start:** `flowchart`, `graph` (header), `subgraph`, `end`, `direction`, `class`, `classDef`, `style`, `linkStyle`.\n\n**Reserved ID characters:** IDs match `[A-Za-z0-9_-]` starting with a letter. Do not use spaces or operator characters in node IDs.\n\n**Operator tokens to avoid inside IDs:** `-->`, `---`, `-.->`, `==>`, `<-->`, `--x`, `--o`, `|`, `&`.\n\n**Labels with special characters:** The label is everything inside the shape brackets. Special characters are supported inside labels as-is \u2014 brackets/braces that would be ambiguous are closed by the matching closing token.\n\n---\n\n## 8. Common mistakes\n\n| You wrote | Parser says | Fix |\n|---|---|---|\n| `flowchart` with no direction | Direction defaults to `TB` | Add a direction: `flowchart TD` |\n| `A --> B` before declaring shapes | Works \u2014 nodes created as rectangles with the ID as label | Declare explicitly when you need a non-rect shape: `A([Start])` |\n| `A[Label with [brackets]]` | Inner `]` closes the shape early | Avoid nested brackets in labels |\n| `subgraph My Group` (unquoted, with space) | Parser takes `My` as subgraph id, `Group` as unknown token | Quote: `subgraph "My Group"` |\n| `%% comment` mid-line after code | Inline comments are not supported; `%%` must be at line start | Move comments to their own line |\n| `A --> B --> C` mixed with `A --> B` | Chains are additive \u2014 duplicate edges may appear | Use chains OR separate lines, not both for the same pair |\n| `direction LR` outside a subgraph | Silently ignored \u2014 `direction` override only applies inside `subgraph \u2026 end` | Set direction on the `flowchart` header line |\n\n---\n\n## 9. Grammar (EBNF)\n\n```text\ndocument       = header (blank | comment | subgraph-block | direction-stmt\n                        | class-stmt | classdef-stmt | style-stmt\n                        | linkstyle-stmt | chain-stmt)*\n\nheader         = ("flowchart" | "graph") ( WS direction )? ( WS title )? NEWLINE\ndirection      = "TD" | "TB" | "BT" | "LR" | "RL"\ntitle          = \'"\' any-char-but-quote* \'"\' | bare-word\n\nsubgraph-block = "subgraph" ( WS subgraph-header )? NEWLINE\n                   ( WS? "direction" WS direction NEWLINE )?\n                   statement*\n                 "end" NEWLINE\nsubgraph-header = id WS "[" label "]"\n                | id WS quoted-string\n                | quoted-string\n                | id\n\nchain-stmt     = node-group ( WS edge-op WS pipe-label? WS node-group )* NEWLINE\nnode-group     = node-ref ( WS "&" WS node-ref )*\nnode-ref       = id shape-suffix?\nshape-suffix   = "[" label "]"          %% rect\n               | "(" label ")"          %% round\n               | "([" label "])"        %% stadium\n               | "{" label "}"          %% diamond\n               | "{{" label "}}"        %% hexagon\n               | "[[" label "]]"        %% subroutine\n               | "[(" label ")]"        %% cylinder\n               | "((" label "))"        %% circle\n               | "(((" label ")))"      %% double-circle\n               | "[/" label "/]"        %% parallelogram\n               | "[\\" label "\\]"        %% parallelogram-alt\n               | "[/" label "\\]"        %% trapezoid\n               | "[\\" label "/]"        %% trapezoid-alt\n               | ">" label "]"          %% asymmetric\n\nedge-op        = "-->" | "---" | "-."-".->" | "==>" | "<-->" | "--x" | "--o"\n               | inline-label variants of the above\npipe-label     = "|" text "|"\n\nclass-stmt     = "class" WS id-list WS class-name NEWLINE\nclassdef-stmt  = "classDef" WS class-name WS css-props NEWLINE\nstyle-stmt     = "style" WS id WS css-props NEWLINE\nlinkstyle-stmt = "linkStyle" WS ...    %% parsed but not yet rendered\n\ncomment        = "%%" any NEWLINE\nid             = [A-Za-z] [A-Za-z0-9_-]*\n```\n\nAuthoritative source: `src/diagrams/flowchart/parser.ts`. If this diverges from the parser, the parser wins \u2014 please open an issue.\n\n---'
+    "content": '## 1. Your first flowchart\n\nThe smallest useful flowchart: a decision with two outcomes.\n\n```\nflowchart TD\n  A([Start]) --> B{File exists?}\n  B -->|Yes| C[Read file]\n  B -->|No| D[Return error]\n  C --> E([Done])\n```\n\nFour rules cover 80% of usage:\n\n1. Start with `flowchart` followed by a direction: `TD`, `LR`, `BT`, or `RL`.\n2. Each node is `ID[Label]` \u2014 the shape brackets determine the node type (see \xA72).\n3. Connect nodes with `-->`. Add a label between pipe characters: `-->|Yes|`.\n4. Nodes are created automatically when first referenced in an edge \u2014 but explicit declarations let you set shapes and labels independently.\n\n> Comments start with `%%` on their own line.\n\n---\n\n## 2. Node shapes\n\nEach node shape is written as `ID<brackets>Label<brackets>`. The ID must start with a letter and may contain letters, digits, `_`, and `-`.\n\n| Syntax | Shape | Typical use |\n|---|---|---|\n| `A[Label]` | Rectangle | Process step, operation |\n| `A(Label)` | Rounded rectangle | Subprocess, soft step |\n| `A([Label])` | Stadium (pill) | Start / end terminal |\n| `A{Label}` | Diamond | Decision / condition |\n| `A{{Label}}` | Hexagon | Preparation, configuration |\n| `A[[Label]]` | Subroutine | Predefined process |\n| `A[(Label)]` | Cylinder | Database, storage |\n| `A((Label))` | Circle | Connector, junction |\n| `A(((Label)))` | Double circle | End state |\n| `A[/Label/]` | Parallelogram | Input / output |\n| `A[\\Label\\]` | Parallelogram (alt) | Manual operation |\n| `A[/Label\\]` | Trapezoid | Manual input |\n| `A[\\Label/]` | Trapezoid (alt) | Off-page connector |\n| `A>Label]` | Asymmetric | Tag, annotation |\n\n```\nflowchart TD\n  t([Terminal / stadium])\n  r[Rectangle process]\n  d{Diamond decision}\n  p[/Parallelogram input/]\n  db[(Cylinder database)]\n  sub[[Subroutine]]\n  t --> r --> d\n  d -->|branch A| p\n  d -->|branch B| db\n  p --> sub\n  db --> sub\n```\n\n---\n\n## 3. Edges\n\nAn edge connects two nodes. The connector symbol determines the visual style and whether a label or arrowhead is present.\n\n### 3.1 Edge types\n\n```\nflowchart TD\n  A --> B\n  C --- D\n  E -.-> F\n  G ==> H\n  I <--> J\n  K --x L\n  M --o N\n```\n\n| Syntax | Style | Arrow | Typical use |\n|---|---|---|---|\n| `A --> B` | Solid | Arrow | Normal flow |\n| `A --- B` | Solid | None | Association, undirected link |\n| `A -.-> B` | Dotted | Arrow | Optional / async path |\n| `A ==> B` | Thick | Arrow | Critical / primary path |\n| `A <--> B` | Solid | Both ends | Bidirectional flow |\n| `A --x B` | Solid | Cross | Blocked / rejected path |\n| `A --o B` | Solid | Circle | Aggregation / composition |\n\n### 3.2 Edge labels\n\nTwo syntaxes attach a label to an edge:\n\n**Pipe label** \u2014 placed between `|` characters directly after the arrow:\n```\nA -->|Yes| B\nA -.->|optional| B\nA ==>|critical| B\n```\n\n**Inline label** \u2014 text placed between the dashes, before the arrow character:\n```\nA -- success --> B\nA -- error --x C\n```\n\nBoth produce identical results. Pipe label is more common when sharing a diagram with Mermaid tools.\n\n```\nflowchart TD\n  req[Request received]\n  req -->|valid| proc[Process]\n  req -->|invalid| err[Return 400]\n  proc -- success --> ok([Done])\n  proc -.->|timeout| retry[Retry queue]\n  retry ==>|max retries| dead[(Dead letter)]\n```\n\n### 3.3 Chains\n\nConnect three or more nodes in a single line:\n\n```\nA --> B --> C --> D\n```\n\nThis is equivalent to three separate edge statements.\n\n### 3.4 Fan-out with `&`\n\nUse `&` to include multiple nodes on either side of an arrow. The parser generates the full cross-product of edges:\n\n```\nA & B --> C        %% A\u2192C and B\u2192C\nA --> B & C        %% A\u2192B and A\u2192C\nA & B --> C & D    %% four edges: A\u2192C, A\u2192D, B\u2192C, B\u2192D\n```\n\n```\nflowchart LR\n  deploy[Deploy service]\n  smoke[Smoke test]\n  health[Health check]\n  notify_slack[Slack alert]\n  notify_email[Email alert]\n  deploy --> smoke & health\n  smoke & health -->|fail| notify_slack & notify_email\n```\n\n---\n\n## 4. Subgraphs\n\nA `subgraph` groups related nodes into a labeled cluster with a visible border.\n\n```\nsubgraph "Title"\n  A --> B\nend\n```\n\nThree subgraph header forms are accepted:\n\n| Form | ID | Label |\n|---|---|---|\n| `subgraph "My Group"` | auto-generated | `My Group` |\n| `subgraph sg1 "My Group"` | `sg1` | `My Group` |\n| `subgraph sg1 [My Group]` | `sg1` | `My Group` |\n\nSubgraphs can have their own `direction` override:\n\n```\nsubgraph sg1 "Frontend"\n  direction LR\n  ui[React App] --> api[API Client]\nend\n```\n\n```\nflowchart TB\n  subgraph ingestion [Ingestion]\n    raw[/Raw events/] --> parse[Parse & validate]\n    parse --> enrich[Enrich]\n  end\n  subgraph storage [Storage]\n    dw[(Data warehouse)]\n    cache[(Redis cache)]\n  end\n  enrich --> dw\n  enrich --> cache\n  dw --> report[Generate report]\n```\n\n---\n\n## 5. Styling\n\n### 5.1 Semantic classes\n\nAssign CSS class names to nodes for theme-level visual grouping. Classes are defined with `classDef` and applied with `class`.\n\n```\nclassDef danger fill:#f9c,stroke:#c00\nclassDef safe fill:#cfc,stroke:#090\nclass errorNode danger\nclass successNode safe\n```\n\n### 5.2 Per-node style overrides\n\n```\nstyle nodeId fill:#f9f,stroke:#333,stroke-width:4px\n```\n\nAccepts standard CSS property names. Multiple properties are comma-separated.\n\n### 5.3 Per-edge style overrides\n\n`linkStyle` targets edges by their **declaration index** (0-based, in the order they appear in the source). Multiple comma-separated indices apply the same props to several edges:\n\n```\nflowchart TD\n  A --> B\n  B ==> C\n  B -.-> D\n  C --> E\n  D --> E\n  linkStyle 1 stroke:#d32f2f,stroke-width:4px\n  linkStyle 2,4 stroke:#f57c00,stroke-dasharray:5 5\n```\n\nUse this to highlight a critical path or distinguish an alternate flow.\n\n### 5.4 Inline label formatting\n\nNode labels accept three inline formatting tags:\n\n| Tag | Effect |\n|---|---|\n| `<br/>` or `<br>` | Line break |\n| `<b>\u2026</b>` | Bold |\n| `<i>\u2026</i>` | Italic |\n\n```\nflowchart TD\n  M1["0 \\| 0<br/><b>START</b>"]\n  M2["4 \\| 4<br/><b>Phase 1</b><br/><i>est. 4h</i>"]\n  M1 --> M2\n```\n\nTags can be nested and mixed mid-line (`Hello <b>world</b>!`). Edge labels are single-line and do not currently support these tags.\n\n---\n\n## 6. Labels & comments\n\n- **Direction:** `flowchart TD` \u2014 first token after `flowchart` or `graph`. `TD` and `TB` are equivalent.\n- **Title:** `flowchart LR "My diagram"` \u2014 optional quoted string after the direction.\n- **Edge labels:** pipe syntax `-->|label|` or inline `-- label -->`.\n- **Comments:** `%%` at the start of a line (after leading whitespace).\n\n```\nflowchart LR\n%% This is a comment \u2014 ignored by the parser\nA[Step 1] --> B[Step 2]  %% inline %% is NOT supported \u2014 only line-start %%\n```\n\n---\n\n## 7. Reserved words & escaping\n\n**Reserved at line start:** `flowchart`, `graph` (header), `subgraph`, `end`, `direction`, `class`, `classDef`, `style`, `linkStyle`.\n\n**Reserved ID characters:** IDs match `[A-Za-z0-9_-]` starting with a letter. Do not use spaces or operator characters in node IDs.\n\n**Operator tokens to avoid inside IDs:** `-->`, `---`, `-.->`, `==>`, `<-->`, `--x`, `--o`, `|`, `&`.\n\n**Labels with special characters:** The label is everything inside the shape brackets. Special characters are supported inside labels as-is \u2014 brackets/braces that would be ambiguous are closed by the matching closing token.\n\n---\n\n## 8. Common mistakes\n\n| You wrote | Parser says | Fix |\n|---|---|---|\n| `flowchart` with no direction | Direction defaults to `TB` | Add a direction: `flowchart TD` |\n| `A --> B` before declaring shapes | Works \u2014 nodes created as rectangles with the ID as label | Declare explicitly when you need a non-rect shape: `A([Start])` |\n| `A[Label with [brackets]]` | Inner `]` closes the shape early | Avoid nested brackets in labels |\n| `subgraph My Group` (unquoted, with space) | Parser takes `My` as subgraph id, `Group` as unknown token | Quote: `subgraph "My Group"` |\n| `%% comment` mid-line after code | Inline comments are not supported; `%%` must be at line start | Move comments to their own line |\n| `A --> B --> C` mixed with `A --> B` | Chains are additive \u2014 duplicate edges may appear | Use chains OR separate lines, not both for the same pair |\n| `direction LR` outside a subgraph | Silently ignored \u2014 `direction` override only applies inside `subgraph \u2026 end` | Set direction on the `flowchart` header line |\n\n---\n\n## 9. Grammar (EBNF)\n\n```text\ndocument       = header (blank | comment | subgraph-block | direction-stmt\n                        | class-stmt | classdef-stmt | style-stmt\n                        | linkstyle-stmt | chain-stmt)*\n\nheader         = ("flowchart" | "graph") ( WS direction )? ( WS title )? NEWLINE\ndirection      = "TD" | "TB" | "BT" | "LR" | "RL"\ntitle          = \'"\' any-char-but-quote* \'"\' | bare-word\n\nsubgraph-block = "subgraph" ( WS subgraph-header )? NEWLINE\n                   ( WS? "direction" WS direction NEWLINE )?\n                   statement*\n                 "end" NEWLINE\nsubgraph-header = id WS "[" label "]"\n                | id WS quoted-string\n                | quoted-string\n                | id\n\nchain-stmt     = node-group ( WS edge-op WS pipe-label? WS node-group )* NEWLINE\nnode-group     = node-ref ( WS "&" WS node-ref )*\nnode-ref       = id shape-suffix?\nshape-suffix   = "[" label "]"          %% rect\n               | "(" label ")"          %% round\n               | "([" label "])"        %% stadium\n               | "{" label "}"          %% diamond\n               | "{{" label "}}"        %% hexagon\n               | "[[" label "]]"        %% subroutine\n               | "[(" label ")]"        %% cylinder\n               | "((" label "))"        %% circle\n               | "(((" label ")))"      %% double-circle\n               | "[/" label "/]"        %% parallelogram\n               | "[\\" label "\\]"        %% parallelogram-alt\n               | "[/" label "\\]"        %% trapezoid\n               | "[\\" label "/]"        %% trapezoid-alt\n               | ">" label "]"          %% asymmetric\n\nedge-op        = "-->" | "---" | "-."-".->" | "==>" | "<-->" | "--x" | "--o"\n               | inline-label variants of the above\npipe-label     = "|" text "|"\n\nclass-stmt     = "class" WS id-list WS class-name NEWLINE\nclassdef-stmt  = "classDef" WS class-name WS css-props NEWLINE\nstyle-stmt     = "style" WS id WS css-props NEWLINE\nlinkstyle-stmt = "linkStyle" WS index-list WS css-props NEWLINE\nindex-list     = NUMBER ( "," NUMBER )* | "default"\n\ncomment        = "%%" any NEWLINE\nid             = [A-Za-z] [A-Za-z0-9_-]*\n```\n\nAuthoritative source: `src/diagrams/flowchart/parser.ts`. If this diverges from the parser, the parser wins \u2014 please open an issue.\n\n---'
   },
   "matrix": {
     "title": "Matrix / Quadrant diagram",
@@ -1154,5 +1154,5 @@ function resolveTypeFromText(text) {
 }
 
 export { DIAGRAM_REGISTRY, getAllDiagramTypes, getDiagramMeta, getExamples, getSyntax, listDiagrams, renderDsl, validateDsl };
-//# sourceMappingURL=chunk-H4CJTKEH.js.map
-//# sourceMappingURL=chunk-H4CJTKEH.js.map
+//# sourceMappingURL=chunk-MNOO7STY.js.map
+//# sourceMappingURL=chunk-MNOO7STY.js.map