rp2040js 0.19.4 → 1.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/cjs/clock/clock.d.ts +6 -8
- package/dist/cjs/clock/mock-clock.d.ts +2 -15
- package/dist/cjs/clock/mock-clock.js +4 -46
- package/dist/cjs/clock/simulation-clock.d.ts +26 -0
- package/dist/cjs/clock/simulation-clock.js +97 -0
- package/dist/cjs/cortex-m0-core.d.ts +1 -1
- package/dist/cjs/cortex-m0-core.js +39 -37
- package/dist/cjs/gdb/gdb-connection.d.ts +1 -1
- package/dist/cjs/gdb/gdb-connection.js +2 -2
- package/dist/cjs/gdb/gdb-server.d.ts +3 -3
- package/dist/cjs/gdb/gdb-server.js +12 -11
- package/dist/cjs/gdb/gdb-target.d.ts +7 -0
- package/dist/cjs/gdb/gdb-target.js +2 -0
- package/dist/cjs/gdb/gdb-tcp-server.d.ts +2 -2
- package/dist/cjs/gdb/gdb-tcp-server.js +2 -2
- package/dist/cjs/index.d.ts +4 -3
- package/dist/cjs/index.js +7 -5
- package/dist/cjs/peripherals/adc.d.ts +7 -2
- package/dist/cjs/peripherals/adc.js +12 -8
- package/dist/cjs/peripherals/dma.d.ts +1 -1
- package/dist/cjs/peripherals/dma.js +6 -15
- package/dist/cjs/peripherals/rtc.d.ts +1 -1
- package/dist/cjs/peripherals/rtc.js +3 -3
- package/dist/cjs/peripherals/timer.js +12 -17
- package/dist/cjs/peripherals/usb.d.ts +4 -0
- package/dist/cjs/peripherals/usb.js +56 -50
- package/dist/cjs/rp2040.d.ts +0 -5
- package/dist/cjs/rp2040.js +2 -27
- package/dist/cjs/simulator.d.ts +13 -0
- package/dist/cjs/simulator.js +45 -0
- package/dist/cjs/utils/timer32.d.ts +3 -3
- package/dist/cjs/utils/timer32.js +14 -16
- package/dist/esm/clock/clock.d.ts +6 -8
- package/dist/esm/clock/mock-clock.d.ts +2 -15
- package/dist/esm/clock/mock-clock.js +3 -44
- package/dist/esm/clock/simulation-clock.d.ts +26 -0
- package/dist/esm/clock/simulation-clock.js +92 -0
- package/dist/esm/cortex-m0-core.d.ts +1 -1
- package/dist/esm/cortex-m0-core.js +39 -37
- package/dist/esm/gdb/gdb-connection.d.ts +1 -1
- package/dist/esm/gdb/gdb-connection.js +2 -2
- package/dist/esm/gdb/gdb-server.d.ts +3 -3
- package/dist/esm/gdb/gdb-server.js +12 -11
- package/dist/esm/gdb/gdb-target.d.ts +7 -0
- package/dist/esm/gdb/gdb-target.js +1 -0
- package/dist/esm/gdb/gdb-tcp-server.d.ts +2 -2
- package/dist/esm/gdb/gdb-tcp-server.js +2 -2
- package/dist/esm/index.d.ts +4 -3
- package/dist/esm/index.js +2 -1
- package/dist/esm/peripherals/adc.d.ts +7 -2
- package/dist/esm/peripherals/adc.js +12 -8
- package/dist/esm/peripherals/dma.d.ts +1 -1
- package/dist/esm/peripherals/dma.js +6 -15
- package/dist/esm/peripherals/rtc.d.ts +1 -1
- package/dist/esm/peripherals/rtc.js +3 -3
- package/dist/esm/peripherals/timer.js +12 -17
- package/dist/esm/peripherals/usb.d.ts +4 -0
- package/dist/esm/peripherals/usb.js +56 -50
- package/dist/esm/rp2040.d.ts +0 -5
- package/dist/esm/rp2040.js +2 -27
- package/dist/esm/simulator.d.ts +13 -0
- package/dist/esm/simulator.js +41 -0
- package/dist/esm/utils/timer32.d.ts +3 -3
- package/dist/esm/utils/timer32.js +14 -16
- package/package.json +1 -1
- package/dist/cjs/clock/realtime-clock.d.ts +0 -23
- package/dist/cjs/clock/realtime-clock.js +0 -73
- package/dist/esm/clock/realtime-clock.d.ts +0 -23
- package/dist/esm/clock/realtime-clock.js +0 -68
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@@ -8,7 +8,7 @@ export declare class Timer32 {
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readonly clock: IClock;
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private baseFreq;
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private baseValue;
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private
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private baseNanos;
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private topValue;
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private prescalerValue;
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private timerMode;
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@@ -32,7 +32,7 @@ export declare class Timer32 {
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set frequency(value: number);
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get prescaler(): number;
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set prescaler(value: number);
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toNanos(cycles: number): number;
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get enable(): boolean;
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set enable(value: boolean);
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get mode(): TimerMode;
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@@ -44,7 +44,7 @@ export declare class Timer32PeriodicAlarm {
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readonly callback: () => void;
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private targetValue;
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private enabled;
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private
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private clockAlarm;
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constructor(timer: Timer32, callback: () => void);
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get enable(): boolean;
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set enable(value: boolean);
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@@ -12,7 +12,7 @@ class Timer32 {
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this.clock = clock;
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this.baseFreq = baseFreq;
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this.baseValue = 0;
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this.
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this.baseNanos = 0;
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this.topValue = 0xffffffff;
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this.prescalerValue = 1;
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this.timerMode = TimerMode.Increment;
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@@ -20,13 +20,13 @@ class Timer32 {
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this.listeners = [];
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}
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reset() {
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this.
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this.baseNanos = this.clock.nanos;
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this.baseValue = 0;
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this.updated();
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}
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set(value, zigZagDown = false) {
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this.baseValue = zigZagDown ? this.topValue * 2 - value : value;
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this.
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this.baseNanos = this.clock.nanos;
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this.updated();
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}
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/**
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@@ -39,12 +39,12 @@ class Timer32 {
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this.baseValue += delta;
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}
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get rawCounter() {
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const { baseFreq, prescalerValue,
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const { baseFreq, prescalerValue, baseNanos, baseValue, enabled, timerMode } = this;
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if (!baseFreq || !prescalerValue || !enabled) {
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return this.baseValue;
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}
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const zigzag = timerMode == TimerMode.ZigZag;
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const ticks = ((this.clock.
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const ticks = ((this.clock.nanos - baseNanos) / 1e9) * (baseFreq / prescalerValue);
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const topModulo = zigzag ? this.topValue * 2 : this.topValue + 1;
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const delta = timerMode == TimerMode.Decrement ? topModulo - (ticks % topModulo) : ticks;
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let currentValue = Math.round(baseValue + delta);
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@@ -73,7 +73,7 @@ class Timer32 {
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}
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set frequency(value) {
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this.baseValue = this.counter;
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this.
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this.baseNanos = this.clock.nanos;
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this.baseFreq = value;
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this.updated();
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}
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}
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set prescaler(value) {
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this.baseValue = this.counter;
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this.
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this.baseNanos = this.clock.nanos;
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this.enabled = this.prescalerValue !== 0;
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this.prescalerValue = value;
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this.updated();
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}
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toNanos(cycles) {
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const { baseFreq, prescalerValue } = this;
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return (cycles *
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return (cycles * 1e9) / (baseFreq / prescalerValue);
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}
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get enable() {
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return this.enabled;
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set enable(value) {
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if (value !== this.enabled) {
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if (value) {
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this.
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this.baseNanos = this.clock.nanos;
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}
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else {
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this.baseValue = this.counter;
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@@ -141,6 +141,7 @@ class Timer32PeriodicAlarm {
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this.schedule();
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}
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};
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this.clockAlarm = this.timer.clock.createAlarm(this.handleAlarm);
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timer.listeners.push(this.update);
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}
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get enable() {
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@@ -195,14 +196,11 @@ class Timer32PeriodicAlarm {
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cycleDelta = top + 1 - cycleDelta;
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}
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const cyclesToAlarm = cycleDelta >>> 0;
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const
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this.
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const nanosToAlarm = timer.toNanos(cyclesToAlarm);
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this.clockAlarm.schedule(nanosToAlarm);
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}
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cancel() {
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this.timer.clock.deleteTimer(this.clockTimer);
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this.clockTimer = undefined;
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}
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this.clockAlarm.cancel();
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}
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}
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exports.Timer32PeriodicAlarm = Timer32PeriodicAlarm;
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export
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export type AlarmCallback = () => void;
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export interface IAlarm {
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schedule(deltaNanos: number): void;
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cancel(): void;
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}
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export interface IClock {
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readonly
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resume(): void;
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createTimer(deltaMicros: number, callback: () => void): IClockTimer;
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deleteTimer(timer: IClockTimer): void;
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readonly nanos: number;
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createAlarm(callback: AlarmCallback): IAlarm;
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}
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import {
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export declare class
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readonly micros: number;
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readonly callback: () => void;
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constructor(micros: number, callback: () => void);
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pause(): void;
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resume(): void;
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}
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export declare class MockClock implements IClock {
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micros: number;
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readonly timers: MockClockTimer[];
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pause(): void;
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resume(): void;
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import { SimulationClock } from './simulation-clock.js';
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export declare class MockClock extends SimulationClock {
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advance(deltaMicros: number): void;
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createTimer(deltaMicros: number, callback: () => void): MockClockTimer;
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deleteTimer(timer: IClockTimer): void;
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this.micros = micros;
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}
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pause() {
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}
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resume() {
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}
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export class MockClock {
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constructor() {
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this.micros = 0;
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this.timers = [];
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}
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pause() {
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}
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resume() {
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}
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import { SimulationClock } from './simulation-clock.js';
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export class MockClock extends SimulationClock {
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advance(deltaMicros) {
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const targetTime = this.micros + Math.max(deltaMicros, 0.01);
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while (timers[0] && timers[0].micros <= targetTime) {
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const timer = timers.shift();
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if (timer) {
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}
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}
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}
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createTimer(deltaMicros, callback) {
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const timer = new MockClockTimer(this.micros + deltaMicros, callback);
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this.timers.sort((a, b) => a.micros - b.micros);
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}
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deleteTimer(timer) {
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}
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this.tick(this.nanos + deltaMicros * 1000);
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import { AlarmCallback, IAlarm, IClock } from './clock.js';
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type ClockEventCallback = () => void;
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export declare class ClockAlarm implements IAlarm {
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private readonly clock;
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readonly callback: AlarmCallback;
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next: ClockAlarm | null;
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nanos: number;
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scheduled: boolean;
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constructor(clock: SimulationClock, callback: AlarmCallback);
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schedule(deltaNanos: number): void;
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cancel(): void;
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}
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export declare class SimulationClock implements IClock {
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readonly frequency: number;
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private nextAlarm;
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private nanosCounter;
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constructor(frequency?: number);
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get nanos(): number;
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get micros(): number;
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createAlarm(callback: ClockEventCallback): ClockAlarm;
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linkAlarm(nanos: number, alarm: ClockAlarm): ClockAlarm;
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unlinkAlarm(alarm: ClockAlarm): boolean;
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tick(deltaNanos: number): void;
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get nanosToNextAlarm(): number;
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}
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export {};
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export class ClockAlarm {
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constructor(clock, callback) {
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this.clock = clock;
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this.callback = callback;
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this.next = null;
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this.nanos = 0;
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this.scheduled = false;
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}
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schedule(deltaNanos) {
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if (this.scheduled) {
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this.cancel();
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}
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this.clock.linkAlarm(deltaNanos, this);
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}
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cancel() {
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this.clock.unlinkAlarm(this);
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this.scheduled = false;
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}
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}
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export class SimulationClock {
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constructor(frequency = 125e6) {
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this.frequency = frequency;
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this.nextAlarm = null;
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this.nanosCounter = 0;
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}
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get nanos() {
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return this.nanosCounter;
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}
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get micros() {
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return this.nanos / 1000;
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}
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createAlarm(callback) {
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|
+
return new ClockAlarm(this, callback);
|
|
34
|
+
}
|
|
35
|
+
linkAlarm(nanos, alarm) {
|
|
36
|
+
alarm.nanos = this.nanos + nanos;
|
|
37
|
+
let alarmListItem = this.nextAlarm;
|
|
38
|
+
let lastItem = null;
|
|
39
|
+
while (alarmListItem && alarmListItem.nanos < alarm.nanos) {
|
|
40
|
+
lastItem = alarmListItem;
|
|
41
|
+
alarmListItem = alarmListItem.next;
|
|
42
|
+
}
|
|
43
|
+
if (lastItem) {
|
|
44
|
+
lastItem.next = alarm;
|
|
45
|
+
alarm.next = alarmListItem;
|
|
46
|
+
}
|
|
47
|
+
else {
|
|
48
|
+
this.nextAlarm = alarm;
|
|
49
|
+
alarm.next = alarmListItem;
|
|
50
|
+
}
|
|
51
|
+
alarm.scheduled = true;
|
|
52
|
+
return alarm;
|
|
53
|
+
}
|
|
54
|
+
unlinkAlarm(alarm) {
|
|
55
|
+
let alarmListItem = this.nextAlarm;
|
|
56
|
+
if (!alarmListItem) {
|
|
57
|
+
return false;
|
|
58
|
+
}
|
|
59
|
+
let lastItem = null;
|
|
60
|
+
while (alarmListItem) {
|
|
61
|
+
if (alarmListItem === alarm) {
|
|
62
|
+
if (lastItem) {
|
|
63
|
+
lastItem.next = alarmListItem.next;
|
|
64
|
+
}
|
|
65
|
+
else {
|
|
66
|
+
this.nextAlarm = alarmListItem.next;
|
|
67
|
+
}
|
|
68
|
+
return true;
|
|
69
|
+
}
|
|
70
|
+
lastItem = alarmListItem;
|
|
71
|
+
alarmListItem = alarmListItem.next;
|
|
72
|
+
}
|
|
73
|
+
return false;
|
|
74
|
+
}
|
|
75
|
+
tick(deltaNanos) {
|
|
76
|
+
const targetNanos = this.nanosCounter + deltaNanos;
|
|
77
|
+
let alarm = this.nextAlarm;
|
|
78
|
+
while (alarm && alarm.nanos <= targetNanos) {
|
|
79
|
+
this.nextAlarm = alarm.next;
|
|
80
|
+
this.nanosCounter = alarm.nanos;
|
|
81
|
+
alarm.callback();
|
|
82
|
+
alarm = this.nextAlarm;
|
|
83
|
+
}
|
|
84
|
+
this.nanosCounter = targetNanos;
|
|
85
|
+
}
|
|
86
|
+
get nanosToNextAlarm() {
|
|
87
|
+
if (this.nextAlarm) {
|
|
88
|
+
return this.nextAlarm.nanos - this.nanos;
|
|
89
|
+
}
|
|
90
|
+
return 0;
|
|
91
|
+
}
|
|
92
|
+
}
|
|
@@ -526,7 +526,7 @@ export class CortexM0Core {
|
|
|
526
526
|
const wideInstruction = opcode >> 12 === 0b1111 || opcode >> 11 === 0b11101;
|
|
527
527
|
const opcode2 = wideInstruction ? this.readUint16(opcodePC + 2) : 0;
|
|
528
528
|
this.PC += 2;
|
|
529
|
-
|
|
529
|
+
let deltaCycles = 1;
|
|
530
530
|
// ADCS
|
|
531
531
|
if (opcode >> 6 === 0b0100000101) {
|
|
532
532
|
const Rm = (opcode >> 3) & 0x7;
|
|
@@ -576,7 +576,7 @@ export class CortexM0Core {
|
|
|
576
576
|
}
|
|
577
577
|
else if (Rdn === pcRegister) {
|
|
578
578
|
this.registers[Rdn] = result & ~0x1;
|
|
579
|
-
|
|
579
|
+
deltaCycles++;
|
|
580
580
|
}
|
|
581
581
|
else if (Rdn === spRegister) {
|
|
582
582
|
this.registers[Rdn] = result & ~0x3;
|
|
@@ -631,7 +631,7 @@ export class CortexM0Core {
|
|
|
631
631
|
}
|
|
632
632
|
if (this.checkCondition(cond)) {
|
|
633
633
|
this.PC += imm8 + 2;
|
|
634
|
-
|
|
634
|
+
deltaCycles++;
|
|
635
635
|
}
|
|
636
636
|
}
|
|
637
637
|
// B
|
|
@@ -641,7 +641,7 @@ export class CortexM0Core {
|
|
|
641
641
|
imm11 = (imm11 & 0x7ff) - 0x800;
|
|
642
642
|
}
|
|
643
643
|
this.PC += imm11 + 2;
|
|
644
|
-
|
|
644
|
+
deltaCycles++;
|
|
645
645
|
}
|
|
646
646
|
// BICS
|
|
647
647
|
else if (opcode >> 6 === 0b0100001110) {
|
|
@@ -669,7 +669,7 @@ export class CortexM0Core {
|
|
|
669
669
|
const imm32 = ((S ? 0b11111111 : 0) << 24) | ((I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1));
|
|
670
670
|
this.LR = (this.PC + 2) | 0x1;
|
|
671
671
|
this.PC += 2 + imm32;
|
|
672
|
-
|
|
672
|
+
deltaCycles += 2;
|
|
673
673
|
this.blTaken(this, false);
|
|
674
674
|
}
|
|
675
675
|
// BLX
|
|
@@ -677,14 +677,14 @@ export class CortexM0Core {
|
|
|
677
677
|
const Rm = (opcode >> 3) & 0xf;
|
|
678
678
|
this.LR = this.PC | 0x1;
|
|
679
679
|
this.PC = this.registers[Rm] & ~1;
|
|
680
|
-
|
|
680
|
+
deltaCycles++;
|
|
681
681
|
this.blTaken(this, true);
|
|
682
682
|
}
|
|
683
683
|
// BX
|
|
684
684
|
else if (opcode >> 7 === 0b010001110 && (opcode & 0x7) === 0) {
|
|
685
685
|
const Rm = (opcode >> 3) & 0xf;
|
|
686
686
|
this.BXWritePC(this.registers[Rm]);
|
|
687
|
-
|
|
687
|
+
deltaCycles++;
|
|
688
688
|
}
|
|
689
689
|
// CMN (register)
|
|
690
690
|
else if (opcode >> 6 === 0b0100001011) {
|
|
@@ -722,12 +722,12 @@ export class CortexM0Core {
|
|
|
722
722
|
// DMB SY
|
|
723
723
|
else if (opcode === 0xf3bf && (opcode2 & 0xfff0) === 0x8f50) {
|
|
724
724
|
this.PC += 2;
|
|
725
|
-
|
|
725
|
+
deltaCycles += 2;
|
|
726
726
|
}
|
|
727
727
|
// DSB SY
|
|
728
728
|
else if (opcode === 0xf3bf && (opcode2 & 0xfff0) === 0x8f40) {
|
|
729
729
|
this.PC += 2;
|
|
730
|
-
|
|
730
|
+
deltaCycles += 2;
|
|
731
731
|
}
|
|
732
732
|
// EORS
|
|
733
733
|
else if (opcode >> 6 === 0b0100000001) {
|
|
@@ -741,7 +741,7 @@ export class CortexM0Core {
|
|
|
741
741
|
// ISB SY
|
|
742
742
|
else if (opcode === 0xf3bf && (opcode2 & 0xfff0) === 0x8f60) {
|
|
743
743
|
this.PC += 2;
|
|
744
|
-
|
|
744
|
+
deltaCycles += 2;
|
|
745
745
|
}
|
|
746
746
|
// LDMIA
|
|
747
747
|
else if (opcode >> 11 === 0b11001) {
|
|
@@ -752,7 +752,7 @@ export class CortexM0Core {
|
|
|
752
752
|
if (registers & (1 << i)) {
|
|
753
753
|
this.registers[i] = this.readUint32(address);
|
|
754
754
|
address += 4;
|
|
755
|
-
|
|
755
|
+
deltaCycles++;
|
|
756
756
|
}
|
|
757
757
|
}
|
|
758
758
|
// Write back
|
|
@@ -766,7 +766,7 @@ export class CortexM0Core {
|
|
|
766
766
|
const Rn = (opcode >> 3) & 0x7;
|
|
767
767
|
const Rt = opcode & 0x7;
|
|
768
768
|
const addr = this.registers[Rn] + imm5;
|
|
769
|
-
|
|
769
|
+
deltaCycles += this.cyclesIO(addr);
|
|
770
770
|
this.registers[Rt] = this.readUint32(addr);
|
|
771
771
|
}
|
|
772
772
|
// LDR (sp + immediate)
|
|
@@ -774,7 +774,7 @@ export class CortexM0Core {
|
|
|
774
774
|
const Rt = (opcode >> 8) & 0x7;
|
|
775
775
|
const imm8 = opcode & 0xff;
|
|
776
776
|
const addr = this.SP + (imm8 << 2);
|
|
777
|
-
|
|
777
|
+
deltaCycles += this.cyclesIO(addr);
|
|
778
778
|
this.registers[Rt] = this.readUint32(addr);
|
|
779
779
|
}
|
|
780
780
|
// LDR (literal)
|
|
@@ -783,7 +783,7 @@ export class CortexM0Core {
|
|
|
783
783
|
const Rt = (opcode >> 8) & 7;
|
|
784
784
|
const nextPC = this.PC + 2;
|
|
785
785
|
const addr = (nextPC & 0xfffffffc) + imm8;
|
|
786
|
-
|
|
786
|
+
deltaCycles += this.cyclesIO(addr);
|
|
787
787
|
this.registers[Rt] = this.readUint32(addr);
|
|
788
788
|
}
|
|
789
789
|
// LDR (register)
|
|
@@ -792,7 +792,7 @@ export class CortexM0Core {
|
|
|
792
792
|
const Rn = (opcode >> 3) & 0x7;
|
|
793
793
|
const Rt = opcode & 0x7;
|
|
794
794
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
795
|
-
|
|
795
|
+
deltaCycles += this.cyclesIO(addr);
|
|
796
796
|
this.registers[Rt] = this.readUint32(addr);
|
|
797
797
|
}
|
|
798
798
|
// LDRB (immediate)
|
|
@@ -801,7 +801,7 @@ export class CortexM0Core {
|
|
|
801
801
|
const Rn = (opcode >> 3) & 0x7;
|
|
802
802
|
const Rt = opcode & 0x7;
|
|
803
803
|
const addr = this.registers[Rn] + imm5;
|
|
804
|
-
|
|
804
|
+
deltaCycles += this.cyclesIO(addr);
|
|
805
805
|
this.registers[Rt] = this.readUint8(addr);
|
|
806
806
|
}
|
|
807
807
|
// LDRB (register)
|
|
@@ -810,7 +810,7 @@ export class CortexM0Core {
|
|
|
810
810
|
const Rn = (opcode >> 3) & 0x7;
|
|
811
811
|
const Rt = opcode & 0x7;
|
|
812
812
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
813
|
-
|
|
813
|
+
deltaCycles += this.cyclesIO(addr);
|
|
814
814
|
this.registers[Rt] = this.readUint8(addr);
|
|
815
815
|
}
|
|
816
816
|
// LDRH (immediate)
|
|
@@ -819,7 +819,7 @@ export class CortexM0Core {
|
|
|
819
819
|
const Rn = (opcode >> 3) & 0x7;
|
|
820
820
|
const Rt = opcode & 0x7;
|
|
821
821
|
const addr = this.registers[Rn] + (imm5 << 1);
|
|
822
|
-
|
|
822
|
+
deltaCycles += this.cyclesIO(addr);
|
|
823
823
|
this.registers[Rt] = this.readUint16(addr);
|
|
824
824
|
}
|
|
825
825
|
// LDRH (register)
|
|
@@ -828,7 +828,7 @@ export class CortexM0Core {
|
|
|
828
828
|
const Rn = (opcode >> 3) & 0x7;
|
|
829
829
|
const Rt = opcode & 0x7;
|
|
830
830
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
831
|
-
|
|
831
|
+
deltaCycles += this.cyclesIO(addr);
|
|
832
832
|
this.registers[Rt] = this.readUint16(addr);
|
|
833
833
|
}
|
|
834
834
|
// LDRSB
|
|
@@ -837,7 +837,7 @@ export class CortexM0Core {
|
|
|
837
837
|
const Rn = (opcode >> 3) & 0x7;
|
|
838
838
|
const Rt = opcode & 0x7;
|
|
839
839
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
840
|
-
|
|
840
|
+
deltaCycles += this.cyclesIO(addr);
|
|
841
841
|
this.registers[Rt] = signExtend8(this.readUint8(addr));
|
|
842
842
|
}
|
|
843
843
|
// LDRSH
|
|
@@ -846,7 +846,7 @@ export class CortexM0Core {
|
|
|
846
846
|
const Rn = (opcode >> 3) & 0x7;
|
|
847
847
|
const Rt = opcode & 0x7;
|
|
848
848
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
849
|
-
|
|
849
|
+
deltaCycles += this.cyclesIO(addr);
|
|
850
850
|
this.registers[Rt] = signExtend16(this.readUint16(addr));
|
|
851
851
|
}
|
|
852
852
|
// LSLS (immediate)
|
|
@@ -903,7 +903,7 @@ export class CortexM0Core {
|
|
|
903
903
|
const Rd = ((opcode >> 4) & 0x8) | (opcode & 0x7);
|
|
904
904
|
let value = Rm === pcRegister ? this.PC + 2 : this.registers[Rm];
|
|
905
905
|
if (Rd === pcRegister) {
|
|
906
|
-
|
|
906
|
+
deltaCycles++;
|
|
907
907
|
value &= ~1;
|
|
908
908
|
}
|
|
909
909
|
else if (Rd === spRegister) {
|
|
@@ -925,7 +925,7 @@ export class CortexM0Core {
|
|
|
925
925
|
const Rd = (opcode2 >> 8) & 0xf;
|
|
926
926
|
this.registers[Rd] = this.readSpecialRegister(SYSm);
|
|
927
927
|
this.PC += 2;
|
|
928
|
-
|
|
928
|
+
deltaCycles += 2;
|
|
929
929
|
}
|
|
930
930
|
// MSR
|
|
931
931
|
else if (opcode >> 4 === 0b111100111000 && opcode2 >> 8 == 0b10001000) {
|
|
@@ -933,7 +933,7 @@ export class CortexM0Core {
|
|
|
933
933
|
const Rn = opcode & 0xf;
|
|
934
934
|
this.writeSpecialRegister(SYSm, this.registers[Rn]);
|
|
935
935
|
this.PC += 2;
|
|
936
|
-
|
|
936
|
+
deltaCycles += 2;
|
|
937
937
|
}
|
|
938
938
|
// MULS
|
|
939
939
|
else if (opcode >> 6 === 0b0100001101) {
|
|
@@ -970,13 +970,13 @@ export class CortexM0Core {
|
|
|
970
970
|
if (opcode & (1 << i)) {
|
|
971
971
|
this.registers[i] = this.readUint32(address);
|
|
972
972
|
address += 4;
|
|
973
|
-
|
|
973
|
+
deltaCycles++;
|
|
974
974
|
}
|
|
975
975
|
}
|
|
976
976
|
if (P) {
|
|
977
977
|
this.SP = address + 4;
|
|
978
978
|
this.BXWritePC(this.readUint32(address));
|
|
979
|
-
|
|
979
|
+
deltaCycles += 2;
|
|
980
980
|
}
|
|
981
981
|
else {
|
|
982
982
|
this.SP = address;
|
|
@@ -994,7 +994,7 @@ export class CortexM0Core {
|
|
|
994
994
|
for (let i = 0; i <= 7; i++) {
|
|
995
995
|
if (opcode & (1 << i)) {
|
|
996
996
|
this.writeUint32(address, this.registers[i]);
|
|
997
|
-
|
|
997
|
+
deltaCycles++;
|
|
998
998
|
address += 4;
|
|
999
999
|
}
|
|
1000
1000
|
}
|
|
@@ -1073,7 +1073,7 @@ export class CortexM0Core {
|
|
|
1073
1073
|
if (registers & (1 << i)) {
|
|
1074
1074
|
this.writeUint32(address, this.registers[i]);
|
|
1075
1075
|
address += 4;
|
|
1076
|
-
|
|
1076
|
+
deltaCycles++;
|
|
1077
1077
|
}
|
|
1078
1078
|
}
|
|
1079
1079
|
// Write back
|
|
@@ -1087,7 +1087,7 @@ export class CortexM0Core {
|
|
|
1087
1087
|
const Rn = (opcode >> 3) & 0x7;
|
|
1088
1088
|
const Rt = opcode & 0x7;
|
|
1089
1089
|
const address = this.registers[Rn] + imm5;
|
|
1090
|
-
|
|
1090
|
+
deltaCycles += this.cyclesIO(address, true);
|
|
1091
1091
|
this.writeUint32(address, this.registers[Rt]);
|
|
1092
1092
|
}
|
|
1093
1093
|
// STR (sp + immediate)
|
|
@@ -1095,7 +1095,7 @@ export class CortexM0Core {
|
|
|
1095
1095
|
const Rt = (opcode >> 8) & 0x7;
|
|
1096
1096
|
const imm8 = opcode & 0xff;
|
|
1097
1097
|
const address = this.SP + (imm8 << 2);
|
|
1098
|
-
|
|
1098
|
+
deltaCycles += this.cyclesIO(address, true);
|
|
1099
1099
|
this.writeUint32(address, this.registers[Rt]);
|
|
1100
1100
|
}
|
|
1101
1101
|
// STR (register)
|
|
@@ -1104,7 +1104,7 @@ export class CortexM0Core {
|
|
|
1104
1104
|
const Rn = (opcode >> 3) & 0x7;
|
|
1105
1105
|
const Rt = opcode & 0x7;
|
|
1106
1106
|
const address = this.registers[Rm] + this.registers[Rn];
|
|
1107
|
-
|
|
1107
|
+
deltaCycles += this.cyclesIO(address, true);
|
|
1108
1108
|
this.writeUint32(address, this.registers[Rt]);
|
|
1109
1109
|
}
|
|
1110
1110
|
// STRB (immediate)
|
|
@@ -1113,7 +1113,7 @@ export class CortexM0Core {
|
|
|
1113
1113
|
const Rn = (opcode >> 3) & 0x7;
|
|
1114
1114
|
const Rt = opcode & 0x7;
|
|
1115
1115
|
const address = this.registers[Rn] + imm5;
|
|
1116
|
-
|
|
1116
|
+
deltaCycles += this.cyclesIO(address, true);
|
|
1117
1117
|
this.writeUint8(address, this.registers[Rt]);
|
|
1118
1118
|
}
|
|
1119
1119
|
// STRB (register)
|
|
@@ -1122,7 +1122,7 @@ export class CortexM0Core {
|
|
|
1122
1122
|
const Rn = (opcode >> 3) & 0x7;
|
|
1123
1123
|
const Rt = opcode & 0x7;
|
|
1124
1124
|
const address = this.registers[Rm] + this.registers[Rn];
|
|
1125
|
-
|
|
1125
|
+
deltaCycles += this.cyclesIO(address, true);
|
|
1126
1126
|
this.writeUint8(address, this.registers[Rt]);
|
|
1127
1127
|
}
|
|
1128
1128
|
// STRH (immediate)
|
|
@@ -1131,7 +1131,7 @@ export class CortexM0Core {
|
|
|
1131
1131
|
const Rn = (opcode >> 3) & 0x7;
|
|
1132
1132
|
const Rt = opcode & 0x7;
|
|
1133
1133
|
const address = this.registers[Rn] + imm5;
|
|
1134
|
-
|
|
1134
|
+
deltaCycles += this.cyclesIO(address, true);
|
|
1135
1135
|
this.writeUint16(address, this.registers[Rt]);
|
|
1136
1136
|
}
|
|
1137
1137
|
// STRH (register)
|
|
@@ -1140,7 +1140,7 @@ export class CortexM0Core {
|
|
|
1140
1140
|
const Rn = (opcode >> 3) & 0x7;
|
|
1141
1141
|
const Rt = opcode & 0x7;
|
|
1142
1142
|
const address = this.registers[Rm] + this.registers[Rn];
|
|
1143
|
-
|
|
1143
|
+
deltaCycles += this.cyclesIO(address, true);
|
|
1144
1144
|
this.writeUint16(address, this.registers[Rt]);
|
|
1145
1145
|
}
|
|
1146
1146
|
// SUB (SP minus immediate)
|
|
@@ -1221,7 +1221,7 @@ export class CortexM0Core {
|
|
|
1221
1221
|
}
|
|
1222
1222
|
// WFE
|
|
1223
1223
|
else if (opcode === 0b1011111100100000) {
|
|
1224
|
-
|
|
1224
|
+
deltaCycles++;
|
|
1225
1225
|
if (this.eventRegistered) {
|
|
1226
1226
|
this.eventRegistered = false;
|
|
1227
1227
|
}
|
|
@@ -1231,7 +1231,7 @@ export class CortexM0Core {
|
|
|
1231
1231
|
}
|
|
1232
1232
|
// WFI
|
|
1233
1233
|
else if (opcode === 0b1011111100110000) {
|
|
1234
|
-
|
|
1234
|
+
deltaCycles++;
|
|
1235
1235
|
this.waiting = true;
|
|
1236
1236
|
}
|
|
1237
1237
|
// YIELD
|
|
@@ -1243,5 +1243,7 @@ export class CortexM0Core {
|
|
|
1243
1243
|
this.logger.warn(LOG_NAME, `Warning: Instruction at ${opcodePC.toString(16)} is not implemented yet!`);
|
|
1244
1244
|
this.logger.warn(LOG_NAME, `Opcode: 0x${opcode.toString(16)} (0x${opcode2.toString(16)})`);
|
|
1245
1245
|
}
|
|
1246
|
+
this.cycles += deltaCycles;
|
|
1247
|
+
return deltaCycles;
|
|
1246
1248
|
}
|
|
1247
1249
|
}
|
|
@@ -3,7 +3,7 @@ export type GDBResponseHandler = (value: string) => void;
|
|
|
3
3
|
export declare class GDBConnection {
|
|
4
4
|
private server;
|
|
5
5
|
private onResponse;
|
|
6
|
-
readonly
|
|
6
|
+
readonly target: import("./gdb-target.js").IGDBTarget;
|
|
7
7
|
private buf;
|
|
8
8
|
constructor(server: GDBServer, onResponse: GDBResponseHandler);
|
|
9
9
|
feedData(data: string): void;
|