rp2040js 0.17.13 → 0.17.14
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
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@@ -40,6 +40,8 @@ export declare class CortexM0Core {
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40
40
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VTOR: number;
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SHPR2: number;
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SHPR3: number;
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43
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/** Hook to listen for function calls - branch-link (BL/BLX) instructions */
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blTaken: (core: CortexM0Core, blx: boolean) => void;
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constructor(rp2040: RP2040);
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get logger(): import(".").Logger;
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reset(): void;
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@@ -77,6 +77,11 @@ class CortexM0Core {
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this.VTOR = 0;
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this.SHPR2 = 0;
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this.SHPR3 = 0;
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/** Hook to listen for function calls - branch-link (BL/BLX) instructions */
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81
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this.blTaken = (core, blx) => {
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82
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void core; // surpress unused variable warnings
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83
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void blx;
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84
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};
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this.SP = 0xfffffffc;
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this.bankedSP = 0xfffffffc;
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}
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@@ -671,6 +676,7 @@ class CortexM0Core {
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this.LR = (this.PC + 2) | 0x1;
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this.PC += 2 + imm32;
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this.cycles += 2;
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679
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this.blTaken(this, false);
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}
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// BLX
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else if (opcode >> 7 === 0b010001111 && (opcode & 0x7) === 0) {
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@@ -678,6 +684,7 @@ class CortexM0Core {
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this.LR = this.PC | 0x1;
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this.PC = this.registers[Rm] & ~1;
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this.cycles++;
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687
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this.blTaken(this, true);
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}
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// BX
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else if (opcode >> 7 === 0b010001110 && (opcode & 0x7) === 0) {
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@@ -40,6 +40,8 @@ export declare class CortexM0Core {
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40
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VTOR: number;
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41
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SHPR2: number;
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42
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SHPR3: number;
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43
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+
/** Hook to listen for function calls - branch-link (BL/BLX) instructions */
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blTaken: (core: CortexM0Core, blx: boolean) => void;
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constructor(rp2040: RP2040);
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get logger(): import("./index").Logger;
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reset(): void;
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@@ -74,6 +74,11 @@ export class CortexM0Core {
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this.VTOR = 0;
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this.SHPR2 = 0;
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this.SHPR3 = 0;
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77
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/** Hook to listen for function calls - branch-link (BL/BLX) instructions */
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78
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this.blTaken = (core, blx) => {
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void core; // surpress unused variable warnings
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void blx;
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};
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this.SP = 0xfffffffc;
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this.bankedSP = 0xfffffffc;
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}
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@@ -668,6 +673,7 @@ export class CortexM0Core {
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this.LR = (this.PC + 2) | 0x1;
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669
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this.PC += 2 + imm32;
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this.cycles += 2;
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676
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this.blTaken(this, false);
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671
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}
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672
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// BLX
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673
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else if (opcode >> 7 === 0b010001111 && (opcode & 0x7) === 0) {
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@@ -675,6 +681,7 @@ export class CortexM0Core {
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this.LR = this.PC | 0x1;
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676
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this.PC = this.registers[Rm] & ~1;
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this.cycles++;
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684
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this.blTaken(this, true);
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678
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}
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// BX
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else if (opcode >> 7 === 0b010001110 && (opcode & 0x7) === 0) {
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