react-native-quick-crypto 1.0.19 → 1.1.0

package/deps/simdutf/benchmarks/competition/u8u16/lib/libgen/make_half_operand_versions.py

@@ -0,0 +1,158 @@
+# 
+#  make_half_operand_versions.py
+#
+#  Copyright (C) 2007 Robert D. Cameron, Dan Lin
+#  Licensed to International Characters Inc. and Simon Fraser University
+#	              under the Academic Free License version 3.0
+#  Licensed to the public under the Open Software License version 3.0.
+#
+# make_halfoperand_versions.py generates macro definitions for
+# the half-operand versions of idealized SIMD operations.
+#
+# The half-operand versions of a (binary) operation on n-bit fields
+# are named by # extending the operation name with an underscore and 
+# two # operand modification letters for the two operands:
+#   operand modifier "h" indicates that the high n/2 bits of fields
+#      are taken as the operand values (shifted right by n/2).
+#   operand modifier "l" indicates that the low n/2 bits of fields
+#      masking off the high n/2 bits.
+#   operand modifier "x" indicates that all n bits of the field are
+#      used as the operand value without modification.
+#
+ops = ["sub", "add", "pack", "mergeh", "mergel", "sll", "srl", "sra", "rotl"]
+mods = ["x", "l", "h"]
+fws = [2, 4, 8, 16, 32]             
+
+# The generic approach to defining these operations is to simply
+# include code to modify each of the operands and then perform
+# the desired operation.  However, this program generates more
+# efficient code when certain optimizations may apply.
+#
+# 1.  Lo-Mask Optimization.
+#     The masking for an "l" operand can be eliminated if
+#     that operation ignores the high n/2 bits.  The
+#     ignores_operand_hi_half property declares this.
+# 2.  Hi-Mask Optimization
+#     The shifting of an "h" operand can be optimized if the
+#     operation ignores the high n/2 bits of the operand.  In this 
+#     case, it is possible to replace a simulated shift for n bit
+#     fields with any built-in shift for fields of a multiple of n.
+# 3.  Double-High Shift Optimization
+#     In some cases, the two shift operations for a pair of "h" operands 
+#     may be eliminated in favor of a single shift operation after
+#     the basic operation is perfomed (support_hh_postshift property).
+# 4.  LH Add Optimization
+#     If both operands are modified (either "h" or "l" modifiers), 
+#     a simulated add on small field widths can be replaced by a
+#     built-in add operation for fields of a multiple of n.
+#
+##########################################################################
+#
+# Operation Properties to Support Optimization
+#
+# 1.  Lo-Mask Optimization.
+#
+# An operation satisfies the ignores_operand_hi_half property
+# for a particular operand if the high n/2 bits of that
+# operand play no role in the operation applied to n bit
+# fields.   This property applies for the second operand
+# of all shifts and rotates, as well as for both operands
+# of packs.
+#
+ignores_operand_hi_half = { 1: ["pack"], 2: ["sll", "srl", "sra", "rotl", "pack"]}
+#
+# 2.  Hi-Mask Optimization
+#
+# Shifts of 2, 4 or 8 bits are simulated on common architectures.  Replace
+# if possible with  16-bit shifts, which are built-in on common architectures.
+#  
+simulated_shift_replacement = {2: 16, 4: 16, 8: 16}
+#
+# 3.  Double-High Shift Optimization
+#
+support_hh_postshift = ["mergeh", "mergel"]
+#
+# 4.  LH Add Optimization
+#
+# Adds of 2-bit or 4-bit fields are simulated on common architectures.  Replace
+# if possible with 8-bit adds, which are built-in on common architectrues.
+#
+simulated_add_replacement = {2: 8, 4: 8}
+
+#
+# Generate a definition that won't override any hand-coded version.
+#
+defn_mode = "INLINE"
+
+def define_macro_if_undefined(op_name, body):
+    return "#ifndef %s\n#define %s(v1, v2) %s\n#endif\n\n" % (op_name, op_name, body)
+
+def define_inline_function_if_undefined(op_name, body):
+    prototype = "inline SIMD_type %s(SIMD_type v1, SIMD_type v2)" % (op_name)
+    return "#ifndef %s\n%s {\n  return %s;\n}\n#endif\n\n" % (op_name, prototype, body)
+
+def define_if_undefined(op_name, body):
+    global defn_mode
+    if defn_mode == "MACRO": return define_macro_if_undefined(op_name, body)
+    else: return define_inline_function_if_undefined(op_name, body)
+
+def operand_name(operand_no):
+    return "v%i" % operand_no
+
+def make_modified_operand(operation, fw, operand_no, modifier):
+    operand = operand_name(operand_no)
+    if modifier == "x": return operand
+    elif operation in ignores_operand_hi_half[operand_no]:
+	if modifier == "l": return operand
+	elif modifier == "h":
+	    if fw in simulated_shift_replacement.keys():
+	      shft_op = "simd_srli_%i" % (simulated_shift_replacement[fw])
+	    else: shft_op = "simd_srli_%i" % (fw)
+	    return "%s(%s, %i)" % (shft_op, operand, fw/2)
+	else: raise Exception("Bad modifier %s" % modifier)
+    elif modifier == "h": return "simd_srli_%i(%s, %i)" % (fw, operand, fw/2)
+    elif modifier == "l": return "simd_andc(%s, simd_himask_%i)" % (operand, fw)
+    else: raise Exception("Bad modifier %s" % modifier)
+
+
+def make_optimized_defn(op, fw, m1, m2):
+    base_operation = "simd_%s_%i" % (op, fw)
+    op_name = base_operation + "_" + m1 + m2
+    operand1 = make_modified_operand(op, fw, 1, m1)
+    operand2 = make_modified_operand(op, fw, 2, m2)
+    if (m1 == "h") and (m2 == "h") and (op in support_hh_postshift):
+        code = "%s(%s, %s)" % (base_operation, operand1, operand2)
+	return define_if_undefined(op_name, code)
+    if (op == "add") and (m1 != "x") and (m2 != "x") and (fw in simulated_add_replacement.keys()):
+	base_operation = "simd_%s_%i" % (op, simulated_add_replacement[fw])
+    return define_if_undefined(op_name, "%s(%s, %s)" % (base_operation, operand1, operand2))
+
+def make_all_for_op_fw(op, fw):
+    defn_list = ''
+    for m1 in mods:
+        for m2 in mods:
+            defn_list += make_optimized_defn(op, fw, m1, m2)
+    return defn_list
+
+#
+# Usage: make_all_half_operand_versions(ops, fws) to generate
+# a complete file of all the "half-operand" modified versions
+# of a set of simd operations for each operation op within
+# the list ops and each field width fw in the list of field
+# widths.
+#
+def make_all_half_operand_versions (ops, fws):
+    defn_list = ''
+    for op in ops:
+        for fw in fws:
+            defn_list += make_all_for_op_fw(op, fw)
+    return defn_list
+
+def generate_and_write_versions(filename, ops, fws):
+    defn_list = make_all_half_operand_versions (ops, fws)
+    file = open(filename, 'w')
+    file.write(defn_list)
+    file.close()
+    
+if __name__ == "__main__":
+    generate_and_write_versions("mmx_simd_modified.h", ops, fws)   

package/deps/simdutf/benchmarks/competition/u8u16/lib/libgen/make_test.py

@@ -0,0 +1,270 @@
+# 
+#  make_simd_operation_test.py
+#
+#  Copyright (C) 2007 Dan Lin, Robert D. Cameron
+#  Licensed to International Characters Inc. and Simon Fraser University
+#	              under the Academic Free License version 3.0
+#  Licensed to the public under the Open Software License version 3.0.
+
+# make_simd_operation_test.py generates test file simd_operation_test.c
+# which compares the result computed by simd operations and 
+# result simulated by this test file
+
+from random import randint
+
+ops = ["rotl"]
+mods = ["x","h","l"]
+fws = [32]
+merge_fws = fws[:-1]
+bitBlock_size = 64
+r1=0
+r2=0
+
+def modified_operand(N, n, operand, modifier):
+    if modifier == "x": return operand
+    elif modifier == "h":
+        for i in range(0,N/n):
+            operand[i] = operand[i] >> ((n+1)/2)
+        return operand
+    else:
+        for i in range(0,N/n):
+            operand[i] = operand[i] % (2** ((n+1)/2))
+        return operand
+
+def split_up(r,N,n):
+    remainder = r
+    result = []
+    for i in range(0,N/n):
+        quotient = remainder / (2**(N-n*(i+1)))
+        remainder = remainder % (2**(N-n*(i+1)))
+        result.append(quotient)
+    return result
+
+def join_up(r,N,n):
+    result = 0
+    for i in range(0,N/n):
+        result = result + (r[i] * (2**(N-n*(i+1))))
+    return result
+
+def gen_const(c,N,n):
+    return c*(2**N-1)/(2**n-1)
+ 
+def get_mask(n):
+    count = 1
+    temp = n
+    while (n/2 != 1):
+        n = n/2
+        count = count + 1
+    return count
+
+def simulate_add (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(0, N/n):
+        r3_field.append((r1_field[i] + r2_field[i])%(2**n))
+    r3 = join_up(r3_field, N, n)
+    return r3
+
+def simulate_sub (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(0, N/n):
+        r3_field.append((r1_field[i] - r2_field[i] + 2**n)%(2**n))
+    r3 = join_up(r3_field, N, n)
+    return r3
+
+def simulate_srl (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(0, N/n):
+        r3_field.append(r1_field[i] >> (r2_field[i] % 2**get_mask(n)))
+    r3 = join_up(r3_field, N, n)
+    return r3
+
+def simulate_sll (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(0, N/n):
+        r3_field.append((r1_field[i] << (r2_field[i] % 2**get_mask(n)))% (2**n))
+    r3 = join_up(r3_field, N, n)
+    return r3
+
+def simulate_sra (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(0, N/n):
+        supplement = 0
+        shift = r2_field[i] % (2**get_mask(n))
+        for j in range(1, shift+1):
+            supplement = supplement + (r1_field[i]/(2**(n-1)))*2**(n-j)
+        r3_field.append((r1_field[i] >> shift) + supplement)
+    r3 = join_up(r3_field, N, n)
+    return r3
+
+def simulate_rotl (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(0, N/n):
+        shift = r2_field[i] % 2**get_mask(n)
+        r3_field.append((r1_field[i] << shift) % 2**n + ((r1_field[i] >> (n - shift))% (2**n)))
+    r3 = join_up(r3_field, N, n)
+    return r3
+
+def simulate_mergeh (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(0, N/n/2):
+        r3_field.append(r1_field[i])
+        r3_field.append(r2_field[i])
+    r3 = join_up(r3_field, N, n)
+    return r3
+
+def simulate_mergel (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(N/n/2, N/n):
+        r3_field.append(r1_field[i])
+        r3_field.append(r2_field[i])
+    r3 = join_up(r3_field, N, n)
+    return r3
+
+def simulate_pack (N, n, m1, m2, r1, r2):
+    r1_field = modified_operand(N, n, split_up(r1,N,n), m1)
+    r2_field = modified_operand(N, n, split_up(r2,N,n), m2)
+    r3_field = []
+    for i in range(0, N/n):
+        r3_field.append(r1_field[i] % (2** (n/2)))
+    for j in range(0, N/n):
+        r3_field.append(r2_field[j] % (2** (n/2)))
+    r3 = join_up(r3_field, N, n/2)
+    return r3
+ 
+def make_modified_operand(fw, operand, modifier):
+    if modifier == "x": return operand
+    elif modifier == "h": return "simd_srli_"+str(fw)+"(%s, %i)" % (operand, fw/2)
+    else: return "simd_andc(%s, simd_himask_%i)" % (operand, fw)
+
+def split_64to16(r):
+    result = []
+    result_hi =  r/2**32
+    result_lo =  r%2**32
+    result.append(result_hi/2**16)
+    result.append(result_hi%2**16)
+    result.append(result_lo/2**16)
+    result.append(result_lo%2**16)
+    return result
+
+def reverse(n):
+    mask = 255
+    result = 0
+    for i in range(0,8):
+	    temp = (n & mask)>>(i*8)
+	    result = (result | temp)<< 8
+	    mask = mask << 8
+    return result>>8
+    
+def make_test(op, fw, m1, m2, r1, r2):
+    test_operation = "simd_%s_%i_%s%s (a, b)"
+    template1 = "\ttest_rslt = %s;\n" % test_operation
+    template1 += "\tif (!(simd_all_eq_8(test_rslt, simd_if(simd_himask_64,simd_if(simd_himask_32,simd_const_16(%s),simd_const_16(%s)),simd_if(simd_himask_32,simd_const_16(%s),simd_const_16(%s)))))) {\n"
+    err_stmts = "\t\t\tprintf(\"error in %s \\n\");\n" % test_operation
+    err_stmts += "\t\t\tprint_bit_block(\"Computed:\", test_rslt);\n"
+    err_stmts += "\t\t\tprintf(\"\\tExpected: %s\\n\");\n"
+    err_stmts += "\t\t}\n"
+    template = template1 + err_stmts
+    if op == "add":
+	r =  simulate_add(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    elif op == "sub":
+	r =  simulate_sub(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    elif op == "pack":
+	r =  simulate_pack(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    elif op == "mergel":
+	r =  simulate_mergel(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    elif op == "mergeh":
+	r =  simulate_mergeh(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    elif op == "srl":
+	r =  simulate_srl(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    elif op == "sll":
+	r =  simulate_sll(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    elif op == "sra":
+	r =  simulate_sra(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    elif op == "rotl":
+	r =  simulate_rotl(bitBlock_size,fw,m1,m2,r1,r2)
+	result = split_64to16(r)
+        return template % (op, fw, m1, m2,result[0],result[1],result[2],result[3],op,fw,m1,m2,hex(reverse(r)))
+    else:
+        return template % (op, fw, m1, m2, "0x0","0x0","0x0","0x0",op,fw,m1,m2,"0x0")
+
+
+def make_all_for_fw(fw,r1,r2):
+    test_list = ''
+    for m1 in mods:
+        for m2 in mods:
+            for op in ops:
+                test_list += make_test(op, fw, m1, m2, r1, r2)
+    return test_list
+
+def gen_operand_sequence(fw):
+    if fw == 2:
+	test_operand = [0x0, 0x1, 0x2, 0x3]
+    elif fw == 4:
+	test_operand = [0x0, 0x7, 0x8, 0xf]
+	test_operand.append(randint(0x1, 0xe))
+    elif fw == 8:
+	test_operand = [0x0, 0x7f, 0x80, 0xff]
+	test_operand.append(randint(0x1, 0xfe))
+    elif fw == 16:
+	test_operand = [0x0, 0x7fff, 0x8000, 0xffff]
+	test_operand.append(randint(0x1, 0xfffe))
+    elif fw == 32:
+	test_operand = [0x0, 0x7fffffff, 0x80000000, 0xffffffff]
+	test_operand.append(randint(0x1, 0xfffffffe))
+    return test_operand
+
+
+def generate_and_write_versions(filename, ops,fws):
+    test_list = r"""#include <stdio.h>
+#include "%s.h"
+int main() {
+        SIMD_type a, b,test_rslt;
+"""
+    test_list = test_list % filename
+    for fw in fws:      
+	for r1 in gen_operand_sequence(fw):
+	      for r2 in  gen_operand_sequence(fw):
+                  test_list +='\ta=simd_const_'+str(fw)+'('+hex(r1)+');\n\tb=simd_const_'+str(fw)+'('+hex(r2)+');\n'
+                  test_list += make_all_for_fw (fw,gen_const(r1,64,fw),gen_const(r2,64,fw))
+    test_list += '\treturn 0;\n}\n'
+    file = open(filename+"_test.c", 'w')
+    file.write(test_list)
+    file.close()
+    
+import sys
+if __name__ == "__main__":
+    if len(sys.argv) < 2: library_under_test = "mmx_simd"
+    else: library_under_test = sys.argv[1]
+    generate_and_write_versions(library_under_test, ops, fws)

package/deps/simdutf/benchmarks/competition/u8u16/lib/mmx_simd.h

@@ -0,0 +1,141 @@
+/* Copyright (C) 2007 Robert D. Cameron, Dan Lin
+   Licensed to International Characters Inc. and Simon Fraser University
+              under the Academic Free License version 3.0.
+   Licensed to the public under the Open Software License version 3.0.
+*/
+#ifndef _MSC_VER
+#include <stdint.h>
+#endif
+#ifdef _MSC_VER
+#include "stdint.h"
+#define LITTLE_ENDIAN 1234
+#define BIG_ENDIAN 4321
+#define BYTE_ORDER LITTLE_ENDIAN
+#endif
+#include <limits.h>
+#ifndef LONG_BIT
+#define LONG_BIT (8* sizeof(unsigned long))
+#endif 
+#include "mmx_simd_built_in.h"
+#include "mmx_simd_basic.h"
+#include "mmx_simd_modified.h"
+
+/* mmintrin.h does not provide access to pmaxub;
+   xmmintrin.h does via _mm_max_pu8(a, b), but also
+   requires SSE. */
+
+static inline SIMD_type simd_max_8(SIMD_type a, SIMD_type b) {
+  asm volatile(
+    "pmaxub %[rb], %[ra]\n\t"
+    : [ra] "+y" (a)
+    : [rb] "y" (b));
+  return a;
+}
+
+char mask_x55 [8] __attribute__ ((aligned(8))) = 
+    {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55};
+char mask_x33 [8] __attribute__ ((aligned(8))) = 
+    {0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33};
+char mask_x0F [8] __attribute__ ((aligned(8))) = 
+    {0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F};
+
+static inline int simd_all_true_8(SIMD_type maskvector) {
+/*  return _mm_movemask_epi8(maskvector) == 0xFF;  */
+  int maskbyte;
+  asm volatile("pmovmskb %[maskvector], %[maskbyte]\n"
+               : [maskbyte] "=r" (maskbyte)
+               : [maskvector] "y" (maskvector));
+  return maskbyte == 0xFF; 
+}
+static inline int simd_any_true_8(SIMD_type maskvector) {
+/*  return _mm_movemask_epi8(maskvector) =!= 0;  */
+  int maskbyte;
+  asm volatile("pmovmskb %[maskvector], %[maskbyte]\n"
+               : [maskbyte] "=r" (maskbyte)
+               : [maskvector] "y" (maskvector));
+  return maskbyte != 0; 
+}
+
+static inline int simd_any_sign_bit_8(SIMD_type v) {
+/*  return _mm_movemask_epi8(v) =!= 0;  */
+  int signbyte;
+  asm volatile("pmovmskb %[v], %[signbyte]\n"
+               : [signbyte] "=r" (signbyte)
+               : [v] "y" (v));
+  return signbyte != 0; 
+}
+
+#define simd_all_eq_8(v1, v2) simd_all_true_8(_mm_cmpeq_pi8(v1, v2))
+#define simd_all_le_8(v1, v2) \
+  simd_all_eq_8(simd_max_8(v1, v2), v2)
+
+#define simd_all_signed_gt_8(v1, v2) simd_all_true_8(_mm_cmpgt_pi8(v1, v2))
+
+static inline int bitblock_has_bit(SIMD_type v) {
+  return !simd_all_true_8(simd_eq_8(v, simd_const_8(0)));
+}
+
+
+#define bitblock_test_bit(blk, n) \
+  sisd_to_int(sisd_srli(sisd_slli(blk, (BLOCKSIZE - 1) - (n)), BLOCKSIZE-1))
+
+/*#define bitblock_test_bit(blk, n) \
+((n) == 63 ? sisd_to_int(sisd_srli(blk, n)) : \
+(sisd_to_int(sisd_srli(blk, n)) & 1)) */
+
+
+void print_bit_block(char * var_name, SIMD_type v) {
+  union {SIMD_type vec; unsigned char elems[8];} x;
+  x.vec = v;
+  unsigned char c, bit_reversed;
+  int i;
+  printf("%20s = ", var_name);
+  for (i = 0; i < sizeof(SIMD_type); i++) {
+    c = x.elems[i];
+     printf("%02X ", c); 
+  }
+  printf("\n");
+}
+
+static inline int bitblock_bit_count(SIMD_type v) {
+
+  SIMD_type cts_2 = simd_add_2_lh(v,v);
+  SIMD_type cts_4 = simd_add_4_lh(cts_2,cts_2);
+  SIMD_type cts_8 = simd_add_8_lh(cts_4,cts_4);
+  SIMD_type r = simd_const_8(0);
+
+  asm volatile("psadbw %[r_reg], %[cts8_reg]\n\t"
+               : [cts8_reg] "+y" (cts_8)
+               : [r_reg] "y" (r));	
+  return sisd_to_int(cts_8);
+}
+
+
+
+static inline int count_forward_zeroes(SIMD_type bits) {
+  union {SIMD_type vec; unsigned int elems[2];} v;
+  v.vec = bits;
+  if (v.elems[0] != 0) return __builtin_ctzl(v.elems[0]);
+  else if (v.elems[1] != 0) return 32 + __builtin_ctzl(v.elems[1]);
+  else return 64;
+}
+
+
+/* Scans for a 1 as long as it takes.  Use a sentinel to fence. */
+static inline int bitstream_scan(SIMD_type * stream, int bit_posn) {
+  unsigned int * bitstream_ptr = (unsigned int *) (((intptr_t) stream) + bit_posn/8);
+  unsigned int bitstream_slice = *bitstream_ptr & (-1 << bit_posn % 8);
+  unsigned int slice_scan;
+  if (bitstream_slice == 0) {
+    do {
+      bitstream_ptr++;
+      bitstream_slice = *bitstream_ptr;
+    } while (bitstream_slice == 0);
+  }
+  slice_scan = __builtin_ctz(bitstream_slice);
+  return 8*((intptr_t) bitstream_ptr - (intptr_t) stream) + slice_scan;
+}
+
+
+
+