psyq-asm 0.0.1

package/dist/isa/encode.js

@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: MIT
+import { InvalidInstructionError } from '../errors.js';
+import { isRecord } from '../options.js';
+import { COP_SLOTS } from './fields.js';
+import { rowFor } from './table.js';
+const EXPECTED_KIND = {
+    rd: 'gpr',
+    rs: 'gpr',
+    rt: 'gpr',
+    sa: 'shamt',
+    imm16s: 'imm',
+    imm16u: 'imm',
+    mem: 'mem',
+    branch: 'branch',
+    target: 'target',
+    code20: 'imm',
+    code10hi: 'imm',
+    code10: 'imm',
+    imm25: 'imm',
+    cop0: 'cop',
+    cop2d: 'cop',
+    cop2c: 'cop',
+    cop2dRt: 'cop',
+};
+function fieldReader(operand, position) {
+    return (key, min, max, what) => {
+        const value = operand[key];
+        if (typeof value !== 'number' || !Number.isInteger(value) || value < min || value > max) {
+            throw new InvalidInstructionError(`${position}: ${what} must be an integer from ${String(min)} to ${String(max)}, not ${String(value)}.`);
+        }
+        return value;
+    };
+}
+/** The bits one operand contributes to the word. */
+function fieldBits(slot, field, operand, position) {
+    switch (slot) {
+        case 'rd':
+            return field('number', 0, 31, 'register') << 11;
+        case 'rs':
+            return field('number', 0, 31, 'register') << 21;
+        case 'rt':
+            return field('number', 0, 31, 'register') << 16;
+        case 'sa':
+            return field('value', 0, 31, 'shift amount') << 6;
+        case 'imm16s':
+            return field('value', -0x8000, 0x7fff, 'signed 16-bit immediate') & 0xffff;
+        case 'imm16u':
+            return field('value', 0, 0xffff, 'unsigned 16-bit immediate');
+        case 'mem':
+            return ((field('base', 0, 31, 'base register') << 21) |
+                (field('offset', -0x8000, 0x7fff, 'offset') & 0xffff));
+        case 'branch':
+            return field('displacement', -0x8000, 0x7fff, 'branch displacement') & 0xffff;
+        case 'target':
+            return field('index', 0, 0x03ffffff, 'jump index');
+        case 'code20':
+            return field('value', 0, 0xfffff, 'code') << 6;
+        case 'code10hi':
+            return field('value', 0, 0x3ff, 'code') << 16;
+        case 'code10':
+            return field('value', 0, 0x3ff, 'code') << 6;
+        case 'imm25':
+            return field('value', 0, 0x01ffffff, 'coprocessor command');
+        case 'cop0':
+        case 'cop2d':
+        case 'cop2c':
+        case 'cop2dRt': {
+            const n = field('number', 0, 31, 'coprocessor register');
+            const { unit, space, shift } = COP_SLOTS[slot];
+            if (operand['unit'] !== unit || operand['space'] !== space) {
+                throw new InvalidInstructionError(`${position} must be a coprocessor ${String(unit)} ${space} register.`);
+            }
+            return n << shift;
+        }
+    }
+}
+/** Fill omitted optional operands so the list matches the row's syntax. */
+function canonicalOperands(row, operands) {
+    if (row.optional === 'trailing-zero' && operands.length < row.syntax.length) {
+        const missing = row.syntax.length - operands.length;
+        return [...operands, ...Array(missing).fill({ kind: 'imm', value: 0 })];
+    }
+    if (row.optional === 'leading-ra' && operands.length === row.syntax.length - 1) {
+        return [{ kind: 'gpr', number: 31 }, ...operands];
+    }
+    return operands;
+}
+/**
+ * Encode one instruction. The operands are in assembly order, as `decode`
+ * produces them; `jalr rs` may omit the link register and `syscall`, `break`,
+ * and `tge` may omit their code. Throws `InvalidInstructionError` for an
+ * unknown mnemonic or an operand that does not fit.
+ */
+export function encode(instruction) {
+    const candidate = instruction;
+    if (!isRecord(candidate) ||
+        typeof candidate['mnemonic'] !== 'string' ||
+        !Array.isArray(candidate['operands'])) {
+        throw new InvalidInstructionError('instruction must be an object with a mnemonic and an operands array.');
+    }
+    const mnemonic = candidate['mnemonic'];
+    const given = candidate['operands'];
+    const row = rowFor(mnemonic);
+    if (row === undefined) {
+        throw new InvalidInstructionError(`unknown mnemonic ${JSON.stringify(mnemonic)}.`);
+    }
+    const operands = canonicalOperands(row, given);
+    if (operands.length !== row.syntax.length) {
+        throw new InvalidInstructionError(`${mnemonic} takes ${String(row.syntax.length)} operands, not ${String(given.length)}.`);
+    }
+    let word = row.value;
+    row.syntax.forEach((slot, index) => {
+        const operand = operands[index];
+        const position = `${mnemonic} operand ${String(index + 1)}`;
+        const expected = EXPECTED_KIND[slot];
+        if (!isRecord(operand) || operand['kind'] !== expected) {
+            const kind = isRecord(operand) ? String(operand['kind']) : typeof operand;
+            throw new InvalidInstructionError(`${position} must be of kind ${expected}, not ${kind}.`);
+        }
+        word |= fieldBits(slot, fieldReader(operand, position), operand, position);
+    });
+    return word >>> 0;
+}
+//# sourceMappingURL=encode.js.map

package/dist/isa/encode.js.map

@@ -0,0 +1 @@
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package/dist/isa/fields.d.ts

@@ -0,0 +1,27 @@
+/**
+ * Operand slots and the bit fields they occupy in an R3000 word.
+ *
+ * Bit layout: op[31:26] rs[25:21] rt[20:16] rd[15:11] sa[10:6] fn[5:0],
+ * imm[15:0], target[25:0].
+ */
+/** Where an operand lives in the word and how it is written in assembly. */
+export type Slot = 'rd' | 'rs' | 'rt' | 'sa' | 'imm16s' | 'imm16u' | 'mem' | 'branch' | 'target' | 'code20' | 'code10hi' | 'code10' | 'imm25' | CopSlot;
+/** Coprocessor register slots: which unit, which register space, which field. */
+export type CopSlot = 'cop0' | 'cop2d' | 'cop2c' | 'cop2dRt';
+export declare const COP_SLOTS: Readonly<Record<CopSlot, {
+    readonly unit: 0 | 2;
+    readonly space: 'data' | 'control';
+    readonly shift: 11 | 16;
+}>>;
+/** The bits of the word each slot owns. */
+export declare const SLOT_BITS: Readonly<Record<Slot, number>>;
+/** Sign-extend the low 16 bits of `value`. */
+export declare function signExtend16(value: number): number;
+/**
+ * The `%hi` half of a 32-bit value: the upper 16 bits, adjusted so that adding
+ * the sign-extended `%lo` half reconstructs the value.
+ */
+export declare function hi16(value: number): number;
+/** The `%lo` half of a 32-bit value, as a field (0 to 0xFFFF). */
+export declare function lo16(value: number): number;
+//# sourceMappingURL=fields.d.ts.map

package/dist/isa/fields.d.ts.map

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package/dist/isa/fields.js

@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: MIT
+/**
+ * Operand slots and the bit fields they occupy in an R3000 word.
+ *
+ * Bit layout: op[31:26] rs[25:21] rt[20:16] rd[15:11] sa[10:6] fn[5:0],
+ * imm[15:0], target[25:0].
+ */
+export const COP_SLOTS = Object.freeze({
+    cop0: { unit: 0, space: 'data', shift: 11 },
+    cop2d: { unit: 2, space: 'data', shift: 11 },
+    cop2c: { unit: 2, space: 'control', shift: 11 },
+    cop2dRt: { unit: 2, space: 'data', shift: 16 },
+});
+/** The bits of the word each slot owns. */
+export const SLOT_BITS = Object.freeze({
+    rd: 0x0000f800,
+    rs: 0x03e00000,
+    rt: 0x001f0000,
+    sa: 0x000007c0,
+    imm16s: 0x0000ffff,
+    imm16u: 0x0000ffff,
+    mem: 0x03e0ffff,
+    branch: 0x0000ffff,
+    target: 0x03ffffff,
+    code20: 0x03ffffc0,
+    code10hi: 0x03ff0000,
+    code10: 0x0000ffc0,
+    imm25: 0x01ffffff,
+    cop0: 0x0000f800,
+    cop2d: 0x0000f800,
+    cop2c: 0x0000f800,
+    cop2dRt: 0x001f0000,
+});
+/** Sign-extend the low 16 bits of `value`. */
+export function signExtend16(value) {
+    return (value << 16) >> 16;
+}
+/**
+ * The `%hi` half of a 32-bit value: the upper 16 bits, adjusted so that adding
+ * the sign-extended `%lo` half reconstructs the value.
+ */
+export function hi16(value) {
+    return ((value + 0x8000) >>> 16) & 0xffff;
+}
+/** The `%lo` half of a 32-bit value, as a field (0 to 0xFFFF). */
+export function lo16(value) {
+    return value & 0xffff;
+}
+//# sourceMappingURL=fields.js.map

package/dist/isa/fields.js.map

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package/dist/isa/format.d.ts

@@ -0,0 +1,14 @@
+import type { FormatStyle, Instruction, Operand, UnknownInstruction } from '../public-types.js';
+import { type NormalizedFormatStyle } from '../options.js';
+/** A number in the chosen radix; hexadecimal digits are upper case. */
+export declare function formatNumber(value: number, hex: boolean): string;
+/** A branch target relative to the branch itself: `.+12` is two instructions past the delay slot. */
+export declare function formatDisplacement(displacement: number): string;
+export declare function formatOperand(operand: Operand, style: NormalizedFormatStyle): string;
+/**
+ * Render one instruction as assembly text: `lw $v0,0x20($s0)`,
+ * `cop2 0x180001`, `.word 0xFFFFFFFF` for an unknown word. Branch targets are
+ * written relative to the branch (`.+12`); `formatProgram` writes labels.
+ */
+export declare function format(instruction: Instruction | UnknownInstruction, style?: FormatStyle): string;
+//# sourceMappingURL=format.d.ts.map

package/dist/isa/format.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"format.d.ts","sourceRoot":"","sources":["../../src/isa/format.ts"],"names":[],"mappings":"AACA,OAAO,KAAK,EAAE,WAAW,EAAE,WAAW,EAAE,OAAO,EAAE,kBAAkB,EAAE,MAAM,oBAAoB,CAAC;AAChG,OAAO,EAAuB,KAAK,qBAAqB,EAAE,MAAM,eAAe,CAAC;AAOhF,uEAAuE;AACvE,wBAAgB,YAAY,CAAC,KAAK,EAAE,MAAM,EAAE,GAAG,EAAE,OAAO,GAAG,MAAM,CAIhE;AAED,qGAAqG;AACrG,wBAAgB,kBAAkB,CAAC,YAAY,EAAE,MAAM,GAAG,MAAM,CAG/D;AAED,wBAAgB,aAAa,CAAC,OAAO,EAAE,OAAO,EAAE,KAAK,EAAE,qBAAqB,GAAG,MAAM,CAkBpF;AA4DD;;;;GAIG;AACH,wBAAgB,MAAM,CAAC,WAAW,EAAE,WAAW,GAAG,kBAAkB,EAAE,KAAK,CAAC,EAAE,WAAW,GAAG,MAAM,CAQjG"}

package/dist/isa/format.js

@@ -0,0 +1,98 @@
+import { validateFormatStyle } from '../options.js';
+import { REGISTER_NAMES } from './registers.js';
+function register(n, style) {
+    return style.registers === 'numeric' ? `$${String(n)}` : `$${REGISTER_NAMES[n] ?? String(n)}`;
+}
+/** A number in the chosen radix; hexadecimal digits are upper case. */
+export function formatNumber(value, hex) {
+    if (!hex)
+        return String(value);
+    const digits = Math.abs(value).toString(16).toUpperCase();
+    return value < 0 ? `-0x${digits}` : `0x${digits}`;
+}
+/** A branch target relative to the branch itself: `.+12` is two instructions past the delay slot. */
+export function formatDisplacement(displacement) {
+    const bytes = 4 + displacement * 4;
+    return bytes < 0 ? `.-${String(-bytes)}` : `.+${String(bytes)}`;
+}
+export function formatOperand(operand, style) {
+    switch (operand.kind) {
+        case 'gpr':
+            return register(operand.number, style);
+        case 'cop':
+            return `$${String(operand.number)}`;
+        case 'imm':
+            // Trap and syscall codes read naturally in decimal (`break 7`).
+            return formatNumber(operand.value, style.hex && (operand.bits === 16 || operand.bits === 25));
+        case 'shamt':
+            return String(operand.value);
+        case 'mem':
+            return `${formatNumber(operand.offset, style.hex)}(${register(operand.base, style)})`;
+        case 'branch':
+            return formatDisplacement(operand.displacement);
+        case 'target':
+            return formatNumber(operand.index * 4, style.hex);
+    }
+}
+function isZeroRegister(operand) {
+    return operand?.kind === 'gpr' && operand.number === 0;
+}
+/** Apply the pseudo-instruction spellings, and drop optional operands at their defaults. */
+function spelling(instruction, pseudo) {
+    const { mnemonic, operands } = instruction;
+    const [first, second, third] = operands;
+    if (pseudo) {
+        if (mnemonic === 'sll' &&
+            operands.length === 3 &&
+            isZeroRegister(first) &&
+            isZeroRegister(second)) {
+            if (third?.kind === 'shamt' && third.value === 0)
+                return { name: 'nop', operands: [] };
+        }
+        if (mnemonic === 'addu' && operands.length === 3 && isZeroRegister(third)) {
+            return { name: 'move', operands: [first, second].filter((o) => o !== undefined) };
+        }
+        if ((mnemonic === 'beq' || mnemonic === 'bne') &&
+            operands.length === 3 &&
+            isZeroRegister(second)) {
+            return {
+                name: mnemonic === 'beq' ? 'beqz' : 'bnez',
+                operands: [first, third].filter((o) => o !== undefined),
+            };
+        }
+    }
+    if (mnemonic === 'jalr' &&
+        operands.length === 2 &&
+        first?.kind === 'gpr' &&
+        first.number === 31) {
+        return { name: mnemonic, operands: operands.slice(1) };
+    }
+    // A break keeps both codes unless both are zero: `break n` alone would be
+    // split into two codes when re-assembled.
+    if (mnemonic === 'break' && operands.every(isZeroCode))
+        return { name: mnemonic, operands: [] };
+    if ((mnemonic === 'syscall' || (mnemonic === 'tge' && operands.length === 3)) &&
+        isZeroCode(operands.at(-1))) {
+        return { name: mnemonic, operands: operands.slice(0, -1) };
+    }
+    return { name: mnemonic, operands };
+}
+function isZeroCode(operand) {
+    return operand?.kind === 'imm' && operand.value === 0;
+}
+/**
+ * Render one instruction as assembly text: `lw $v0,0x20($s0)`,
+ * `cop2 0x180001`, `.word 0xFFFFFFFF` for an unknown word. Branch targets are
+ * written relative to the branch (`.+12`); `formatProgram` writes labels.
+ */
+export function format(instruction, style) {
+    const normalized = validateFormatStyle(style);
+    if (instruction.mnemonic === '.word') {
+        return `.word 0x${instruction.word.toString(16).toUpperCase().padStart(8, '0')}`;
+    }
+    const { name, operands } = spelling(instruction, normalized.pseudo);
+    if (operands.length === 0)
+        return name;
+    return `${name} ${operands.map((o) => formatOperand(o, normalized)).join(',')}`;
+}
+//# sourceMappingURL=format.js.map

package/dist/isa/format.js.map

@@ -0,0 +1 @@
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package/dist/isa/instruction.d.ts

@@ -0,0 +1,15 @@
+/** Derivations shared by the encoder and decoder: reserved bits and register use. */
+import type { Instruction, Operand } from '../public-types.js';
+import type { IsaRow, RegisterRef } from './table.js';
+/** Bits that must be zero in a word of this row: neither selector nor operand. */
+export declare function reservedBits(row: IsaRow): number;
+/**
+ * Resolve register references against an encoded word. `$0` is hard-wired to
+ * zero, so it is never reported as read or written.
+ */
+export declare function registersOf(refs: readonly RegisterRef[], word: number): number[];
+/** Registers that count as read for the load-delay rule. */
+export declare function hazardReadsOf(row: IsaRow, word: number): number[];
+/** Assemble the public `Instruction` for a row, its canonical operands, and its word. */
+export declare function buildInstruction(row: IsaRow, operands: readonly Operand[], word: number): Instruction;
+//# sourceMappingURL=instruction.d.ts.map

package/dist/isa/instruction.d.ts.map

@@ -0,0 +1 @@
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package/dist/isa/instruction.js

@@ -0,0 +1,47 @@
+import { SLOT_BITS } from './fields.js';
+/** Bits that must be zero in a word of this row: neither selector nor operand. */
+export function reservedBits(row) {
+    const owned = row.syntax.reduce((bits, slot) => bits | SLOT_BITS[slot], row.mask);
+    return ~owned >>> 0;
+}
+function registerOf(ref, word) {
+    switch (ref) {
+        case 'rs':
+            return (word >>> 21) & 31;
+        case 'rt':
+            return (word >>> 16) & 31;
+        case 'rd':
+            return (word >>> 11) & 31;
+        case 31:
+            return 31;
+    }
+}
+/**
+ * Resolve register references against an encoded word. `$0` is hard-wired to
+ * zero, so it is never reported as read or written.
+ */
+export function registersOf(refs, word) {
+    const out = [];
+    for (const ref of refs) {
+        const n = registerOf(ref, word);
+        if (n !== 0 && !out.includes(n))
+            out.push(n);
+    }
+    return out;
+}
+/** Registers that count as read for the load-delay rule. */
+export function hazardReadsOf(row, word) {
+    return registersOf(row.hazardReads ?? row.reads, word);
+}
+/** Assemble the public `Instruction` for a row, its canonical operands, and its word. */
+export function buildInstruction(row, operands, word) {
+    return {
+        mnemonic: row.mnemonic,
+        format: row.format,
+        operands,
+        reads: registersOf(row.reads, word),
+        writes: registersOf(row.writes, word),
+        hazardClass: row.hazard,
+    };
+}
+//# sourceMappingURL=instruction.js.map

package/dist/isa/instruction.js.map

@@ -0,0 +1 @@
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package/dist/isa/registers.d.ts

@@ -0,0 +1,8 @@
+/** General-purpose register names, by number, in the o32 ABI spelling ASPSX accepts. */
+export declare const REGISTER_NAMES: readonly string[];
+/**
+ * Parse a register spelled `$n` (0 to 31) or `$name` (`$zero`, `$v0`, `$s8`,
+ * `$fp`, ...). Returns `undefined` for anything else.
+ */
+export declare function parseRegister(text: string): number | undefined;
+//# sourceMappingURL=registers.d.ts.map

package/dist/isa/registers.d.ts.map

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package/dist/isa/registers.js

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: MIT
+/** General-purpose register names, by number, in the o32 ABI spelling ASPSX accepts. */
+export const REGISTER_NAMES = Object.freeze([
+    'zero',
+    'at',
+    'v0',
+    'v1',
+    'a0',
+    'a1',
+    'a2',
+    'a3',
+    't0',
+    't1',
+    't2',
+    't3',
+    't4',
+    't5',
+    't6',
+    't7',
+    's0',
+    's1',
+    's2',
+    's3',
+    's4',
+    's5',
+    's6',
+    's7',
+    't8',
+    't9',
+    'k0',
+    'k1',
+    'gp',
+    'sp',
+    'fp',
+    'ra',
+]);
+const BY_NAME = new Map([
+    ...REGISTER_NAMES.map((name, index) => [name, index]),
+    ['s8', 30],
+]);
+/**
+ * Parse a register spelled `$n` (0 to 31) or `$name` (`$zero`, `$v0`, `$s8`,
+ * `$fp`, ...). Returns `undefined` for anything else.
+ */
+export function parseRegister(text) {
+    if (!text.startsWith('$'))
+        return undefined;
+    const body = text.slice(1);
+    if (/^(0|[1-9]\d?)$/.test(body)) {
+        const n = Number(body);
+        return n <= 31 ? n : undefined;
+    }
+    return BY_NAME.get(body);
+}
+//# sourceMappingURL=registers.js.map

package/dist/isa/registers.js.map

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