pico-emu 1.0.2 → 1.0.3

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (185) hide show
  1. package/README.md +7 -4
  2. package/about.html +101 -0
  3. package/docs.html +185 -0
  4. package/favicon.ico +0 -0
  5. package/package.json +9 -4
  6. package/picoemu-logo.png +0 -0
  7. package/site.css +308 -0
  8. package/adc_rv32.uf2 +0 -0
  9. package/adc_test.uf2 +0 -0
  10. package/adc_test_pico2.uf2 +0 -0
  11. package/ble_adv_pico2.uf2 +0 -0
  12. package/clocks_rv32.uf2 +0 -0
  13. package/clocks_test.uf2 +0 -0
  14. package/clocks_test_pico2.uf2 +0 -0
  15. package/dma_rv32.uf2 +0 -0
  16. package/dma_test.uf2 +0 -0
  17. package/dma_test_pico2.uf2 +0 -0
  18. package/dualcore_rv32.uf2 +0 -0
  19. package/eth_dhcp6300_pico2.uf2 +0 -0
  20. package/eth_dhcp6300_rv32.uf2 +0 -0
  21. package/eth_dhcp_pico2.uf2 +0 -0
  22. package/eth_dhcp_rv32.uf2 +0 -0
  23. package/eth_http6300_pico2.uf2 +0 -0
  24. package/eth_http6300_rv32.uf2 +0 -0
  25. package/eth_http_pico2.uf2 +0 -0
  26. package/eth_http_rv32.uf2 +0 -0
  27. package/ethdhcp6300_arduino_pico2.uf2 +0 -0
  28. package/examples/adc_rv32.uf2 +0 -0
  29. package/examples/adc_test.uf2 +0 -0
  30. package/examples/adc_test_pico2.uf2 +0 -0
  31. package/examples/ble_adv.uf2 +0 -0
  32. package/examples/ble_adv_pico2.uf2 +0 -0
  33. package/examples/clocks_rv32.uf2 +0 -0
  34. package/examples/clocks_test.uf2 +0 -0
  35. package/examples/clocks_test_pico2.uf2 +0 -0
  36. package/examples/dma_rv32.uf2 +0 -0
  37. package/examples/dma_test.uf2 +0 -0
  38. package/examples/dma_test_pico2.uf2 +0 -0
  39. package/examples/dualcore_rv32.uf2 +0 -0
  40. package/examples/eth_dhcp.uf2 +0 -0
  41. package/examples/eth_dhcp6300.uf2 +0 -0
  42. package/examples/eth_dhcp6300_pico2.uf2 +0 -0
  43. package/examples/eth_dhcp6300_rv32.uf2 +0 -0
  44. package/examples/eth_dhcp_pico2.uf2 +0 -0
  45. package/examples/eth_dhcp_rv32.uf2 +0 -0
  46. package/examples/eth_http.uf2 +0 -0
  47. package/examples/eth_http6300.uf2 +0 -0
  48. package/examples/eth_http6300_pico2.uf2 +0 -0
  49. package/examples/eth_http6300_rv32.uf2 +0 -0
  50. package/examples/eth_http_pico2.uf2 +0 -0
  51. package/examples/eth_http_rv32.uf2 +0 -0
  52. package/examples/fp_test.uf2 +0 -0
  53. package/examples/fp_test_pico2.uf2 +0 -0
  54. package/examples/gpio_rv32.uf2 +0 -0
  55. package/examples/gpio_test_pico2.uf2 +0 -0
  56. package/examples/hello_rv32.uf2 +0 -0
  57. package/examples/hello_usb.uf2 +0 -0
  58. package/examples/hello_world_pico2.uf2 +0 -0
  59. package/examples/i2c_rv32.uf2 +0 -0
  60. package/examples/i2c_test.uf2 +0 -0
  61. package/examples/i2c_test_pico2.uf2 +0 -0
  62. package/examples/interrupt_rv32.uf2 +0 -0
  63. package/examples/interrupt_test.uf2 +0 -0
  64. package/examples/interrupt_test_pico2.uf2 +0 -0
  65. package/examples/littleos_pico2.uf2 +0 -0
  66. package/examples/littleos_pico2_riscv.uf2 +0 -0
  67. package/examples/name_prompt.uf2 +0 -0
  68. package/examples/name_prompt_pico2.uf2 +0 -0
  69. package/examples/name_prompt_rv32.uf2 +0 -0
  70. package/examples/pio_rv32.uf2 +0 -0
  71. package/examples/pio_test.uf2 +0 -0
  72. package/examples/pio_test_pico2.uf2 +0 -0
  73. package/examples/psm_rv32.uf2 +0 -0
  74. package/examples/psm_test.uf2 +0 -0
  75. package/examples/psm_test_pico2.uf2 +0 -0
  76. package/examples/pwm_rv32.uf2 +0 -0
  77. package/examples/pwm_test.uf2 +0 -0
  78. package/examples/pwm_test_pico2.uf2 +0 -0
  79. package/examples/rtc_rv32.uf2 +0 -0
  80. package/examples/rtc_test.uf2 +0 -0
  81. package/examples/rtc_test_pico2.uf2 +0 -0
  82. package/examples/spi_rv32.uf2 +0 -0
  83. package/examples/spi_test.uf2 +0 -0
  84. package/examples/spi_test_pico2.uf2 +0 -0
  85. package/examples/timer_rv32.uf2 +0 -0
  86. package/examples/timer_test.uf2 +0 -0
  87. package/examples/timer_test_pico2.uf2 +0 -0
  88. package/examples/uart_echo.uf2 +0 -0
  89. package/examples/uart_echo_pico2.uf2 +0 -0
  90. package/examples/uart_echo_rv32.uf2 +0 -0
  91. package/examples/usb_rv32.uf2 +0 -0
  92. package/examples/usb_test.uf2 +0 -0
  93. package/examples/usb_test_pico2.uf2 +0 -0
  94. package/examples/wifi_ble_adv_rv32.uf2 +0 -0
  95. package/examples/wifi_ble_gatt_rv32.uf2 +0 -0
  96. package/examples/wifi_join_rv32.uf2 +0 -0
  97. package/examples/wifi_ping.uf2 +0 -0
  98. package/examples/wifi_ping6_rv32.uf2 +0 -0
  99. package/examples/wifi_ping_pico2.uf2 +0 -0
  100. package/examples/wifi_ping_rv32.uf2 +0 -0
  101. package/examples/wifi_rv32.uf2 +0 -0
  102. package/examples/wifi_scan_pico2.uf2 +0 -0
  103. package/examples/wifi_scan_rv32.uf2 +0 -0
  104. package/examples/wifi_webserver.uf2 +0 -0
  105. package/examples/wifi_webserver_pico2.uf2 +0 -0
  106. package/examples/wifi_webserver_rv32.uf2 +0 -0
  107. package/examples/ws2812_rv32.uf2 +0 -0
  108. package/examples/ws2812_test.uf2 +0 -0
  109. package/examples/ws2812_test_pico2.uf2 +0 -0
  110. package/fp_test.uf2 +0 -0
  111. package/fp_test_pico2.uf2 +0 -0
  112. package/gpio_rv32.uf2 +0 -0
  113. package/gpio_test.uf2 +0 -0
  114. package/gpio_test_pico2.uf2 +0 -0
  115. package/hello_rv32.uf2 +0 -0
  116. package/hello_usb.uf2 +0 -0
  117. package/hello_world.uf2 +0 -0
  118. package/hello_world_pico2.uf2 +0 -0
  119. package/i2c_rv32.uf2 +0 -0
  120. package/i2c_test.uf2 +0 -0
  121. package/i2c_test_pico2.uf2 +0 -0
  122. package/interrupt_rv32.uf2 +0 -0
  123. package/interrupt_test.uf2 +0 -0
  124. package/interrupt_test_pico2.uf2 +0 -0
  125. package/littleos.uf2 +0 -0
  126. package/littleos_pico2.uf2 +0 -0
  127. package/littleos_pico2_riscv.uf2 +0 -0
  128. package/micropython_rp2040.uf2 +0 -0
  129. package/micropython_rp2350.uf2 +0 -0
  130. package/name_prompt.uf2 +0 -0
  131. package/name_prompt_pico2.uf2 +0 -0
  132. package/name_prompt_rv32.uf2 +0 -0
  133. package/pio_rv32.uf2 +0 -0
  134. package/pio_test.uf2 +0 -0
  135. package/pio_test_pico2.uf2 +0 -0
  136. package/psm_rv32.uf2 +0 -0
  137. package/psm_test.uf2 +0 -0
  138. package/psm_test_pico2.uf2 +0 -0
  139. package/pwm_rv32.uf2 +0 -0
  140. package/pwm_test.uf2 +0 -0
  141. package/pwm_test_pico2.uf2 +0 -0
  142. package/rtc_rv32.uf2 +0 -0
  143. package/rtc_test.uf2 +0 -0
  144. package/rtc_test_pico2.uf2 +0 -0
  145. package/spi_rv32.uf2 +0 -0
  146. package/spi_test.uf2 +0 -0
  147. package/spi_test_pico2.uf2 +0 -0
  148. package/timer_rv32.uf2 +0 -0
  149. package/timer_test.uf2 +0 -0
  150. package/timer_test_pico2.uf2 +0 -0
  151. package/uart_echo.uf2 +0 -0
  152. package/uart_echo_pico2.uf2 +0 -0
  153. package/uart_echo_rv32.uf2 +0 -0
  154. package/usb_rv32.uf2 +0 -0
  155. package/usb_test.uf2 +0 -0
  156. package/usb_test_pico2.uf2 +0 -0
  157. package/wifi_ble_adv_rv32.uf2 +0 -0
  158. package/wifi_ble_gatt_rv32.uf2 +0 -0
  159. package/wifi_join_rv32.uf2 +0 -0
  160. package/wifi_ping.uf2 +0 -0
  161. package/wifi_ping6_rv32.uf2 +0 -0
  162. package/wifi_ping_pico2.uf2 +0 -0
  163. package/wifi_ping_rv32.uf2 +0 -0
  164. package/wifi_rv32.uf2 +0 -0
  165. package/wifi_scan.uf2 +0 -0
  166. package/wifi_scan_pico2.uf2 +0 -0
  167. package/wifi_scan_rv32.uf2 +0 -0
  168. package/wifi_webserver.uf2 +0 -0
  169. package/wifi_webserver_pico2.uf2 +0 -0
  170. package/wifi_webserver_rv32.uf2 +0 -0
  171. package/ws2812_rv32.uf2 +0 -0
  172. package/ws2812_test.uf2 +0 -0
  173. package/ws2812_test_pico2.uf2 +0 -0
  174. /package/{ble_adv.uf2 → firmware/ble_adv.uf2} +0 -0
  175. /package/{eth_dhcp.uf2 → firmware/eth_dhcp.uf2} +0 -0
  176. /package/{eth_dhcp6300.uf2 → firmware/eth_dhcp6300.uf2} +0 -0
  177. /package/{eth_http.uf2 → firmware/eth_http.uf2} +0 -0
  178. /package/{eth_http6300.uf2 → firmware/eth_http6300.uf2} +0 -0
  179. /package/{ethdhcp6300_arduino.uf2 → firmware/ethdhcp6300_arduino.uf2} +0 -0
  180. /package/{examples → firmware}/gpio_test.uf2 +0 -0
  181. /package/{examples → firmware}/hello_world.uf2 +0 -0
  182. /package/{examples → firmware}/littleos.uf2 +0 -0
  183. /package/{examples → firmware}/micropython_rp2040.uf2 +0 -0
  184. /package/{examples → firmware}/micropython_rp2350.uf2 +0 -0
  185. /package/{examples → firmware}/wifi_scan.uf2 +0 -0
package/README.md CHANGED
@@ -64,9 +64,12 @@ dropdowns: RP2040 / M33 / RV32). Serve the package dir and open it, or copy
64
64
 
65
65
  ## Firmware in this package
66
66
 
67
- Top level: one UF2 per demo (`*_test.uf2` RP2040, `*_pico2.uf2` M33,
68
- `*_rv32.uf2` RV32) plus `littleos*.uf2` and `micropython*.uf2`.
69
- `examples/` mirrors the same set for the UI dropdowns.
67
+ `firmware/` ships a curated demo set (browser UI dropdowns load from here):
68
+ `hello_world`, `gpio_test`, `eth_dhcp` + `eth_http` (W5500, pico-eth),
69
+ `eth_dhcp6300` + `eth_http6300` + `ethdhcp6300_arduino` (W6300, pico-w6300),
70
+ `micropython_rp2040` + `micropython_rp2350`, `ble_adv`, `wifi_scan`,
71
+ `littleos`. Full per-arch build output (90 UF2s incl. `_pico2`/`_rv32`
72
+ variants) lives in the GitHub repo under `web/` — run the sweep there.
70
73
 
71
74
  Networking extras: `eth_dhcp{,_pico2,_rv32}.uf2` + `eth_http{,_pico2,_rv32}.uf2`
72
75
  (W5500 DHCP + HTTP client, pico-eth on SPI0 — pick the board in the UI,
@@ -92,4 +95,4 @@ options; live host sockets for IPv4 + IPv6 (loopback-verified).
92
95
 
93
96
  ## License
94
97
 
95
- MIT — see LICENSE (upstream © 2025 Night-Traders-Dev).
98
+ MIT — see LICENSE (© 2026 danish9661; upstream © 2025 Night-Traders-Dev).
package/about.html ADDED
@@ -0,0 +1,101 @@
1
+ <!DOCTYPE html>
2
+ <html lang="en">
3
+ <head>
4
+ <meta charset="UTF-8">
5
+ <meta name="viewport" content="width=device-width, initial-scale=1.0">
6
+ <title>About — Pico-emu RP2040/RP2350 emulator</title>
7
+ <meta name="description" content="What Pico-emu is, how the emulator is built, and how the three CPU cores map onto RP2040 and RP2350 silicon.">
8
+ <link rel="icon" type="image/png" href="./picoemu-logo.png">
9
+ <link rel="preconnect" href="https://fonts.googleapis.com">
10
+ <link rel="preconnect" href="https://fonts.gstatic.com" crossorigin>
11
+ <link href="https://fonts.googleapis.com/css2?family=Space+Grotesk:wght@400;500;700&family=IBM+Plex+Mono:wght@400;500&display=swap" rel="stylesheet">
12
+ <link rel="stylesheet" href="./site.css">
13
+ </head>
14
+ <body>
15
+
16
+ <header class="faceplate">
17
+ <a class="brand" href="./index.html" aria-label="Pico-emu home">
18
+ <span class="brand-mark" aria-hidden="true"></span>
19
+ <span>
20
+ <span class="brand-name">Pico-emu</span><br>
21
+ <span class="brand-sub">RP2040 / RP2350 emulator in the browser</span>
22
+ </span>
23
+ </a>
24
+ <nav class="site-nav" aria-label="Site">
25
+ <a href="./index.html">Bench</a>
26
+ <a href="./about.html" aria-current="page">About</a>
27
+ <a href="./docs.html">Docs</a>
28
+ <a href="https://github.com/danish9661/pico-emulator">GitHub</a>
29
+ </nav>
30
+ </header>
31
+
32
+ <main class="page">
33
+ <div class="page-hero">
34
+ <h1>One bench, three cores, two chips.</h1>
35
+ <p class="lede">Pico-emu emulates Raspberry Pi's RP2040 and RP2350 microcontrollers well enough to boot real firmware — littleOS shells, MicroPython, and bare-metal peripheral demos — natively and in the browser through WebAssembly.</p>
36
+ <div class="facts">
37
+ <span class="fact">474 sweep-locked tests · v1.0.2</span>
38
+ <span class="fact">Cortex-M0+ / M33 / Hazard3 RV32</span>
39
+ <span class="fact">native + WASM, same sources</span>
40
+ </div>
41
+ </div>
42
+
43
+ <div class="prose">
44
+ <h2>What this project is</h2>
45
+ <p>Pico-emu is a from-scratch emulator for the RP2040 (dual Cortex-M0+) and the RP2350 (dual Cortex-M33 or dual Hazard3 RISC-V, switched at boot). It loads UF2 and ELF images, models flash, SRAM, the boot path, interrupts, SysTick, and the full peripheral set, and it runs unmodified firmware: the same <code>littleos.uf2</code> or MicroPython build you would flash onto a Pico.</p>
46
+ <p>The emulation core is a port of <a href="https://github.com/Night-Traders-Dev/Bramble">Night-Traders-Dev/Bramble</a> (MIT), extended here with M33 and RISC-V cores, VFP single-precision, a double-precision unit, and host-threaded dual-core execution. The WebAssembly build compiles those exact sources with Emscripten, so the browser bench and the native binary agree instruction for instruction.</p>
47
+
48
+ <h2>How it is put together</h2>
49
+ <p>Three layers, each replaceable without touching the others:</p>
50
+ <ol>
51
+ <li><strong>Cores.</strong> An O(1)-dispatch Thumb engine shared by M0+ and M33 (M33 adds Thumb-2, BASEPRI, its own CPUID, VFP/DCP floating point on top), plus a separate Hazard3 RV32IMAC engine with Zba/Zbb/Zbs/Zcb/Zcmp extensions, CSRs, CLINT, and semihosting.</li>
52
+ <li><strong>Memory and peripherals.</strong> A routed bus (flash/XIP, SRAM, ROM function table, NVIC, SysTick, GPIO, UART, SPI, I2C, PWM, ADC, DMA, PIO, USB, clocks, watchdog, RTC), RP2350 additions (520&nbsp;KB SRAM, 32&nbsp;KB ROM, TIMER1, PIO2, QMI, OTP, BOOTRAM, POWMAN, TICKS), and device models on top (CYW43 WiFi/BT, W5500/W6300 Ethernet, SD/eMMC, sensors).</li>
53
+ <li><strong>Hosts.</strong> A native CLI for speed and scripting, and a WASM embedding (<code>picoemu_step</code> + UART/GPIO/memory exports) that the browser bench, a Node CLI, GDB-over-WebSocket, and virtual-network bridges all share.</li>
54
+ </ol>
55
+
56
+ <div class="arch-diagram">firmware.uf2 ──▶ loader ──┬──▶ Cortex-M0+ ──▶ RP2040 bus ──▶ peripherals ──▶ host
57
+ │ ├──▶ Cortex-M33 ──▶ RP2350 bus ──▶ peripherals ──▶ host
58
+ │ └──▶ Hazard3 RV32 ─▶ RP2350 bus ──▶ peripherals ──▶ host
59
+ │
60
+ └── arch from UF2 family ID or picobin IMAGE_DEF</div>
61
+ <p class="diagram-cap">One loader, three cores, one peripheral set per chip family. The host is either the native CLI loop or the browser frame loop.</p>
62
+
63
+ <h2>The three cores</h2>
64
+ <h3>Cortex-M0+ — the RP2040 core</h3>
65
+ <p>Full Thumb-1 plus BL, MSR/MRS, barriers, NZCV flags, tail-chaining and late-arriving interrupts, PRIMASK/FAULTMASK. Boots through boot2 and the ROM table like real silicon. This is the core behind the classic Pico demos and the RP2040 MicroPython build.</p>
66
+ <h3>Cortex-M33 — the RP2350 ARM core</h3>
67
+ <p>Thumb-2 engine reuse with M33 CPUID, BASEPRI masking, IT-block handling, single-precision VFP and a double-precision unit, running against the RP2350 memory map. Boots littleOS to a shell with a working Sage evaluator. TrustZone (SAU attribution + TT), an 8-region PMSAv8 MPU with faults, the ARMv7-M DSP scalar subset, and the MVE-Helium integer vector subset are all modeled (single Secure world); vector FP/complex beats remain future work.</p>
68
+ <h3>Hazard3 RV32 — the RP2350 RISC-V core</h3>
69
+ <p>A clean-room RV32IMAC implementation with the Zba/Zbb/Zbs/Zcb/Zcmp bit-manipulation and code-size extensions, machine CSRs, CLINT timer and software interrupts, dual-hart launch through the SIO mailbox, and ebreak semihosting. Boots the RISC-V littleOS build to an interactive shell.</p>
70
+
71
+ <div class="callout">
72
+ <strong>RP2350A or RP2350B?</strong>
73
+ Both, as far as software can tell. A and B are package variants of the same die: 30 versus 48 GPIO pins (and 4 versus 8 ADC channels, 16 versus 24 PWM channels). Pico-emu models the full 48-pin die, so firmware written for either package runs; pins 30–47 simply stay quiet on A-package builds.
74
+ </div>
75
+
76
+ <h2>What runs on it</h2>
77
+ <ul>
78
+ <li>littleOS interactive shells on all three cores, including Sage <code>print(6*7)</code> evaluation.</li>
79
+ <li>MicroPython REPLs over USB CDC (RP2040 and RP2350 builds), tested with banner plus <code>print(6*7) → 42</code>.</li>
80
+ <li>Forty-plus bare-metal self-tests covering every peripheral, plus WiFi scan/ping/join, BLE advertise and GATT (RV32 reference path), IPv6 ping, dual-core demos, and in-tree W5500 + W6300 DHCP + HTTP-client guests on all three cores.</li>
81
+ <li>Wired Ethernet on WIZnet W5500-EVB-Pico/Pico2 and W6300-EVB-Pico/Pico2 carriers: the W5500 is a register-level IPv4 offload NIC; the W6300 is a dual IPv4/IPv6 offload NIC (TCP6/UDP6/IPRAW6/TCPD/UDPD, CONNECT6/SEND6, masked interrupts, retry engine, keep-alive, Wake-on-LAN). Both join the same gateway as WiFi from MACRAW socket 0; Arduino <code>W6300lwIP</code> DHCP runs unmodified via a PIO-QSPI bridge.</li>
82
+ <li>Live MicroPython on a Pico W build: WiFi station, BLE <code>active(True)</code> with the full HCI bring-up trace, advertising, and GATT register/write/read.</li>
83
+ </ul>
84
+
85
+ <h2>How to check any claim</h2>
86
+ <p>Every statement on this page traces to something runnable: <code>ctest --test-dir build</code> for the 474 unit tests, <code>node test-wasm.js</code> for the browser equivalents, the UF2 dropdown on the bench page for firmware, and the <a href="./docs.html">support tables</a> for the per-feature, per-core breakdown with remarks.</p>
87
+ </div>
88
+ </main>
89
+
90
+ <footer class="page-footer">
91
+ <span>Pico-emu — a browser bench for RP2040 and RP2350 firmware.</span>
92
+ <nav aria-label="Footer">
93
+ <a href="./index.html">Bench</a>
94
+ <a href="./docs.html">Support tables</a>
95
+ <a href="https://github.com/danish9661/pico-emulator">GitHub repo</a>
96
+ <a href="https://github.com/Night-Traders-Dev/Bramble">Upstream Bramble</a>
97
+ </nav>
98
+ </footer>
99
+
100
+ </body>
101
+ </html>
package/docs.html ADDED
@@ -0,0 +1,185 @@
1
+ <!DOCTYPE html>
2
+ <html lang="en">
3
+ <head>
4
+ <meta charset="UTF-8">
5
+ <meta name="viewport" content="width=device-width, initial-scale=1.0">
6
+ <title>Docs — Pico-emu per-core support tables</title>
7
+ <meta name="description" content="Feature support tables for RP2040 Cortex-M0+, RP2350 Cortex-M33, and RP2350 Hazard3 RV32 in the Pico-emu emulator.">
8
+ <link rel="icon" type="image/png" href="./picoemu-logo.png">
9
+ <link rel="preconnect" href="https://fonts.googleapis.com">
10
+ <link rel="preconnect" href="https://fonts.gstatic.com" crossorigin>
11
+ <link href="https://fonts.googleapis.com/css2?family=Space+Grotesk:wght@400;500;700&family=IBM+Plex+Mono:wght@400;500&display=swap" rel="stylesheet">
12
+ <link rel="stylesheet" href="./site.css">
13
+ </head>
14
+ <body>
15
+
16
+ <header class="faceplate">
17
+ <a class="brand" href="./index.html" aria-label="Pico-emu home">
18
+ <span class="brand-mark" aria-hidden="true"></span>
19
+ <span>
20
+ <span class="brand-name">Pico-emu</span><br>
21
+ <span class="brand-sub">RP2040 / RP2350 emulator in the browser</span>
22
+ </span>
23
+ </a>
24
+ <nav class="site-nav" aria-label="Site">
25
+ <a href="./index.html">Bench</a>
26
+ <a href="./about.html">About</a>
27
+ <a href="./docs.html" aria-current="page">Docs</a>
28
+ <a href="https://github.com/danish9661/pico-emulator">GitHub</a>
29
+ </nav>
30
+ </header>
31
+
32
+ <main class="page">
33
+ <div class="page-hero">
34
+ <h1>What each core supports.</h1>
35
+ <p class="lede">Three tables — one per emulated core — listing every feature area, what was done, what is still missing, and the remark that explains the gap. Status words mean: done (verified), partial (works with known limits), missing (not modeled).</p>
36
+ <div class="facts">
37
+ <span class="fact">474 tests · v1.0.2</span>
38
+ <span class="fact">native + WASM agree</span>
39
+ <span class="fact">A and B packages both run</span>
40
+ </div>
41
+ </div>
42
+
43
+ <div class="prose">
44
+ <div class="callout">
45
+ <strong>RP2350A or RP2350B — do we support them?</strong>
46
+ Yes, both. The A/B split is packaging, not silicon: the same die in a 60-pin package (30 GPIO, 4 ADC channels, 16 PWM channels) or an 80-pin package (48 GPIO, 8 ADC, 24 PWM). Pico-emu models the full die — 48 GPIO, 8 ADC channels, 16 DMA channels, 3 PIO blocks — so A-package firmware runs unchanged and the extra B pins stay idle. RP2354 variants (stacked 2&nbsp;MB flash) behave like external flash here: capacity is configurable up to 16&nbsp;MB.
47
+ </div>
48
+
49
+ <h2>Pico 1 — RP2040, Cortex-M0+</h2>
50
+ <p>Dual M0+ at up to 133&nbsp;MHz on real silicon (configurable here), 264&nbsp;KB SRAM, 16&nbsp;KB ROM, 2&nbsp;MB external flash. The reference core: everything below is verified by peripheral self-tests plus littleOS and MicroPython boots.</p>
51
+ </div>
52
+ <div class="table-scroll" role="region" aria-label="RP2040 Cortex-M0+ support table" tabindex="0">
53
+ <table class="support">
54
+ <caption>Pico 1 · RP2040 · Cortex-M0+</caption>
55
+ <thead><tr><th scope="col">Feature</th><th scope="col">Status</th><th scope="col">What was done</th><th scope="col">What is left</th><th scope="col">Remark</th></tr></thead>
56
+ <tbody>
57
+ <tr><td>Thumb-1 ISA + BL/MSR/MRS/barriers</td><td><span class="pill done">done</span></td><td>O(1) dispatch, NZCV flags, 65+ instructions</td><td>Nothing open</td><td>Reference ISA; M33 reuses this engine</td></tr>
58
+ <tr><td>NVIC + exceptions</td><td><span class="pill done">done</span></td><td>Tail-chaining, late-arriving, PRIMASK/FAULTMASK, 4 priority levels, user IRQs 26–31</td><td>Nothing open</td><td>User IRQs carry the TinyUSB pump</td></tr>
59
+ <tr><td>SysTick + timer + RTC + watchdog</td><td><span class="pill done">done</span></td><td>64-bit timer, 4 alarms, calendar rollover, WDT reboot with multicore reset</td><td>Nothing open</td><td>WFI fast-forwards to the next alarm</td></tr>
60
+ <tr><td>Boot (vector table, boot2, ROM)</td><td><span class="pill done">done</span></td><td>16&nbsp;KB ROM table incl. soft-float/double and flash-write helpers</td><td>Nothing open</td><td>littleOS and MicroPython boot through it</td></tr>
61
+ <tr><td>GPIO 0–29 (SIO, IO_BANK0, PADS)</td><td><span class="pill done">done</span></td><td>Edge/level IRQs, atomic aliases, divider/interpolators/spinlocks</td><td>Nothing open</td><td>LED25 demos sweep-locked</td></tr>
62
+ <tr><td>UART ×2 (PL011)</td><td><span class="pill done">done</span></td><td>Dual ports, 16-deep FIFOs, Tx/Rx IRQs, stdin routing</td><td>Nothing open</td><td>littleOS shell path</td></tr>
63
+ <tr><td>SPI ×2 (PL022)</td><td><span class="pill done">done</span></td><td>Dual ports, FIFOs, attachable devices</td><td>Nothing open</td><td>Carries SD cards and the CYW43</td></tr>
64
+ <tr><td>I2C ×2</td><td><span class="pill done">done</span></td><td>16-deep RX FIFO, device callbacks</td><td>Nothing open</td><td>TMP102/EEPROM models attach here</td></tr>
65
+ <tr><td>PWM (8 slices / 16 channels)</td><td><span class="pill done">done</span></td><td>CSR/DIV/CTR/CC/TOP, interrupts</td><td>Nothing open</td><td>B-package extras do not exist on this die</td></tr>
66
+ <tr><td>ADC (4 channels + temp)</td><td><span class="pill done">done</span></td><td>5 channels, FIFO, round-robin, ~27&nbsp;°C sensor</td><td>Nothing open</td><td>B package would add 4 more channels</td></tr>
67
+ <tr><td>DMA (12 channels)</td><td><span class="pill done">done</span></td><td>Chaining, 4 alias layouts</td><td>Cycle pacing is a functional model</td><td>Correct data, approximate timing</td></tr>
68
+ <tr><td>PIO (2 blocks, 9 opcodes)</td><td><span class="pill done">done</span></td><td>Full instruction exec, FIFOs, dividers</td><td>Very-high-speed timing approximate</td><td>Drives the CYW43 gSPI path</td></tr>
69
+ <tr><td>USB device (CDC)</td><td><span class="pill done">done</span></td><td>Host enumeration, multi-packet IN, CDC bridge, stdio_usb</td><td>Non-CDC classes unmodeled</td><td>MicroPython REPL + hello_usb verified</td></tr>
70
+ <tr><td>Clocks/XOSC/PLLs/resets</td><td><span class="pill done">done</span></td><td>10 generators, FC0, lock/status bits</td><td>Nothing open</td><td>SDK clock setup runs unmodified</td></tr>
71
+ <tr><td>XIP flash + cache</td><td><span class="pill done">done</span></td><td>2&nbsp;MB, aliases, 16&nbsp;KB cache-as-SRAM</td><td>Cache timing not modeled</td><td>Always ready, like a warm cache</td></tr>
72
+ <tr><td>Dual-core (host-threaded)</td><td><span class="pill done">done</span></td><td>WFI sleep, FIFOs, spinlocks, auto-launch</td><td>Nothing open</td><td>Browser build steps cooperatively</td></tr>
73
+ <tr><td>GDB + 18 devtools</td><td><span class="pill done">done</span></td><td>RSP stub, coverage, trace, VCD, heatmap, fault injection</td><td>Nothing open</td><td>Real GDB session verified</td></tr>
74
+ <tr><td>CYW43 WiFi + BT</td><td><span class="pill done">done</span></td><td>gSPI-over-PIO, scan/join, TAP bridge, HCI responder, GATT loopback, HCI forward</td><td>Physical adapters need root</td><td>Live-MP BLE active + advertise green</td></tr>
75
+ <tr><td>BLE bare-metal guests (all three cores)</td><td><span class="pill done">done</span></td><td><code>ble_adv{,_pico2}.uf2</code> + <code>wifi_ble_adv_rv32.uf2</code>: BT bring-up + ADV + scan over the CYW43 BT bus</td><td>Room SCAN-OK needs a second peer</td><td>LISTEN marker is sweep-locked on all three cores</td></tr>
76
+ <tr><td>SD / eMMC / FUSE flash</td><td><span class="pill done">done</span></td><td>SPI protocols, file-backed, live host mount</td><td>Nothing open</td><td>Combines with MicroPython persistence</td></tr>
77
+ <tr><td>Wired Ethernet (W5500 SPI NIC)</td><td><span class="pill done">done</span></td><td>Register-level W5500: 8 sockets, 2&nbsp;KB buffers, live host dial; in-tree <code>eth_dhcp</code>/<code>eth_http</code> guests (DORA + HTTP client) on all three cores</td><td>ENC28J60/LAN8720 not modeled</td><td>No on-chip MAC exists; W5500 hats and carrier boards work</td></tr>
78
+ <tr><td>Wired Ethernet (W6300 QSPI NIC)</td><td><span class="pill done">done</span></td><td>Register-level W6300 (QSPI-single, CIDR <code>0x61</code>): 8 sockets, 4&nbsp;KB buffers, CHIP/NET/PHY lock groups, masked INT chain, dual IPv4/IPv6 TCP/IP offload (TCP6/UDP6/TCPD/UDPD/IPRAW6, CONNECT6/SEND6, masked SIR/INTn) + retry engine + KPALVTR + WOL; in-tree <code>eth_dhcp6300</code>/<code>eth_http6300</code> guests (DORA + HTTP client) on all three cores + Arduino <code>W6300lwIP</code> PIO-QSPI DORA</td><td>ENC28J60/LAN8720 not modeled; RX layout is silicon PACKET INFO per the W6300 datasheet + io6Library (UDP4 8B / UDP6 20B / IPRAW4 6B / IPRAW6 18B)</td><td>Board: <code>pico-w6300</code>/<code>pico-w6300-2</code> (SPI0, CSn16/RSTn22/INTn15); pick it in the Board row, same gateway as WiFi</td></tr>
79
+ </tbody>
80
+ </table>
81
+ </div>
82
+
83
+ <div class="prose">
84
+ <h2>Pico 2 ARM — RP2350, Cortex-M33</h2>
85
+ <p>Dual M33 with FPU at 150&nbsp;MHz, 520&nbsp;KB SRAM, 32&nbsp;KB ROM, 4&nbsp;MB flash on Pico&nbsp;2 boards. The M33 reuses the Thumb engine with an ARMv8-M overlay; RP2350-only blocks are modeled alongside.</p>
86
+ </div>
87
+ <div class="table-scroll" role="region" aria-label="RP2350 Cortex-M33 support table" tabindex="0">
88
+ <table class="support">
89
+ <caption>Pico 2 ARM · RP2350 · Cortex-M33</caption>
90
+ <thead><tr><th scope="col">Feature</th><th scope="col">Status</th><th scope="col">What was done</th><th scope="col">What is left</th><th scope="col">Remark</th></tr></thead>
91
+ <tbody>
92
+ <tr><td>Thumb-2 ISA</td><td><span class="pill done">done</span></td><td>Full decode via shared engine, IT blocks, MOVW/SDIV/UDIV/CBZ</td><td>Nothing open</td><td>Verified against assembler encodings</td></tr>
93
+ <tr><td>BASEPRI + M33 CPUID</td><td><span class="pill done">done</span></td><td>Masked interrupt delivery, 0x410FD210 identification</td><td>Nothing open</td><td>Unit-tested priority masking</td></tr>
94
+ <tr><td>VFP single-precision</td><td><span class="pill done">done</span></td><td>VLDR/VSTR, arithmetic, convert, compare, VSEL</td><td>Dual-core FPU state not saved</td><td>All current workloads are single-core FP</td></tr>
95
+ <tr><td>Double-precision unit</td><td><span class="pill done">done</span></td><td>Deferred-compute model, IEEE-754 via host double</td><td>Nested use across an IRQ clobbers state</td><td>Same limit as the VFP path</td></tr>
96
+ <tr><td>RRX/USAT/SMMULR class fixes</td><td><span class="pill done">done</span></td><td>Barrel-shifter RRX, saturate, signed-multiply group</td><td>Nothing open</td><td>Each fixed a real pico_double/Sage failure</td></tr>
97
+ <tr><td>RP2350 memory map</td><td><span class="pill done">done</span></td><td>520&nbsp;KB SRAM, 32&nbsp;KB ROM, CLINT-adjacent ARM map, picobin parser</td><td>Nothing open</td><td>UF2 family ID auto-selects M33</td></tr>
98
+ <tr><td>TICKS / POWMAN / QMI / OTP / BOOTRAM</td><td><span class="pill done">done</span></td><td>Tick generators, power states, flash config, OTP data, boot scratch</td><td>Deep-sleep power modeling</td><td>Registers behave; current draw does not</td></tr>
99
+ <tr><td>TIMER1 / PIO2 / 48 GPIO</td><td><span class="pill done">done</span></td><td>Second timer, third PIO block, full pin bank</td><td>Pins 30–47 idle on A-package code</td><td>This is the A/B difference, handled</td></tr>
100
+ <tr><td>ADC (8 channels on B)</td><td><span class="pill done">done</span></td><td>Full 9-input mux (GPIO 40–47 + temp on 8), 9-bit RROBIN, 8-deep FIFO</td><td>A-package guests use inputs 0–4 only</td><td>Depth gate keeps RP2040 FULL-at-4 behavior</td></tr>
101
+ <tr><td>PWM (24 channels on B)</td><td><span class="pill done">done</span></td><td>12 slices, 12-bit masks, IRQ0/IRQ1 blocks at 0xF0–0x10C, RP2350 base 0x400A8000</td><td>Nothing open</td><td>RP2040 layout (8 slices, 0xA0 block) kept by mode</td></tr>
102
+ <tr><td>DMA (16 channels)</td><td><span class="pill done">done</span></td><td>All 16 channels, chains, aliases, RP2350 CTRL remap, N_CHANNELS=16</td><td>Cycle pacing is a functional model</td><td>Correct data, approximate timing</td></tr>
103
+ <tr><td>HSTX (DVI output)</td><td><span class="pill done">done</span></td><td>CSR/BITx/EXPAND registers, 8-word FIFO with FULL/WOF, raw + TMDS-encode serializer with TX log</td><td>No pin-level waveform timing</td><td>Firmware produces observable serial bytes</td></tr>
104
+ <tr><td>TRNG / SHA-256</td><td><span class="pill done">done</span></td><td>TRNG: EHR stream + VALID/ISR/IRQ39 + BUSY; SHA-256: real FIPS digest, START/WDATA/SUM, BSWAP</td><td>TRNG is deterministic xorshift, not physical entropy</td><td>SHA-256("abc") matches the FIPS vector</td></tr>
105
+ <tr><td>TrustZone / SAU / MPU</td><td><span class="pill done">done</span></td><td>SAU 8 regions + ALLNS/NSC attribution, MPU 8 regions PMSAv8 + faults (SHCSR/CFSR/HFSR), TT answers</td><td>Single Secure world (no NS memory split)</td><td>TT/MPU/SAU agree; unprogrammed TT still 0</td></tr>
106
+ <tr><td>DSP / MVE-Helium</td><td><span class="pill done">done</span></td><td>DSP scalar: QADD/SUB, ASX/SAX, SHADD/SUB, SMLAD/SD/ALD/SLD, SEL, PKHBT/TB, SSAT16/USAT16 + Q flag; Helium integer vectors: ALU, shifts, loads, VDUP, across-ops, VPST/VPT/VPR</td><td>Helium float ops, complex/coprocessor beats</td><td>All encodings verified against clang</td></tr>
107
+ <tr><td>USB / WiFi / BT / storage / GDB</td><td><span class="pill done">done</span></td><td>Same models as RP2040, on the RP2350 map; in-tree <code>ble_adv_pico2.uf2</code> reaches <code>ARM BLE LISTEN</code></td><td>Same limits as RP2040</td><td>MicroPython RP2350 REPL verified</td></tr>
108
+ <tr><td>Wired Ethernet (W5500 SPI NIC)</td><td><span class="pill done">done</span></td><td>Same SPI NIC model, M33 DMA remap aware; in-tree <code>eth_dhcp_pico2</code>/<code>eth_http_pico2</code> guests</td><td>ENC28J60/LAN8720 not modeled</td><td>No on-chip MAC; W5500 boards work</td></tr>
109
+ <tr><td>Wired Ethernet (W6300 QSPI NIC)</td><td><span class="pill done">done</span></td><td>Same QSPI NIC model (CSn16/RSTn22/INTn15); in-tree <code>eth_dhcp6300_pico2</code>/<code>eth_http6300_pico2</code> guests + Arduino <code>W6300lwIP</code> M33 DORA</td><td>ENC28J60/LAN8720 not modeled; RX layout is silicon PACKET INFO (datasheet + io6Library)</td><td>No on-chip MAC; W6300-EVB-Pico2 boards work</td></tr>
110
+ <tr><td>littleOS + Sage on M33</td><td><span class="pill done">done</span></td><td>Shell boot, eval, floats, health nominal</td><td>Nothing open</td><td><code>print(6*7)</code> → 42</td></tr>
111
+ </tbody>
112
+ </table>
113
+ </div>
114
+
115
+ <div class="prose">
116
+ <h2>Pico 2 RISC-V — RP2350, Hazard3 RV32</h2>
117
+ <p>Dual Hazard3 RV32IMAC cores sharing the same 520&nbsp;KB RP2350 map and peripherals as the M33 build. A separate engine: new decoder, CSRs, CLINT, and bootrom rather than an ARM overlay.</p>
118
+ </div>
119
+ <div class="table-scroll" role="region" aria-label="RP2350 Hazard3 RV32 support table" tabindex="0">
120
+ <table class="support">
121
+ <caption>Pico 2 RISC-V · RP2350 · Hazard3 RV32</caption>
122
+ <thead><tr><th scope="col">Feature</th><th scope="col">Status</th><th scope="col">What was done</th><th scope="col">What is left</th><th scope="col">Remark</th></tr></thead>
123
+ <tbody>
124
+ <tr><td>RV32IMAC base + jumps/branches</td><td><span class="pill done">done</span></td><td>93 instructions, LR/SC atomics, traps, mtvec/MRET</td><td>Nothing open</td><td>Dual-hart with CLINT routing</td></tr>
125
+ <tr><td>Zba / Zbb / Zbs / Zcb / Zcmp</td><td><span class="pill done">done</span></td><td>Bit-manip and code-size groups incl. cm.push/pop</td><td>Zbkb beyond PACK stubs</td><td>Vintage firmware health quirk is stale FW, not emulation</td></tr>
126
+ <tr><td>Hazard3 CSRs + MIE/MPIE routing</td><td><span class="pill done">done</span></td><td>Custom meie/meip/mlei/stack CSRs, external IRQ fan-in</td><td>Nothing open</td><td>SDK interrupt code runs unmodified</td></tr>
127
+ <tr><td>CLINT + bootrom + picobin</td><td><span class="pill done">done</span></td><td>mtime/mtimecmp/MSIP, SP init, flash jump, IMAGE_DEF parse</td><td>Nothing open</td><td>UF2 family auto-selects RV32</td></tr>
128
+ <tr><td>RP2350 peripherals</td><td><span class="pill done">done</span></td><td>Same TICKS/POWMAN/QMI/OTP/BOOTRAM/TIMER1/PIO2/HSTX/TRNG/SHA-256 model via shared bus</td><td>Nothing open</td><td>One model serves both RP2350 cores</td></tr>
129
+ <tr><td>GPIO / UART / SPI / I2C / PWM / ADC / DMA / PIO</td><td><span class="pill done">done</span></td><td>Shared-bus translation onto RP2040-semantics handlers (full B-package channels)</td><td>Nothing open</td><td>All RV32 self-tests sweep green</td></tr>
130
+ <tr><td>USB / WiFi / BT / IPv6</td><td><span class="pill done">done</span></td><td>BLE advertise + GATT-DONE, ping6, room mesh verified</td><td>Same limits as M33</td><td>RV32 BLE demos are the reference path</td></tr>
131
+ <tr><td>Wired Ethernet (W5500 SPI NIC)</td><td><span class="pill done">done</span></td><td>Same SPI NIC model over the shared bus; in-tree <code>eth_dhcp_rv32</code>/<code>eth_http_rv32</code> guests</td><td>ENC28J60/LAN8720 not modeled</td><td>No on-chip MAC; W5500 boards work</td></tr>
132
+ <tr><td>Wired Ethernet (W6300 QSPI NIC)</td><td><span class="pill done">done</span></td><td>Same QSPI NIC model over the shared bus; in-tree <code>eth_dhcp6300_rv32</code>/<code>eth_http6300_rv32</code> guests</td><td>ENC28J60/LAN8720 not modeled; RX layout is silicon PACKET INFO (datasheet + io6Library)</td><td>No on-chip MAC; W6300-EVB-Pico boards work</td></tr>
133
+ <tr><td>FPU (Zfinx / single-float)</td><td><span class="pill done">done</span></td><td>FLW/FSW, FADD/SUB/MUL/DIV/SQRT, SGNJ/MIN/MAX, converts, moves, compares, CLASS, FMADD/SUB, fcsr + NX/UF/OF/DZ/NV</td><td>Double-float (D extension) not present on Hazard3</td><td>Softfloat firmware runs natively now</td></tr>
134
+ <tr><td>HSTX / TRNG / SHA-256</td><td><span class="pill done">done</span></td><td>Same engines as M33 (shared bus)</td><td>Same notes as M33</td><td>Shared model, one fix covers both</td></tr>
135
+ <tr><td>littleOS shell on RV32</td><td><span class="pill done">done</span></td><td>Shell boot via PSM + shadow bypasses</td><td>Nothing open</td><td>Sage eval verified like M33</td></tr>
136
+ <tr><td>Semihosting / GDB / ICache</td><td><span class="pill done">done</span></td><td>EBREAK protocol, RV register layout, 64K decode cache</td><td>Nothing open</td><td>single-core by firmware design</td></tr>
137
+ </tbody>
138
+ </table>
139
+ </div>
140
+
141
+ <div class="prose">
142
+ <h2>Guides</h2>
143
+ <h3>Wired Ethernet: is there any on these chips?</h3>
144
+ <p>Neither the RP2040 nor the RP2350 has an on-chip Ethernet MAC — there is nothing to route to pins, on any package. Boards that advertise Ethernet with these chips always add a separate controller over SPI. The boards you have seen are almost certainly WIZnet W5500 designs (hardwired TCP/IP stack, very common on Pico-shaped Ethernet hats) or, less often, Microchip ENC28J60 or LAN8720 PHY boards.</p>
145
+ <p>Pico-emu emulates the W5500 itself as an SPI device (<code>src/w5500.c</code>): 8 sockets with 2&nbsp;KB TX/RX buffers each, register-level compatible, with a live mode (<code>-net-live</code> natively, WebSocket proxy in the browser) that dials real host TCP/UDP sockets. So W5500-based firmware and carrier boards work here; what is modeled is the external chip, not silicon Ethernet — because the silicon has none.</p>
146
+ <h3>pico-w6300 board: WIZnet W6300-EVB-Pico (and Pico2)</h3>
147
+ <p>The <code>pico-w6300</code> board variant models the actual WIZnet W6300-EVB-Pico carrier: the W6300 on <strong>SPI0 QSPI-single</strong> with <strong>CSn&nbsp;=&nbsp;GPIO16</strong>, <strong>RSTn&nbsp;=&nbsp;GPIO22</strong>, <strong>INTn&nbsp;=&nbsp;GPIO15</strong> (active-low). Chip ID <code>CIDR 0x61/0x00/0x11</code>, CHIP/NET/PHY lock groups (<code>0xCE/0x3A/0x53</code> unlock), 4&nbsp;KB buffers per direction, <code>Sn_IRCLR</code> W1C. The W6300 is a dual IPv4/IPv6 hardwired TCP/IP controller, and the model covers the full feature set: IPv6 net registers (LLAR/GUAR/SUB6R/GA6R, SLDIP6R, UIP6R), socket modes TCP6/UDP6/IPRAW6/TCPD/UDPD, commands CONNECT6/SEND6/SEND_KEEP/SEND_MAC, the masked interrupt chain (Sn_IR&amp;Sn_IMR → SIR&amp;SIMR → INTn, plus common IR/SLIR masks and IEN gate), the RTR/RCR retry engine with TIMEOUT, KPALVTR auto-keepalive, NETMR WOL magic-packet detect, and TTL/TOS/MSS socket options. Socket 0 in <code>MR_MACRAW</code> joins the same shared vnet bus as CYW43/W5500, so the same gateway serves WiFi + both Ethernet chips. Probe it from the Examples dropdowns: <code>ETH DHCP (pico-w6300)</code>, <code>ETH DHCP Arduino (pico-w6300)</code>, <code>ETH HTTP (pico-w6300)</code> (M0+, M33, and RV32 variants).</p>
148
+ <p>Native: <code>./build/picoemu firmware.uf2 -board pico-w6300</code> for the stub, plus <code>-board6300-live</code> to dial real host TCP/UDP (IPv4 + IPv6 loopback-verified; raw IPRAW sockets need privilege). Browser bench: pick <code>pico-w6300</code> in the Board row (SPI + live tickbox); Node: <code>node web/cli.js firmware.uf2 --board pico-w6300 --board-live</code>. Off by default with zero cost. <strong>Version 2?</strong> Yes — <code>pico-w6300-2</code> is the RP2350-based WIZnet W6300-EVB-Pico2 (same wiring/pins, only the SoC changes; RP2350 SPI bases route identically).</p>
149
+ <h3>pico-eth board: WIZnet W5500-EVB-Pico (and Pico2)</h3>
150
+ <p>The legacy <code>-net-live</code> device floats on the SPI bus with no board pins. The <code>pico-eth</code> board variant models the actual WIZnet W5500-EVB-Pico carrier: the same W5500 on <strong>SPI0</strong> (SCK&nbsp;18 / MOSI&nbsp;19 / MISO&nbsp;16, mode&nbsp;0/3) with <strong>CSn&nbsp;=&nbsp;GPIO17</strong>, <strong>RSTn&nbsp;=&nbsp;GPIO20</strong>, <strong>INTn&nbsp;=&nbsp;GPIO21</strong> (active-low). Firmware bit-bangs CSn/RSTn as GPIOs and polls or waits on INTn exactly like on hardware; VERSIONR reads <code>0x04</code>, socket IR bits are write-1-to-clear, and SIR is computed from live socket state.</p>
151
+ <p>Native: <code>./build/picoemu firmware.uf2 -board pico-eth</code> for the stub (instant ESTABLISHED, no host sockets), plus <code>-board-live</code> to dial real host TCP/UDP, <code>-board-spi 0|1</code> to move the board (default&nbsp;0). Explicit <code>-sdcard</code>/<code>-emmc</code> flags win the SPI slot on conflict. Browser bench: pick <code>pico-eth</code> in the Board row (SPI + live tickbox); Node: <code>node web/cli.js firmware.uf2 --board pico-eth --board-live</code>. Off by default with zero cost: one flag test in the GPIO/poll hooks, no device attached, no sockets polled.</p>
152
+ <p><strong>Version 2?</strong> Yes — <code>pico-eth2</code> is an accepted alias for the RP2350-based WIZnet W5500-EVB-Pico2. It selects the identical model: WIZnet kept the exact same wiring and pins on the Pico2 board (verified against their docs, the Zephyr board DTS, and the MicroPython board ports), so only the SoC changes. On M33/RV32 firmware the RP2350 SPI bases (<code>0x40080000</code>/<code>0x40088000</code>) route to the same SPI instances; GPIO17/20/21 behave identically (SIO base is unchanged at <code>0xD0000000</code>).</p>
153
+ <h3>Run firmware</h3>
154
+ <p>Native: <code>cmake -S . -B build &amp;&amp; cmake --build build -j</code>, then <code>./build/picoemu firmware.uf2 -clock 125</code>. Add <code>-stdin</code> for interactive shells, <code>-wifi</code> for the CYW43, <code>-gdb</code> for remote debugging. The browser bench mirrors every flag with a control on the page.</p>
155
+ <h3>Browser and Node</h3>
156
+ <p><code>./build_wasm.sh</code> produces the WASM pair; serve <code>web/</code> over HTTP and open the bench, or drive it headless with <code>node test-wasm.js</code> and <code>node test-mp-ble-live.mjs</code>. The <code>-pthread</code> threads build needs cross-origin isolation (<code>python3 web/serve_coop.py</code>).</p>
157
+ <h3>Networking and Bluetooth</h3>
158
+ <p>Virtual Ethernet (<code>-net</code>, <code>-net-peer</code>), live sockets (<code>-net-live</code>, <code>web/net_proxy.py</code>), gateway NAT64/DNS64, and BLE either internally (advertise, scan room, GATT loopback) or forwarded to Bumble/RootCanal/physical adapters (<code>-bt-hci</code>, <code>web/hci_bridge.py</code>). Details live in <code>docs/NETWORKING.md</code> and <code>docs/GATEWAY.md</code>.</p>
159
+ <h3>WASM networking: one gateway for WiFi + Ethernet</h3>
160
+ <p>Yes — WASM fully emulates the W5500 chip (same <code>src/w5500.c</code> registers, sockets, and SPI framing as native). There is a <strong>single gateway</strong>: socket&nbsp;0 in <code>MACRAW</code> mode joins the same vnet bus as CYW43, so guest DHCP/ARP/IP flow as raw Ethernet frames to the same Go gateway (<code>ws://host:5090/api/network-gateway</code>), same room, same DHCP pool. Browser: tick <code>Ethernet via gateway</code> (default on) and open the Gateway panel; the per-frame pump forwards <code>picoemu_eth_pop_tx()</code> both ways automatically. Node: pass <code>--gateway …</code> — no proxy sockets needed for the gateway path.</p>
161
+ <p>The same holds for the W6300: the browser bench compiles the same <code>src/w6300.c</code> model (QSPI-single framing, full IPv6 register/offload surface, PIO-QSPI bridge for the Arduino driver) with its own pump (<code>picoemu_w6300_pop_tx</code> / <code>push_rx</code> / <code>push_status</code>, CONNECT6/SEND6/LISTEN6 framing understood by <code>web/net_proxy.py</code>). Pick <code>pico-w6300</code> in the Board row and run any <code>pico-w6300</code> Example; MACRAW socket 0 joins the same gateway as WiFi/W5500.</p>
162
+ <p>The older per-socket <code>/w5500</code> proxy path (<code>web/net_proxy.py</code> dialing host TCP/UDP per socket) still exists for offload sockets&nbsp;1–7, but it is <em>not</em> a second gateway: it bypasses DHCP/rooms by design. Prefer MACRAW. Full matrix — DHCP, ARP, coexistence, RP2350 — lives in <code>docs/NETWORKING.md</code> under “Ethernet (W5500 MACRAW) support matrix”.</p>
163
+ <h3>Docs map</h3>
164
+ <ul>
165
+ <li><code>README.md</code> — build, run, test, coverage tables.</li>
166
+ <li><code>docs/ROADMAP.md</code> — release history from v0.36 to present.</li>
167
+ <li><code>docs/PICOEMU.md</code> — every WASM export with signatures.</li>
168
+ <li><code>docs/NETWORKING.md</code> — vnet, gateway, BLE matrix.</li>
169
+ <li><code>docs/GPIO.md</code> — pin model. <code>docs/WASM.md</code> — browser build. <code>docs/GATEWAY.md</code> — gateway protocol.</li>
170
+ </ul>
171
+ </div>
172
+ </main>
173
+
174
+ <footer class="page-footer">
175
+ <span>Pico-emu — a browser bench for RP2040 and RP2350 firmware.</span>
176
+ <nav aria-label="Footer">
177
+ <a href="./index.html">Bench</a>
178
+ <a href="./about.html">About this project</a>
179
+ <a href="https://github.com/danish9661/pico-emulator">GitHub repo</a>
180
+ <a href="https://github.com/Night-Traders-Dev/Bramble">Upstream Bramble</a>
181
+ </nav>
182
+ </footer>
183
+
184
+ </body>
185
+ </html>
package/favicon.ico ADDED
Binary file
package/package.json CHANGED
@@ -1,7 +1,7 @@
1
1
  {
2
2
  "name": "pico-emu",
3
- "version": "1.0.2",
4
- "description": "v1.0.2 — package renamed to pico-emu, repo moved to pico-emulator This release renames and relocates the project. No emulation changes since 1.0.1 (474/474 tests, sweep 70/70 carry over). What changed The npm package is now pico-emu. Install with npm i pico-emu and run with npx pico-emu. The old picoemu name stays published but deprecated. The repo moved to danish9661/pico-emulator. Demo site is now danish9661.github.io/pico-emulator. All badges, links, CLI usage lines and the publish workflow point at the new names. LICENSE now lists danish9661 first, keeping the upstream Night-Traders-Dev line as MIT requires. README rewritten (was 844 lines, now ~455): fixed dead alarm_test.uf2 references, corrected MicroPython to bundled v1.22.1, refreshed test counts, condensed the reference sections. Website now has GitHub repo buttons in the nav and footer of all three pages (Bench, About, Docs). Install npm i pico-emu npx pico-emu hello_world.uf2 Verified 474/474 unit tests, sweep 70/70, WASM + threads rebuilt, test-wasm PASS.",
3
+ "version": "1.0.3",
4
+ "description": "project struture update",
5
5
  "type": "module",
6
6
  "main": "picoemu.wasm.js",
7
7
  "bin": {
@@ -21,7 +21,12 @@
21
21
  "picoemu_worker.js",
22
22
  "cli.js",
23
23
  "index.html",
24
- "*.uf2",
25
- "examples/*.uf2"
24
+ "about.html",
25
+ "docs.html",
26
+ "site.css",
27
+ "favicon.ico",
28
+ "picoemu-logo.png",
29
+ "README.md",
30
+ "firmware/*.uf2"
26
31
  ]
27
32
  }
package/picoemu-logo.png ADDED
Binary file