ming_node 3.0.3 → 3.0.5
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- package/README.md +0 -7
- package/output/ming_api_mock/ming_api_mock.js +3251 -0
- package/output/ming_api_mock/mock.bat +21 -0
- package/output/ming_api_mock/mock.sh +15 -0
- package/output/npr/npr.bat +7 -0
- package/output/npr/npr_plugins/MakeModelsim/index.js +157 -0
- package/output/npr/npr_plugins/Modelsim/index.js +72 -0
- package/output/npr/npr_plugins/common/ming_node.js +58 -0
- package/output/npr/npr_plugins/demo/index.js +1 -0
- package/output/npr/npr_plugins/hello/index.js +1 -0
- package/output/npr/npr_plugins/install/index.js +27 -0
- package/output/npr/npr_plugins/list/index.js +20 -0
- package/output/npr/npr_plugins/verilog/Readme.md +1 -0
- package/output/npr/npr_plugins/verilog/breath_led/breath_led.v +99 -0
- package/output/npr/npr_plugins/verilog/breath_led/tb.v +39 -0
- package/output/npr/npr_plugins/verilog/demo/led.v +12 -0
- package/output/npr/npr_plugins/verilog/demo/sims/Makefile +25 -0
- package/output/npr/npr_plugins/verilog/demo/sims/filelist.f +1 -0
- package/output/npr/npr_plugins/verilog/demo/sims/run.do +3 -0
- package/output/npr/npr_plugins/verilog/demo/tb.v +30 -0
- package/output/npr/npr_plugins/verilog/index.js +25 -0
- package/output/npr/npr_plugins/verilog/key_led/key_debounce.v +57 -0
- package/output/npr/npr_plugins/verilog/key_led/tb.v +78 -0
- package/output/npr/npr_plugins/verilog/key_led/toggle_pin.v +35 -0
- package/output/npr/npr_plugins/verilog/led/led.v +12 -0
- package/output/npr/npr_plugins/verilog/led/tb.v +30 -0
- package/output/npr/npr_plugins/verilog/modelsim_tcl/filelist.f +2 -0
- package/output/npr/npr_plugins/verilog/modelsim_tcl/restart.tcl +1 -0
- package/output/npr/npr_plugins/verilog/modelsim_tcl/run.do +3 -0
- package/output/npr/npr_plugins/verilog/modelsim_tcl//346/216/247/345/210/266/345/217/260_Makefile +24 -0
- package/output/npr/npr_plugins/verilog/modelsim_tcl//347/252/227/345/217/243_Makefile +24 -0
- package/output/npr/npr_plugins/verilog/simple_verilog/sims/C_Makefile +27 -0
- package/output/npr/npr_plugins/verilog/simple_verilog/sims/Makefile +25 -0
- package/output/npr/npr_plugins/verilog/simple_verilog/sims/W_Makefile +24 -0
- package/output/npr/npr_plugins/verilog/simple_verilog/sims/filelist.f +1 -0
- package/output/npr/npr_plugins/verilog/simple_verilog/sims/run.do +3 -0
- package/output/npr/npr_plugins/verilog/simple_verilog/tb/led.sv +72 -0
- package/output/npr/npr_plugins/verilog/simple_verilog/tb/tb.sv +54 -0
- package/output/npr/npr_plugins/verilog/smg/HC_FPGA_Demo_Top.v +29 -0
- package/output/npr/npr_plugins/verilog/smg/digital_tube.v +93 -0
- package/output/npr/npr_plugins/verilog/smg/tb.v +56 -0
- package/output/npr/npr_plugins/verilog/uart/calc.js +4 -0
- package/output/npr/npr_plugins/verilog/uart/tb.v +35 -0
- package/output/npr/npr_plugins/verilog/uart/top_UART_RX.v +37 -0
- package/output/npr/npr_plugins/verilog/uart/top_UART_TX.v +41 -0
- package/output/npr/npr_plugins/verilog/uart/uart_rx.v +148 -0
- package/output/npr/npr_plugins/verilog/uart/uart_rx_led.v +23 -0
- package/output/npr/npr_plugins/verilog/uart/uart_tx.v +121 -0
- package/output/npr/npr_plugins/verilog/uart/uart_tx_count.v +72 -0
- package/output/npr/readme.md +7 -0
- package/package.json +1 -1
- package/plugins/Modelsim/Modelsim.js +29 -0
- package/plugins/Modelsim/run.bat +6 -0
- package/plugins/Modelsim/top.do +6 -0
package/README.md
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# ming_node使用文档
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https://www.yuque.com/docs/share/e1f16015-0719-4ffd-9464-a35610389153?# 《ming_node》
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# ming_node使用文档
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https://www.yuque.com/docs/share/e1f16015-0719-4ffd-9464-a35610389153?# 《ming_node》
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https://unpkg.com/minglitlie-test/h5/index.html
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