llvm-runtime-resources-darwin 22.1.8 → 23.1.0

package/include/hvx_hexagon_protos.h

@@ -4577,8 +4577,9 @@
 #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vdd32.sf=vadd(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Wsf_vadd_VbfVbf(Vu, Vv)                                             \
@@ -4636,8 +4637,9 @@
 #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vd32.bf=vcvt(Vu32.sf,Vv32.sf)
-   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Vbf_vcvt_VsfVsf(Vu, Vv)                                             \
@@ -4647,8 +4649,9 @@
 #if __HVX_ARCH__ >= 73
 /* ==========================================================================
    Assembly Syntax:       Qd4=vcmp.gt(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv)                                            \
@@ -4659,9 +4662,9 @@
 #if __HVX_ARCH__ >= 73
 /* ==========================================================================
    Assembly Syntax:       Qx4&=vcmp.gt(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv)                                    \
@@ -4675,9 +4678,9 @@
 #if __HVX_ARCH__ >= 73
 /* ==========================================================================
    Assembly Syntax:       Qx4|=vcmp.gt(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv)                                     \
@@ -4691,9 +4694,9 @@
 #if __HVX_ARCH__ >= 73
 /* ==========================================================================
    Assembly Syntax:       Qx4^=vcmp.gt(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv)                                   \
@@ -4707,8 +4710,9 @@
 #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vd32.bf=vmax(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX_LATE Execution Slots: SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Vbf_vmax_VbfVbf(Vu, Vv)                                             \
@@ -4718,8 +4722,9 @@
 #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vd32.bf=vmin(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX_LATE Execution Slots: SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_LATE
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Vbf_vmin_VbfVbf(Vu, Vv)                                             \
@@ -4729,8 +4734,9 @@
 #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vdd32.sf=vmpy(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Wsf_vmpy_VbfVbf(Vu, Vv)                                             \
@@ -4740,9 +4746,9 @@
 #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair
-   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
-   Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv)                                  \
@@ -4752,8 +4758,9 @@
 #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vdd32.sf=vsub(Vu32.bf,Vv32.bf)
-   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Wsf_vsub_VbfVbf(Vu, Vv)                                             \
@@ -4775,9 +4782,9 @@
 #if __HVX_ARCH__ >= 79
 /* ==========================================================================
    Assembly Syntax:       Vx32|=vgetqfext(Vu32.x,Rt32)
-   C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx,
-   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
-   SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt)                                       \
@@ -4810,8 +4817,9 @@
 #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vdd32.hf=vadd(Vu32.f8,Vv32.f8)
-   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Whf_vadd_VV(Vu, Vv)                                                 \
@@ -4821,8 +4829,9 @@
 #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vd32.b=vcvt2(Vu32.hf,Vv32.hf)
-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Vb_vcvt2_VhfVhf(Vu, Vv)                                             \
@@ -4856,8 +4865,9 @@
 #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vd32.ub=vcvt2(Vu32.hf,Vv32.hf)
-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Vub_vcvt2_VhfVhf(Vu, Vv)                                            \
@@ -4867,8 +4877,9 @@
 #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vd32.f8=vcvt(Vu32.hf,Vv32.hf)
-   C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector
-   Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_V_vcvt_VhfVhf(Vu, Vv)                                               \
@@ -4926,8 +4937,9 @@
 #if __HVX_ARCH__ >= 79
 /* ==========================================================================
    Assembly Syntax:       Vd32=vmerge(Vu32.x,Vv32.w)
-   C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector
-   Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_V_vmerge_VVw(Vu, Vv)                                                \
@@ -4937,8 +4949,9 @@
 #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vdd32.hf=vmpy(Vu32.f8,Vv32.f8)
-   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Whf_vmpy_VV(Vu, Vv)                                                 \
@@ -4948,9 +4961,9 @@
 #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8)
-   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair
-   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
-   Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv)                                      \
@@ -4960,8 +4973,9 @@
 #if __HVX_ARCH__ >= 79
 /* ==========================================================================
    Assembly Syntax:       Vd32.qf16=vmpy(Vu32.hf,Rt32.hf)
-   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32
-   Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt)                                           \
@@ -4971,8 +4985,9 @@
 #if __HVX_ARCH__ >= 79
 /* ==========================================================================
    Assembly Syntax:       Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf)
-   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu,
-   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt)                                         \
@@ -4982,8 +4997,9 @@
 #if __HVX_ARCH__ >= 79
 /* ==========================================================================
    Assembly Syntax:       Vd32.qf32=vmpy(Vu32.sf,Rt32.sf)
-   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32
-   Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32 Rt)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt)                                           \
@@ -4993,8 +5009,9 @@
 #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
 /* ==========================================================================
    Assembly Syntax:       Vdd32.hf=vsub(Vu32.f8,Vv32.f8)
-   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VX_DV
+   Execution Slots:       SLOT23
    ========================================================================== */
 
 #define Q6_Whf_vsub_VV(Vu, Vv)                                                 \
@@ -5052,8 +5069,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Vd32=valign4(Vu32,Vv32,Rt8)
-   C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector
-   Vv, Word32 Rt) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_V_valign4_VVR(Vu, Vv, Rt)                                           \
@@ -5159,8 +5177,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Qd4=vcmp.eq(Vu32.hf,Vv32.hf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv)                                            \
@@ -5171,9 +5190,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Qx4&=vcmp.eq(Vu32.hf,Vv32.hf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv)                                    \
@@ -5187,9 +5206,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Qx4|=vcmp.eq(Vu32.hf,Vv32.hf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv)                                     \
@@ -5203,9 +5222,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Qx4^=vcmp.eq(Vu32.hf,Vv32.hf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv)                                   \
@@ -5219,8 +5238,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Qd4=vcmp.eq(Vu32.sf,Vv32.sf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv)                                            \
@@ -5231,9 +5251,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Qx4&=vcmp.eq(Vu32.sf,Vv32.sf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv)                                    \
@@ -5247,9 +5267,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Qx4|=vcmp.eq(Vu32.sf,Vv32.sf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv)                                     \
@@ -5263,9 +5283,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Qx4^=vcmp.eq(Vu32.sf,Vv32.sf)
-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred
-   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
-   Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VA
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv)                                   \
@@ -5375,8 +5395,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Vd32.qf16=vsub(Vu32.hf,Vv32.qf16)
-   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv)                                         \
@@ -5386,8 +5407,9 @@
 #if __HVX_ARCH__ >= 81
 /* ==========================================================================
    Assembly Syntax:       Vd32.qf32=vsub(Vu32.sf,Vv32.qf32)
-   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu,
-   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, HVX_Vector Vv)
+   Instruction Type:      CVI_VS
+   Execution Slots:       SLOT0123
    ========================================================================== */
 
 #define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv)                                         \

package/include/immintrin.h

@@ -58,6 +58,10 @@
 
 #include <avx512bitalgintrin.h>
 
+#include <avx512bmmintrin.h>
+
+#include <avx512bmmvlintrin.h>
+
 #include <avx512cdintrin.h>
 
 #include <avx512vpopcntdqintrin.h>
@@ -479,8 +483,6 @@ _storebe_i64(void * __P, long long __D) {
 
 #include <amxavx512intrin.h>
 
-#include <amxtf32intrin.h>
-
 #include <avx512vp2intersectintrin.h>
 
 #include <avx512vlvp2intersectintrin.h>

package/include/intrin.h

@@ -44,8 +44,10 @@
 
 #if __x86_64__
 #define __LPTRINT_TYPE__ __int64
+#define __IPTRINT_TYPE__ __int64
 #else
 #define __LPTRINT_TYPE__ long
+#define __IPTRINT_TYPE__ int
 #endif
 
 #ifdef __cplusplus
@@ -95,12 +97,12 @@ void __outdword(unsigned short, unsigned long);
 void __outdwordstring(unsigned short, unsigned long *, unsigned long);
 void __outword(unsigned short, unsigned short);
 void __outwordstring(unsigned short, unsigned short *, unsigned long);
-unsigned long __readcr0(void);
-unsigned long __readcr2(void);
+unsigned __LPTRINT_TYPE__ __readcr0(void);
+unsigned __LPTRINT_TYPE__ __readcr2(void);
 unsigned __LPTRINT_TYPE__ __readcr3(void);
 unsigned __LPTRINT_TYPE__ __readcr4(void);
-unsigned __int64 __readcr8(void);
-unsigned int __readdr(unsigned int);
+unsigned __LPTRINT_TYPE__ __readcr8(void);
+unsigned __IPTRINT_TYPE__ __readdr(unsigned int);
 #ifdef __i386__
 unsigned char __readfsbyte(unsigned long);
 unsigned short __readfsword(unsigned long);
@@ -126,11 +128,12 @@ unsigned __int64 __ull_rshift(unsigned __int64, int);
 void __vmx_off(void);
 void __vmx_vmptrst(unsigned __int64 *);
 void __wbinvd(void);
-void __writecr0(unsigned int);
-void __writecr3(unsigned __INTPTR_TYPE__);
-void __writecr4(unsigned __INTPTR_TYPE__);
-void __writecr8(unsigned __int64);
-void __writedr(unsigned int, unsigned int);
+void __writecr0(unsigned __IPTRINT_TYPE__);
+void __writecr2(unsigned __IPTRINT_TYPE__);
+void __writecr3(unsigned __IPTRINT_TYPE__);
+void __writecr4(unsigned __IPTRINT_TYPE__);
+void __writecr8(unsigned __IPTRINT_TYPE__);
+void __writedr(unsigned int, unsigned __IPTRINT_TYPE__);
 void __writefsbyte(unsigned long, unsigned char);
 void __writefsdword(unsigned long, unsigned long);
 void __writefsqword(unsigned long, unsigned __int64);
@@ -374,6 +377,9 @@ static __inline__ void __DEFAULT_FN_ATTRS __nop(void) {
 \*----------------------------------------------------------------------------*/
 #if defined(__aarch64__) || defined(__arm64ec__)
 unsigned __int64 __getReg(int);
+double __getRegFp(int _Reg);
+void __setReg(int, unsigned __int64);
+void __setRegFp(int, double);
 unsigned char _interlockedbittestandreset_acq(long volatile *, long);
 unsigned char _interlockedbittestandreset_nf(long volatile *, long);
 unsigned char _interlockedbittestandreset_rel(long volatile *, long);
@@ -438,10 +444,13 @@ unsigned int _CountLeadingSigns(long);
 unsigned int _CountLeadingSigns64(__int64);
 unsigned int _CountOneBits(unsigned long);
 unsigned int _CountOneBits64(unsigned __int64);
+unsigned int _CountTrailingZeros(unsigned long);
+unsigned int _CountTrailingZeros64(unsigned __int64);
 
 unsigned int __hlt(unsigned int, ...);
 
 void __cdecl __prefetch(const void *);
+void __cdecl __prefetch2(const void *, unsigned char);
 
 #endif
 
@@ -474,7 +483,7 @@ static __inline__ unsigned __LPTRINT_TYPE__ __DEFAULT_FN_ATTRS __readcr3(void) {
 }
 
 static __inline__ void __DEFAULT_FN_ATTRS
-__writecr3(unsigned __INTPTR_TYPE__ __cr3_val) {
+__writecr3(unsigned __IPTRINT_TYPE__ __cr3_val) {
   __asm__ ("mov {%0, %%cr3|cr3, %0}" : : "r"(__cr3_val) : "memory");
 }
 #endif
@@ -484,6 +493,7 @@ __writecr3(unsigned __INTPTR_TYPE__ __cr3_val) {
 #endif
 
 #undef __LPTRINT_TYPE__
+#undef __IPTRINT_TYPE__
 
 #undef __DEFAULT_FN_ATTRS
 

package/include/larchintrin.h

@@ -120,10 +120,12 @@ extern __inline int
 
 #define __ibar(/*ui15*/ _1) __builtin_loongarch_ibar((_1))
 
+#ifdef __loongarch_hard_float
 #define __movfcsr2gr(/*ui5*/ _1) __builtin_loongarch_movfcsr2gr((_1));
 
 #define __movgr2fcsr(/*ui5*/ _1, _2)                                           \
   __builtin_loongarch_movgr2fcsr((_1), (unsigned int)_2);
+#endif
 
 #define __syscall(/*ui15*/ _1) __builtin_loongarch_syscall((_1))
 

package/include/llvm_libc_wrappers/ctype.h

@@ -9,13 +9,14 @@
 #ifndef __CLANG_LLVM_LIBC_WRAPPERS_CTYPE_H__
 #define __CLANG_LLVM_LIBC_WRAPPERS_CTYPE_H__
 
-#if !defined(_OPENMP) && !defined(__HIP__) && !defined(__CUDA__)
+#if !defined(_OPENMP) && !defined(__HIP__) && !defined(__CUDA__) &&            \
+    !defined(__SPIRV__)
 #error "This file is for GPU offloading compilation only"
 #endif
 
 #include_next <ctype.h>
 
-#if defined(__HIP__) || defined(__CUDA__)
+#if defined(__HIP__) || defined(__CUDA__) || defined(__SPIRV__)
 #define __LIBC_ATTRS __attribute__((device))
 #else
 #define __LIBC_ATTRS

package/include/llvm_libc_wrappers/string.h

@@ -9,13 +9,14 @@
 #ifndef __CLANG_LLVM_LIBC_WRAPPERS_STRING_H__
 #define __CLANG_LLVM_LIBC_WRAPPERS_STRING_H__
 
-#if !defined(_OPENMP) && !defined(__HIP__) && !defined(__CUDA__)
+#if !defined(_OPENMP) && !defined(__HIP__) && !defined(__CUDA__) &&            \
+    !defined(__SPIRV__)
 #error "This file is for GPU offloading compilation only"
 #endif
 
 #include_next <string.h>
 
-#if defined(__HIP__) || defined(__CUDA__)
+#if defined(__HIP__) || defined(__CUDA__) || defined(__SPIRV__)
 #define __LIBC_ATTRS __attribute__((device))
 #else
 #define __LIBC_ATTRS

package/include/module.modulemap

@@ -21,10 +21,19 @@ module _Builtin_intrinsics [system] [extern_c] {
       export *
     }
 
+    explicit module bf16 {
+      header "arm_bf16.h"
+      export *
+    }
+
+    explicit module fp16 {
+      header "arm_fp16.h"
+      export *
+    }
+
     explicit module neon {
       requires neon
       header "arm_neon.h"
-      header "arm_fp16.h"
       export *
     }
 
@@ -41,6 +50,12 @@ module _Builtin_intrinsics [system] [extern_c] {
 
     header "arm64intr.h"
     export *
+
+    explicit module neon {
+      requires neon
+      header "arm64_neon.h"
+      export *
+    }
   }
 
   explicit module intel {