llvm-runtime-resources-darwin 0.0.0 → 23.1.0

package/include/sanitizer/tsan_interface_atomic.h

@@ -0,0 +1,223 @@
+//===-- tsan_interface_atomic.h ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is a part of ThreadSanitizer (TSan), a race detector.
+//
+// Public interface header for TSan atomics.
+//===----------------------------------------------------------------------===//
+#ifndef TSAN_INTERFACE_ATOMIC_H
+#define TSAN_INTERFACE_ATOMIC_H
+
+#include <sanitizer/common_interface_defs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char __tsan_atomic8;
+typedef short __tsan_atomic16;
+typedef int __tsan_atomic32;
+typedef long __tsan_atomic64;
+#if defined(__SIZEOF_INT128__) ||                                              \
+    (__clang_major__ * 100 + __clang_minor__ >= 302)
+__extension__ typedef __int128 __tsan_atomic128;
+#define __TSAN_HAS_INT128 1
+#else
+#define __TSAN_HAS_INT128 0
+#endif
+
+// Part of ABI, do not change.
+// https://github.com/llvm/llvm-project/blob/main/libcxx/include/atomic
+typedef enum {
+  __tsan_memory_order_relaxed,
+  __tsan_memory_order_consume,
+  __tsan_memory_order_acquire,
+  __tsan_memory_order_release,
+  __tsan_memory_order_acq_rel,
+  __tsan_memory_order_seq_cst
+} __tsan_memory_order;
+
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_load(const volatile __tsan_atomic8 *a, int mo);
+__tsan_atomic16 SANITIZER_CDECL
+__tsan_atomic16_load(const volatile __tsan_atomic16 *a, int mo);
+__tsan_atomic32 SANITIZER_CDECL
+__tsan_atomic32_load(const volatile __tsan_atomic32 *a, int mo);
+__tsan_atomic64 SANITIZER_CDECL
+__tsan_atomic64_load(const volatile __tsan_atomic64 *a, int mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL
+__tsan_atomic128_load(const volatile __tsan_atomic128 *a, int mo);
+#endif
+
+void SANITIZER_CDECL __tsan_atomic8_store(volatile __tsan_atomic8 *a,
+                                          __tsan_atomic8 v, int mo);
+void SANITIZER_CDECL __tsan_atomic16_store(volatile __tsan_atomic16 *a,
+                                           __tsan_atomic16 v, int mo);
+void SANITIZER_CDECL __tsan_atomic32_store(volatile __tsan_atomic32 *a,
+                                           __tsan_atomic32 v, int mo);
+void SANITIZER_CDECL __tsan_atomic64_store(volatile __tsan_atomic64 *a,
+                                           __tsan_atomic64 v, int mo);
+#if __TSAN_HAS_INT128
+void SANITIZER_CDECL __tsan_atomic128_store(volatile __tsan_atomic128 *a,
+                                            __tsan_atomic128 v, int mo);
+#endif
+
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_exchange(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_exchange(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_exchange(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
+__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_exchange(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_exchange(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
+#endif
+
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_fetch_add(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_fetch_add(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_fetch_add(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
+__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_fetch_add(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_fetch_add(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
+#endif
+
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_fetch_sub(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_fetch_sub(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_fetch_sub(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
+__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_fetch_sub(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_fetch_sub(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
+#endif
+
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_fetch_and(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_fetch_and(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_fetch_and(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
+__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_fetch_and(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_fetch_and(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
+#endif
+
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_fetch_or(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_fetch_or(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_fetch_or(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
+__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_fetch_or(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_fetch_or(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
+#endif
+
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_fetch_xor(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_fetch_xor(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_fetch_xor(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
+__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_fetch_xor(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_fetch_xor(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
+#endif
+
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_fetch_nand(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_fetch_nand(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_fetch_nand(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
+__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_fetch_nand(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_fetch_nand(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
+#endif
+
+int SANITIZER_CDECL __tsan_atomic8_compare_exchange_weak(
+    volatile __tsan_atomic8 *a, __tsan_atomic8 *c, __tsan_atomic8 v, int mo,
+    int fail_mo);
+int SANITIZER_CDECL __tsan_atomic16_compare_exchange_weak(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 *c, __tsan_atomic16 v, int mo,
+    int fail_mo);
+int SANITIZER_CDECL __tsan_atomic32_compare_exchange_weak(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 *c, __tsan_atomic32 v, int mo,
+    int fail_mo);
+int SANITIZER_CDECL __tsan_atomic64_compare_exchange_weak(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 *c, __tsan_atomic64 v, int mo,
+    int fail_mo);
+#if __TSAN_HAS_INT128
+int SANITIZER_CDECL __tsan_atomic128_compare_exchange_weak(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 *c, __tsan_atomic128 v,
+    int mo, int fail_mo);
+#endif
+
+int SANITIZER_CDECL __tsan_atomic8_compare_exchange_strong(
+    volatile __tsan_atomic8 *a, __tsan_atomic8 *c, __tsan_atomic8 v, int mo,
+    int fail_mo);
+int SANITIZER_CDECL __tsan_atomic16_compare_exchange_strong(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 *c, __tsan_atomic16 v, int mo,
+    int fail_mo);
+int SANITIZER_CDECL __tsan_atomic32_compare_exchange_strong(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 *c, __tsan_atomic32 v, int mo,
+    int fail_mo);
+int SANITIZER_CDECL __tsan_atomic64_compare_exchange_strong(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 *c, __tsan_atomic64 v, int mo,
+    int fail_mo);
+#if __TSAN_HAS_INT128
+int SANITIZER_CDECL __tsan_atomic128_compare_exchange_strong(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 *c, __tsan_atomic128 v,
+    int mo, int fail_mo);
+#endif
+
+__tsan_atomic8 SANITIZER_CDECL __tsan_atomic8_compare_exchange_val(
+    volatile __tsan_atomic8 *a, __tsan_atomic8 c, __tsan_atomic8 v, int mo,
+    int fail_mo);
+__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_compare_exchange_val(
+    volatile __tsan_atomic16 *a, __tsan_atomic16 c, __tsan_atomic16 v, int mo,
+    int fail_mo);
+__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_compare_exchange_val(
+    volatile __tsan_atomic32 *a, __tsan_atomic32 c, __tsan_atomic32 v, int mo,
+    int fail_mo);
+__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_compare_exchange_val(
+    volatile __tsan_atomic64 *a, __tsan_atomic64 c, __tsan_atomic64 v, int mo,
+    int fail_mo);
+#if __TSAN_HAS_INT128
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_compare_exchange_val(
+    volatile __tsan_atomic128 *a, __tsan_atomic128 c, __tsan_atomic128 v,
+    int mo, int fail_mo);
+#endif
+
+void SANITIZER_CDECL __tsan_atomic_thread_fence(int mo);
+void SANITIZER_CDECL __tsan_atomic_signal_fence(int mo);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // TSAN_INTERFACE_ATOMIC_H

package/include/sanitizer/tysan_interface.h

@@ -0,0 +1,36 @@
+//===-- tysan_interface.h ---------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is a part of TypeSanitizer.
+//
+// Public interface header for TySan.
+//===----------------------------------------------------------------------===//
+#ifndef SANITIZER_TYSAN_INTERFACE_H
+#define SANITIZER_TYSAN_INTERFACE_H
+
+#include <sanitizer/common_interface_defs.h>
+#include <stdlib.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// Marks a memory region (<c>[addr, addr+size)</c>) as not yet having a type.
+///
+/// TySan will take the next read/write to the memory region to be the correct
+/// type for the memory, and use that for its checks from then on.
+///
+/// \param addr Start of memory region.
+/// \param size Size of memory region.
+void SANITIZER_CDECL __tysan_set_type_unknown(void const *addr, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

package/include/sanitizer/ubsan_interface.h

@@ -0,0 +1,64 @@
+//===-- sanitizer/ubsan_interface.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is a part of UBSanitizer (UBSan).
+//
+// Public interface header.
+//===----------------------------------------------------------------------===//
+#ifndef SANITIZER_UBSAN_INTERFACE_H
+#define SANITIZER_UBSAN_INTERFACE_H
+
+#include <sanitizer/common_interface_defs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// User-provided default option settings.
+///
+/// You can provide your own implementation of this function to return a string
+/// containing UBSan runtime options (for example,
+/// <c>verbosity=1:halt_on_error=0</c>).
+///
+/// \returns Default options string.
+const char *SANITIZER_CDECL __ubsan_default_options(void);
+
+/// User-provided default suppressions.
+///
+/// You can provide your own implementation of this function to return a string
+/// containing UBSan suppressions.
+///
+/// \returns Default suppressions string.
+const char *SANITIZER_CDECL __ubsan_default_suppressions(void);
+
+/// Set up an interval timer and install a SIGPROF signal handler that crashes
+/// the program if it is stuck in a trap loop generated by -fsanitize-trap-loop.
+///
+/// This function is only intended to be called by single-threaded programs.
+/// Because interval timers are delivered to an arbitrary thread in the process,
+/// it is possible that a thread in a trap loop will never have the signal
+/// delivered to it. For multi-threaded programs, it is recommended to call
+/// OS-specific APIs such as timer_create(CLOCK_THREAD_CPUTIME_ID) on Linux to
+/// install a timer on each thread.
+///
+/// Programs with their own signal handlers can call __ubsan_is_trap_loop from
+/// the signal handler to implement trap loop handling.
+///
+/// This function is currently only supported on Linux/x86.
+void __ubsan_install_trap_loop_detection(void);
+
+/// Returns whether uc (actually a pointer to ucontext_t) indicates that the
+/// thread is stuck in a trap loop generated by -fsanitize-trap-loop.
+///
+/// This function is currently only supported on Linux/x86.
+int __ubsan_is_trap_loop(void *uc);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // SANITIZER_UBSAN_INTERFACE_H

package/include/serializeintrin.h

@@ -0,0 +1,30 @@
+/*===--------------- serializeintrin.h - serialize intrinsics --------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use <serializeintrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef __SERIALIZEINTRIN_H
+#define __SERIALIZEINTRIN_H
+
+/// Serialize instruction fetch and execution.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the <c> SERIALIZE </c> instruction.
+///
+static __inline__ void
+__attribute__((__always_inline__, __nodebug__, __target__("serialize")))
+_serialize (void)
+{
+  __builtin_ia32_serialize ();
+}
+
+#endif /* __SERIALIZEINTRIN_H */

package/include/sgxintrin.h

@@ -0,0 +1,60 @@
+/*===---- sgxintrin.h - X86 SGX intrinsics configuration -------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#if !defined __X86INTRIN_H && !defined __IMMINTRIN_H
+#error "Never use <sgxintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef __SGXINTRIN_H
+#define __SGXINTRIN_H
+
+#if __has_extension(gnu_asm)
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __nodebug__,  __target__("sgx")))
+
+static __inline unsigned int __DEFAULT_FN_ATTRS
+_enclu_u32(unsigned int __leaf, __SIZE_TYPE__ __d[])
+{
+  unsigned int __result;
+  __asm__ ("enclu"
+           : "=a" (__result), "=b" (__d[0]), "=c" (__d[1]), "=d" (__d[2])
+           : "a" (__leaf), "b" (__d[0]), "c" (__d[1]), "d" (__d[2])
+           : "cc");
+  return __result;
+}
+
+static __inline unsigned int __DEFAULT_FN_ATTRS
+_encls_u32(unsigned int __leaf, __SIZE_TYPE__ __d[])
+{
+  unsigned int __result;
+  __asm__ ("encls"
+           : "=a" (__result), "=b" (__d[0]), "=c" (__d[1]), "=d" (__d[2])
+           : "a" (__leaf), "b" (__d[0]), "c" (__d[1]), "d" (__d[2])
+           : "cc");
+  return __result;
+}
+
+static __inline unsigned int __DEFAULT_FN_ATTRS
+_enclv_u32(unsigned int __leaf, __SIZE_TYPE__ __d[])
+{
+  unsigned int __result;
+  __asm__ ("enclv"
+           : "=a" (__result), "=b" (__d[0]), "=c" (__d[1]), "=d" (__d[2])
+           : "a" (__leaf), "b" (__d[0]), "c" (__d[1]), "d" (__d[2])
+           : "cc");
+  return __result;
+}
+
+#undef __DEFAULT_FN_ATTRS
+
+#endif /* __has_extension(gnu_asm) */
+
+#endif

package/include/sha512intrin.h

@@ -0,0 +1,200 @@
+/*===--------------- sha512intrin.h - SHA512 intrinsics -----------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use <sha512intrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifndef __SHA512INTRIN_H
+#define __SHA512INTRIN_H
+
+#define __DEFAULT_FN_ATTRS256                                                  \
+  __attribute__((__always_inline__, __nodebug__, __target__("sha512"),         \
+                 __min_vector_width__(256)))
+
+/// This intrinisc is one of the two SHA512 message scheduling instructions.
+///    The intrinsic performs an intermediate calculation for the next four
+///    SHA512 message qwords. The calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m256i _mm256_sha512msg1_epi64(__m256i __A, __m128i __B)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSHA512MSG1 instruction.
+///
+/// \param __A
+///    A 256-bit vector of [4 x long long].
+/// \param __B
+///    A 128-bit vector of [2 x long long].
+/// \returns
+///    A 256-bit vector of [4 x long long].
+///
+/// \code{.operation}
+/// DEFINE ROR64(qword, n) {
+/// 	count := n % 64
+/// 	dest := (qword >> count) | (qword << (64 - count))
+/// 	RETURN dest
+/// }
+/// DEFINE SHR64(qword, n) {
+/// 	RETURN qword >> n
+/// }
+/// DEFINE s0(qword):
+/// 	RETURN ROR64(qword,1) ^ ROR64(qword, 8) ^ SHR64(qword, 7)
+/// }
+/// W[4] := __B.qword[0]
+/// W[3] := __A.qword[3]
+/// W[2] := __A.qword[2]
+/// W[1] := __A.qword[1]
+/// W[0] := __A.qword[0]
+/// dst.qword[3] := W[3] + s0(W[4])
+/// dst.qword[2] := W[2] + s0(W[3])
+/// dst.qword[1] := W[1] + s0(W[2])
+/// dst.qword[0] := W[0] + s0(W[1])
+/// dst[MAX:256] := 0
+/// \endcode
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_sha512msg1_epi64(__m256i __A, __m128i __B) {
+  return (__m256i)__builtin_ia32_vsha512msg1((__v4du)__A, (__v2du)__B);
+}
+
+/// This intrinisc is one of the two SHA512 message scheduling instructions.
+///    The intrinsic performs the final calculation for the next four SHA512
+///    message qwords. The calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m256i _mm256_sha512msg2_epi64(__m256i __A, __m256i __B)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSHA512MSG2 instruction.
+///
+/// \param __A
+///    A 256-bit vector of [4 x long long].
+/// \param __B
+///    A 256-bit vector of [4 x long long].
+/// \returns
+///    A 256-bit vector of [4 x long long].
+///
+/// \code{.operation}
+/// DEFINE ROR64(qword, n) {
+/// 	count := n % 64
+/// 	dest := (qword >> count) | (qword << (64 - count))
+/// 	RETURN dest
+/// }
+/// DEFINE SHR64(qword, n) {
+/// 	RETURN qword >> n
+/// }
+/// DEFINE s1(qword) {
+/// 	RETURN ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)
+/// }
+/// W[14] := __B.qword[2]
+/// W[15] := __B.qword[3]
+/// W[16] := __A.qword[0] + s1(W[14])
+/// W[17] := __A.qword[1] + s1(W[15])
+/// W[18] := __A.qword[2] + s1(W[16])
+/// W[19] := __A.qword[3] + s1(W[17])
+/// dst.qword[3] := W[19]
+/// dst.qword[2] := W[18]
+/// dst.qword[1] := W[17]
+/// dst.qword[0] := W[16]
+/// dst[MAX:256] := 0
+/// \endcode
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_sha512msg2_epi64(__m256i __A, __m256i __B) {
+  return (__m256i)__builtin_ia32_vsha512msg2((__v4du)__A, (__v4du)__B);
+}
+
+/// This intrinisc performs two rounds of SHA512 operation using initial SHA512
+///    state (C,D,G,H) from \a __A, an initial SHA512 state (A,B,E,F) from
+///    \a __A, and a pre-computed sum of the next two round message qwords and
+///    the corresponding round constants from \a __C (only the two lower qwords
+///    of the third operand). The updated SHA512 state (A,B,E,F) is written to
+///    \a __A, and \a __A can be used as the updated state (C,D,G,H) in later
+///    rounds.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m256i _mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSHA512RNDS2 instruction.
+///
+/// \param __A
+///    A 256-bit vector of [4 x long long].
+/// \param __B
+///    A 256-bit vector of [4 x long long].
+/// \param __C
+///    A 128-bit vector of [2 x long long].
+/// \returns
+///    A 256-bit vector of [4 x long long].
+///
+/// \code{.operation}
+/// DEFINE ROR64(qword, n) {
+/// 	count := n % 64
+/// 	dest := (qword >> count) | (qword << (64 - count))
+/// 	RETURN dest
+/// }
+/// DEFINE SHR64(qword, n) {
+/// 	RETURN qword >> n
+/// }
+/// DEFINE cap_sigma0(qword) {
+/// 	RETURN ROR64(qword,28) ^ ROR64(qword, 34) ^ ROR64(qword, 39)
+/// }
+/// DEFINE cap_sigma1(qword) {
+/// 	RETURN ROR64(qword,14) ^ ROR64(qword, 18) ^ ROR64(qword, 41)
+/// }
+/// DEFINE MAJ(a,b,c) {
+/// 	RETURN (a & b) ^ (a & c) ^ (b & c)
+/// }
+/// DEFINE CH(e,f,g) {
+/// 	RETURN (e & f) ^ (g & ~e)
+/// }
+/// A[0] := __B.qword[3]
+/// B[0] := __B.qword[2]
+/// C[0] := __C.qword[3]
+/// D[0] := __C.qword[2]
+/// E[0] := __B.qword[1]
+/// F[0] := __B.qword[0]
+/// G[0] := __C.qword[1]
+/// H[0] := __C.qword[0]
+/// WK[0]:= __A.qword[0]
+/// WK[1]:= __A.qword[1]
+/// FOR i := 0 to 1:
+/// 	A[i+1] := CH(E[i], F[i], G[i]) +
+/// 	cap_sigma1(E[i]) + WK[i] + H[i] +
+/// 	MAJ(A[i], B[i], C[i]) +
+/// 	cap_sigma0(A[i])
+/// 	B[i+1] := A[i]
+/// 	C[i+1] := B[i]
+/// 	D[i+1] := C[i]
+/// 	E[i+1] := CH(E[i], F[i], G[i]) +
+/// 	cap_sigma1(E[i]) + WK[i] + H[i] + D[i]
+/// 	F[i+1] := E[i]
+/// 	G[i+1] := F[i]
+/// 	H[i+1] := G[i]
+/// ENDFOR
+/// dst.qword[3] := A[2]
+/// dst.qword[2] := B[2]
+/// dst.qword[1] := E[2]
+/// dst.qword[0] := F[2]
+/// dst[MAX:256] := 0
+/// \endcode
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C) {
+  return (__m256i)__builtin_ia32_vsha512rnds2((__v4du)__A, (__v4du)__B,
+                                              (__v2du)__C);
+}
+
+#undef __DEFAULT_FN_ATTRS256
+
+#endif // __SHA512INTRIN_H