esp32tool 1.3.6 → 1.3.8

package/dist/console.js

@@ -149,14 +149,25 @@ export class ESP32ToolConsole {
     }
     async _connect(abortSignal) {
         console.log("Starting console read loop");
-        // Check if port.readable is available
-        if (!this.port.readable) {
-            this.console.addLine("");
-            this.console.addLine("");
-            this.console.addLine(`Terminal disconnected: Port readable stream not available`);
-            console.error("Port readable stream not available - port may need to be reopened at correct baudrate");
-            return;
+        // Wait for readable stream to be available with timeout
+        const maxWaitTime = 3000; // 3 seconds
+        const startTime = Date.now();
+        while (!this.port.readable) {
+            const elapsed = Date.now() - startTime;
+            if (elapsed > maxWaitTime) {
+                this.console.addLine("");
+                this.console.addLine("");
+                this.console.addLine(`Terminal disconnected: Port readable stream not available after ${maxWaitTime}ms`);
+                this.console.addLine(`This can happen if:`);
+                this.console.addLine(`1. Port was just opened and streams are not ready yet`);
+                this.console.addLine(`2. Device was reset and port needs to be reopened`);
+                this.console.addLine(`3. USB device re-enumerated after reset`);
+                console.error("Port readable stream not available - port may need to be reopened at correct baudrate");
+                return;
+            }
+            await new Promise((resolve) => setTimeout(resolve, 50));
         }
+        console.log("Port readable stream is ready - starting console");
         try {
             await this.port
                 .readable.pipeThrough(new TextDecoderStream(), {

package/dist/const.d.ts

@@ -56,8 +56,10 @@ export declare const ESP32_SPI_MISO_DLEN_OFFS = 44;
 export declare const ESP32_SPI_W0_OFFS = 128;
 export declare const ESP32_UART_DATE_REG_ADDR = 1610612856;
 export declare const ESP32_BOOTLOADER_FLASH_OFFSET = 4096;
+export declare const ESP32_APB_CTL_DATE_ADDR: number;
 export declare const ESP32S2_SPI_REG_BASE = 1061167104;
 export declare const ESP32S2_BASEFUSEADDR = 1061265408;
+export declare const ESP32S2_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32S2_MACFUSEADDR = 1061265476;
 export declare const ESP32S2_SPI_USR_OFFS = 24;
 export declare const ESP32S2_SPI_USR1_OFFS = 28;
@@ -81,6 +83,7 @@ export declare const ESP32S2_UARTDEV_BUF_NO = 1073741076;
 export declare const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2;
 export declare const ESP32S3_SPI_REG_BASE = 1610620928;
 export declare const ESP32S3_BASEFUSEADDR = 1610641408;
+export declare const ESP32S3_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32S3_MACFUSEADDR: number;
 export declare const ESP32S3_SPI_USR_OFFS = 24;
 export declare const ESP32S3_SPI_USR1_OFFS = 28;
@@ -105,6 +108,7 @@ export declare const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3;
 export declare const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4;
 export declare const ESP32C2_SPI_REG_BASE = 1610620928;
 export declare const ESP32C2_BASEFUSEADDR = 1610647552;
+export declare const ESP32C2_EFUSE_BLOCK2_ADDR: number;
 export declare const ESP32C2_MACFUSEADDR: number;
 export declare const ESP32C2_SPI_USR_OFFS = 24;
 export declare const ESP32C2_SPI_USR1_OFFS = 28;
@@ -146,6 +150,7 @@ export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 1610647632;
 export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 1610647640;
 export declare const ESP32C5_SPI_REG_BASE = 1610625024;
 export declare const ESP32C5_BASEFUSEADDR = 1611352064;
+export declare const ESP32C5_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32C5_MACFUSEADDR: number;
 export declare const ESP32C5_SPI_USR_OFFS = 24;
 export declare const ESP32C5_SPI_USR1_OFFS = 28;
@@ -154,11 +159,16 @@ export declare const ESP32C5_SPI_MOSI_DLEN_OFFS = 36;
 export declare const ESP32C5_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32C5_SPI_W0_OFFS = 88;
 export declare const ESP32C5_UART_DATE_REG_ADDR = 1610612860;
+export declare const ESP32C5_UART_CLKDIV_REG = 1610612756;
 export declare const ESP32C5_BOOTLOADER_FLASH_OFFSET = 8192;
+export declare const ESP32C5_PCR_SYSCLK_CONF_REG = 1611227408;
+export declare const ESP32C5_PCR_SYSCLK_XTAL_FREQ_V: number;
+export declare const ESP32C5_PCR_SYSCLK_XTAL_FREQ_S = 24;
 export declare const ESP32C5_UARTDEV_BUF_NO = 1082520852;
 export declare const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
 export declare const ESP32C6_SPI_REG_BASE = 1610625024;
 export declare const ESP32C6_BASEFUSEADDR = 1611335680;
+export declare const ESP32C6_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32C6_MACFUSEADDR: number;
 export declare const ESP32C6_SPI_USR_OFFS = 24;
 export declare const ESP32C6_SPI_USR1_OFFS = 28;
@@ -186,6 +196,7 @@ export declare const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN: number;
 export declare const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG: number;
 export declare const ESP32C61_SPI_REG_BASE = 1610625024;
 export declare const ESP32C61_BASEFUSEADDR = 1611352064;
+export declare const ESP32C61_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32C61_MACFUSEADDR: number;
 export declare const ESP32C61_SPI_USR_OFFS = 24;
 export declare const ESP32C61_SPI_USR1_OFFS = 28;
@@ -195,8 +206,13 @@ export declare const ESP32C61_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32C61_SPI_W0_OFFS = 88;
 export declare const ESP32C61_UART_DATE_REG_ADDR = 1610612860;
 export declare const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0;
+export declare const ESP32C61_UARTDEV_BUF_NO_REV_LE2 = 1082455532;
+export declare const ESP32C61_UARTDEV_BUF_NO_REV_GT2 = 1082455524;
+export declare const ESP32C61_UARTDEV_BUF_NO_USB_JTAG_SERIAL_REV_LE2 = 3;
+export declare const ESP32C61_UARTDEV_BUF_NO_USB_JTAG_SERIAL_REV_GT2 = 4;
 export declare const ESP32H2_SPI_REG_BASE = 1610625024;
 export declare const ESP32H2_BASEFUSEADDR = 1611335680;
+export declare const ESP32H2_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32H2_MACFUSEADDR: number;
 export declare const ESP32H2_SPI_USR_OFFS = 24;
 export declare const ESP32H2_SPI_USR1_OFFS = 28;
@@ -216,6 +232,7 @@ export declare const ESP32H2_UARTDEV_BUF_NO = 1082457852;
 export declare const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
 export declare const ESP32H4_SPI_REG_BASE = 1611239424;
 export declare const ESP32H4_BASEFUSEADDR = 1611339776;
+export declare const ESP32H4_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32H4_MACFUSEADDR: number;
 export declare const ESP32H4_SPI_USR_OFFS = 24;
 export declare const ESP32H4_SPI_USR1_OFFS = 28;
@@ -231,8 +248,11 @@ export declare const ESP32H4_RTC_CNTL_WDTCONFIG0_REG: number;
 export declare const ESP32H4_RTC_CNTL_WDTCONFIG1_REG: number;
 export declare const ESP32H4_RTC_CNTL_WDT_WKEY = 1356348065;
 export declare const ESP32H4_RTC_CNTL_SWD_WKEY = 1356348065;
+export declare const ESP32H4_UARTDEV_BUF_NO = 1082652032;
+export declare const ESP32H4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
 export declare const ESP32H21_SPI_REG_BASE = 1610625024;
 export declare const ESP32H21_BASEFUSEADDR = 1611350016;
+export declare const ESP32H21_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32H21_MACFUSEADDR: number;
 export declare const ESP32H21_SPI_USR_OFFS = 24;
 export declare const ESP32H21_SPI_USR1_OFFS = 28;

package/dist/const.js

@@ -75,8 +75,10 @@ export const ESP32_SPI_MISO_DLEN_OFFS = 0x2c;
 export const ESP32_SPI_W0_OFFS = 0x80;
 export const ESP32_UART_DATE_REG_ADDR = 0x60000078;
 export const ESP32_BOOTLOADER_FLASH_OFFSET = 0x1000;
+export const ESP32_APB_CTL_DATE_ADDR = 0x3ff66000 + 0x7c;
 export const ESP32S2_SPI_REG_BASE = 0x3f402000;
 export const ESP32S2_BASEFUSEADDR = 0x3f41a000;
+export const ESP32S2_EFUSE_BLOCK1_ADDR = ESP32S2_BASEFUSEADDR + 0x044;
 export const ESP32S2_MACFUSEADDR = 0x3f41a044;
 export const ESP32S2_SPI_USR_OFFS = 0x18;
 export const ESP32S2_SPI_USR1_OFFS = 0x1c;
@@ -102,6 +104,7 @@ export const ESP32S2_UARTDEV_BUF_NO = 0x3ffffd14; // Variable in ROM .bss which
 export const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2; // Value of the above indicating that USB-OTG is in use
 export const ESP32S3_SPI_REG_BASE = 0x60002000;
 export const ESP32S3_BASEFUSEADDR = 0x60007000;
+export const ESP32S3_EFUSE_BLOCK1_ADDR = ESP32S3_BASEFUSEADDR + 0x044;
 export const ESP32S3_MACFUSEADDR = 0x60007000 + 0x044;
 export const ESP32S3_SPI_USR_OFFS = 0x18;
 export const ESP32S3_SPI_USR1_OFFS = 0x1c;
@@ -128,6 +131,7 @@ export const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3; // The above var when USB-OTG i
 export const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4; // The above var when USB-JTAG/Serial is used
 export const ESP32C2_SPI_REG_BASE = 0x60002000;
 export const ESP32C2_BASEFUSEADDR = 0x60008800;
+export const ESP32C2_EFUSE_BLOCK2_ADDR = ESP32C2_BASEFUSEADDR + 0x040;
 export const ESP32C2_MACFUSEADDR = ESP32C2_BASEFUSEADDR + 0x040;
 export const ESP32C2_SPI_USR_OFFS = 0x18;
 export const ESP32C2_SPI_USR1_OFFS = 0x1c;
@@ -174,6 +178,7 @@ export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 0x60008850;
 export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 0x60008858;
 export const ESP32C5_SPI_REG_BASE = 0x60003000;
 export const ESP32C5_BASEFUSEADDR = 0x600b4800;
+export const ESP32C5_EFUSE_BLOCK1_ADDR = ESP32C5_BASEFUSEADDR + 0x044;
 export const ESP32C5_MACFUSEADDR = 0x600b4800 + 0x044;
 export const ESP32C5_SPI_USR_OFFS = 0x18;
 export const ESP32C5_SPI_USR1_OFFS = 0x1c;
@@ -182,12 +187,18 @@ export const ESP32C5_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C5_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C5_SPI_W0_OFFS = 0x58;
 export const ESP32C5_UART_DATE_REG_ADDR = 0x6000007c;
+export const ESP32C5_UART_CLKDIV_REG = 0x60000014;
 export const ESP32C5_BOOTLOADER_FLASH_OFFSET = 0x2000;
+// ESP32-C5 Crystal frequency detection registers
+export const ESP32C5_PCR_SYSCLK_CONF_REG = 0x60096110;
+export const ESP32C5_PCR_SYSCLK_XTAL_FREQ_V = 0x7f << 24;
+export const ESP32C5_PCR_SYSCLK_XTAL_FREQ_S = 24;
 // ESP32-C5 USB-JTAG/Serial detection
 export const ESP32C5_UARTDEV_BUF_NO = 0x4085f514; // Variable in ROM .bss which indicates the port in use
 export const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 export const ESP32C6_SPI_REG_BASE = 0x60003000;
 export const ESP32C6_BASEFUSEADDR = 0x600b0800;
+export const ESP32C6_EFUSE_BLOCK1_ADDR = ESP32C6_BASEFUSEADDR + 0x044;
 export const ESP32C6_MACFUSEADDR = 0x600b0800 + 0x044;
 export const ESP32C6_SPI_USR_OFFS = 0x18;
 export const ESP32C6_SPI_USR1_OFFS = 0x1c;
@@ -218,6 +229,7 @@ export const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
 export const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0020; // LP_WDT_SWD_WPROTECT_REG
 export const ESP32C61_SPI_REG_BASE = 0x60003000;
 export const ESP32C61_BASEFUSEADDR = 0x600b4800;
+export const ESP32C61_EFUSE_BLOCK1_ADDR = ESP32C61_BASEFUSEADDR + 0x044;
 export const ESP32C61_MACFUSEADDR = 0x600b4800 + 0x044;
 export const ESP32C61_SPI_USR_OFFS = 0x18;
 export const ESP32C61_SPI_USR1_OFFS = 0x1c;
@@ -227,8 +239,14 @@ export const ESP32C61_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C61_SPI_W0_OFFS = 0x58;
 export const ESP32C61_UART_DATE_REG_ADDR = 0x6000007c;
 export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-C61 USB-JTAG/Serial detection (dynamic based on chip revision)
+export const ESP32C61_UARTDEV_BUF_NO_REV_LE2 = 0x4084f5ec; // revision <= 2
+export const ESP32C61_UARTDEV_BUF_NO_REV_GT2 = 0x4084f5e4; // revision > 2
+export const ESP32C61_UARTDEV_BUF_NO_USB_JTAG_SERIAL_REV_LE2 = 3; // revision <= 2
+export const ESP32C61_UARTDEV_BUF_NO_USB_JTAG_SERIAL_REV_GT2 = 4; // revision > 2
 export const ESP32H2_SPI_REG_BASE = 0x60003000;
 export const ESP32H2_BASEFUSEADDR = 0x600b0800;
+export const ESP32H2_EFUSE_BLOCK1_ADDR = ESP32H2_BASEFUSEADDR + 0x044;
 export const ESP32H2_MACFUSEADDR = 0x600b0800 + 0x044;
 export const ESP32H2_SPI_USR_OFFS = 0x18;
 export const ESP32H2_SPI_USR1_OFFS = 0x1c;
@@ -250,6 +268,7 @@ export const ESP32H2_UARTDEV_BUF_NO = 0x4084fefc; // Variable in ROM .bss which
 export const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 export const ESP32H4_SPI_REG_BASE = 0x60099000;
 export const ESP32H4_BASEFUSEADDR = 0x600b1800;
+export const ESP32H4_EFUSE_BLOCK1_ADDR = ESP32H4_BASEFUSEADDR + 0x044;
 export const ESP32H4_MACFUSEADDR = 0x600b1800 + 0x044;
 export const ESP32H4_SPI_USR_OFFS = 0x18;
 export const ESP32H4_SPI_USR1_OFFS = 0x1c;
@@ -266,8 +285,12 @@ export const ESP32H4_RTC_CNTL_WDTCONFIG0_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x00
 export const ESP32H4_RTC_CNTL_WDTCONFIG1_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
 export const ESP32H4_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
 export const ESP32H4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+// ESP32-H4 USB-JTAG/Serial detection
+export const ESP32H4_UARTDEV_BUF_NO = 0x4087f580; // Variable in ROM .bss which indicates the port in use
+export const ESP32H4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 export const ESP32H21_SPI_REG_BASE = 0x60003000;
 export const ESP32H21_BASEFUSEADDR = 0x600b4000;
+export const ESP32H21_EFUSE_BLOCK1_ADDR = ESP32H21_BASEFUSEADDR + 0x044;
 export const ESP32H21_MACFUSEADDR = 0x600b4000 + 0x044;
 export const ESP32H21_SPI_USR_OFFS = 0x18;
 export const ESP32H21_SPI_USR1_OFFS = 0x1c;

package/dist/esp_loader.d.ts

@@ -84,9 +84,6 @@ export declare class ESPLoader extends EventTarget {
      * Detect chip type using GET_SECURITY_INFO (for newer chips) or magic value (for older chips)
      */
     detectChip(): Promise<void>;
-    /**
-     * Get chip revision for ESP32-P4
-     */
     getChipRevision(): Promise<number>;
     /**
      * Power on the flash chip for ESP32-P4 Rev 301 (ECO6)
@@ -113,12 +110,12 @@ export declare class ESPLoader extends EventTarget {
      * Reads data from the input stream and places it in the inputBuffer
      */
     readLoop(): Promise<void>;
-    sleep(ms?: number): Promise<unknown>;
     state_DTR: boolean;
     state_RTS: boolean;
     setRTS(state: boolean): Promise<void>;
     setDTR(state: boolean): Promise<void>;
     setDTRandRTS(dtr: boolean, rts: boolean): Promise<void>;
+    private runSignalSequence;
     /**
      * @name hardResetUSBJTAGSerial
      * USB-JTAG/Serial reset for Web Serial (Desktop)
@@ -134,11 +131,6 @@ export declare class ESPLoader extends EventTarget {
      * Keeps IO0=HIGH during reset so chip boots into firmware
      */
     hardResetToFirmware(): Promise<void>;
-    /**
-     * Reset to firmware mode (not bootloader) for WebUSB
-     * Keeps IO0=HIGH during reset so chip boots into firmware
-     */
-    hardResetToFirmwareWebUSB(): Promise<void>;
     /**
      * @name hardResetUnixTight
      * Unix Tight reset for Web Serial (Desktop) - sets DTR and RTS simultaneously
@@ -147,26 +139,11 @@ export declare class ESPLoader extends EventTarget {
     setRTSWebUSB(state: boolean): Promise<void>;
     setDTRWebUSB(state: boolean): Promise<void>;
     setDTRandRTSWebUSB(dtr: boolean, rts: boolean): Promise<void>;
-    /**
-     * @name hardResetUSBJTAGSerialWebUSB
-     * USB-JTAG/Serial reset for WebUSB (Android)
-     */
-    hardResetUSBJTAGSerialWebUSB(): Promise<void>;
     /**
      * @name hardResetUSBJTAGSerialInvertedDTRWebUSB
      * USB-JTAG/Serial reset with inverted DTR for WebUSB (Android)
      */
     hardResetUSBJTAGSerialInvertedDTRWebUSB(): Promise<void>;
-    /**
-     * @name hardResetClassicWebUSB
-     * Classic reset for WebUSB (Android)
-     */
-    hardResetClassicWebUSB(): Promise<void>;
-    /**
-     * @name hardResetUnixTightWebUSB
-     * Unix Tight reset for WebUSB (Android) - sets DTR and RTS simultaneously
-     */
-    hardResetUnixTightWebUSB(): Promise<void>;
     /**
      * @name hardResetClassicLongDelayWebUSB
      * Classic reset with longer delays for WebUSB (Android)
@@ -210,11 +187,6 @@ export declare class ESPLoader extends EventTarget {
      * This is an alias for rtcWdtResetChipSpecific() for backwards compatibility
      */
     watchdogReset(): Promise<void>;
-    /**
-     * Get chip revision for ESP32-C3
-     * Reads from EFUSE registers and calculates revision
-     */
-    getChipRevisionC3(): Promise<number>;
     /**
      * RTC watchdog timer reset for ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C5, ESP32-C6, and ESP32-P4
      * Uses specific registers for each chip family
@@ -222,10 +194,12 @@ export declare class ESPLoader extends EventTarget {
      */
     rtcWdtResetChipSpecific(): Promise<void>;
     /**
-     * Helper: USB-based WDT reset
-     * Returns true if WDT reset was performed, false otherwise
+     * Reset device from bootloader mode to firmware mode
+     * Automatically selects the correct reset strategy based on USB connection type
+     * @param clearForceDownloadFlag - If true, clears the force download boot flag (USB-OTG only)
+     * @returns true if port will change (USB-OTG), false otherwise
      */
-    private tryUsbWdtReset;
+    resetToFirmwareMode(clearForceDownloadFlag?: boolean): Promise<boolean>;
     hardReset(bootloader?: boolean): Promise<void>;
     /**
      * @name macAddr
@@ -271,7 +245,10 @@ export declare class ESPLoader extends EventTarget {
      * Calculate checksum of a blob, as it is defined by the ROM
      */
     checksum(data: number[], state?: number): number;
+    getC5CrystalFreqRomExpect(): Promise<number>;
+    getC5CrystalFreqDetected(): Promise<number>;
     setBaudrate(baud: number): Promise<void>;
+    private setBaudrateC5Rom;
     reconfigurePort(baud: number): Promise<void>;
     /**
      * @name syncWithTimeout
@@ -386,6 +363,22 @@ export declare class ESPLoader extends EventTarget {
      * @returns true if USB-JTAG or USB-OTG, false if external serial chip
      */
     detectUsbConnectionType(): Promise<boolean>;
+    getUsbMode(): Promise<{
+        mode: "uart" | "usb-jtag-serial" | "usb-otg";
+        uartNo: number;
+    }>;
+    /**
+     * Check if the current chip supports USB-JTAG or USB-OTG
+     * @returns true if chip has native USB support (JTAG or OTG)
+     */
+    supportsNativeUsb(): boolean;
+    /**
+     * @name _ensureStreamsReady
+     * After a hardware reset, ensure port streams are available.
+     * On WebUSB, recreates streams since they break after reset.
+     * On Web Serial, waits for streams to become available.
+     */
+    private _ensureStreamsReady;
     /**
      * @name enterConsoleMode
      * Prepare device for console mode by resetting to firmware
@@ -393,12 +386,6 @@ export declare class ESPLoader extends EventTarget {
      * @returns true if port was closed (USB-JTAG), false if port stays open (serial chip)
      */
     enterConsoleMode(): Promise<boolean>;
-    /**
-     * @name _resetToFirmwareIfNeeded
-     * Reset device from bootloader to firmware when switching to console mode
-     * Detects USB-JTAG/Serial and USB-OTG devices and performs appropriate reset
-     * @returns true if reconnect was performed, false otherwise
-     */
     /**
      * @name _clearForceDownloadBootIfNeeded
      * Read and clear the force download boot flag if it is set
@@ -407,6 +394,12 @@ export declare class ESPLoader extends EventTarget {
      * Returns true if the flag was cleared, false if it was already clear
      */
     private _clearForceDownloadBootIfNeeded;
+    /**
+     * @name _resetToFirmwareIfNeeded
+     * Reset device from bootloader to firmware when switching to console mode
+     * Detects USB-JTAG/Serial and USB-OTG devices and performs appropriate reset
+     * @returns true if reconnect was performed, false otherwise
+     */
     private _resetToFirmwareIfNeeded;
     /**
      * @name reconnectAndResume
@@ -442,6 +435,15 @@ export declare class ESPLoader extends EventTarget {
      * This is a hardware limitation - use isConsoleResetSupported() to check first.
      */
     resetInConsoleMode(): Promise<void>;
+    /**
+     * @name syncAndWdtReset
+     * Open a new bootloader port, sync with ROM (no stub, no reset strategies), and fire WDT reset.
+     * This is used for ESP32-S2 USB-OTG devices which require WDT reset to switch modes.
+     * After WDT reset the port will re-enumerate again.
+     * The user must select the new port after this method is called.
+     * @param newPort - The bootloader port selected by the user
+     */
+    syncAndWdtReset(newPort: SerialPort): Promise<void>;
     /**
      * @name drainInputBuffer
      * Actively drain the input buffer by reading data for a specified time.